Abstract: A nitride-based semiconductor device of the present invention includes: a nitride-based semiconductor multilayer structure 20 which includes a p-type semiconductor region with a surface 12 being inclined from the m-plane by an angle of not less than 1° and not more than 5°; and an electrode 30 provided on the p-type semiconductor region. The p-type semiconductor region is formed by an AlxInyGazN (where x+y+z=1, x?0, y?0, and z?0) layer 26. The electrode 30 includes a Mg layer 32 and an Ag layer 34 provided on the Mg layer 32. The Mg layer 32 is in contact with the surface 12 of the p-type semiconductor region of the semiconductor multilayer structure 20.

Abstract: Nano-engineered structures are disclosed, incorporating nanowhiskers of high mobility conductivity and incorporating pn junctions. In one embodiment, a nanowhisker of a first semiconducting material has a first band gap, and an enclosure comprising at least one second material with a second band gap encloses said nanoelement along at least part of its length, the second material being doped to provide opposite conductivity type charge carriers in respective first and second regions along the length of the of the nanowhisker, whereby to create in the nanowhisker by transfer of charge carriers into the nanowhisker, corresponding first and second regions of opposite conductivity type charge carriers with a region depleted of free carriers therebetween.

Abstract: Disclosed are a growth substrate and a light emitting device. The light emitting device includes a silicon substrate, a first buffer layer disposed on the silicon substrate and having an exposing portions of the silicon substrate, a second buffer layer covering the first buffer layer and the exposed portions of the silicon substrate, wherein the second buffer layer is formed of a material causing a eutectic reaction with the silicon substrate, a third buffer layer disposed on the second buffer layer, and a light emitting structure disposed on the third buffer layer, and the second buffer layer includes voids.

Abstract: A p-type semiconductor nanowire transistor is formed on the first semiconductor nanowire and an n-type semiconductor nanowire transistor is formed on the second semiconductor nanowire. The first and second semiconductor nanowires have a rectangular cross-sectional area with different width-to-height ratios. The type of semiconductor nanowires for each semiconductor nanowire transistor is selected such that top and bottom surfaces provide a greater on-current per unit width than sidewall surfaces in a semiconductor nanowire having a greater width-to-height ratio, while sidewall surfaces provide a greater on-current per unit width than top and bottom surfaces in the other semiconductor nanowire having a lesser width-to-height ratio. Different types of stress-generating material layers may be formed on the first and second semiconductor nanowire transistors to provide opposite types of stress, which may be employed to enhance the on-current of the first and second semiconductor nanowire transistors.

Abstract: Inorganic semiconducting materials such as silicon are used as a host matrix in which quantum dots reside to provide a radiation detector or energy converter. The quantum dot material may be disposed by incorporating materials sensitive to neutron detection such as boron-containing compounds, or the use of methods such as chemical vapor deposition or atomic layer deposition to insert the quantum dot material. Electrodes may be extended deep into the host matrix material to improve efficiency. Likewise, the host matrix may be machined to create pores in the matrix material. Further, amplification and signal-processing structures may be used in close proximity to the radiation-sensitive region of the device.

Abstract: A unique family of nanoparticles characterized by their nanometric size and cage-like shapes (hollow structures), capable of holding in their hollow cavity a variety of materials is disclosed herein.

Abstract: Nanowire-based opto-electronic devices including nanowire lasers, photodetectors and semiconductor optical amplifiers are disclosed. The devices include nanowires grown from single crystal and/or non-single surfaces. The semiconductor optical amplifiers include nanowire arrays that act as ballast lasers to amplify a signal carried by a signal waveguide. Embodiments of the nanowire lasers and photodetectors include horizontal and vertical nanowires that can provide different polarizations.

Abstract: A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device includes a group III nitride semiconductor supporting base, a GaN based semiconductor region, an active layer, and a GaN semiconductor region. The primary surface of the group III nitride semiconductor supporting base is not any polar plane, and forms a finite angle with a reference plane that is orthogonal to a reference axis extending in the direction of a c-axis of the group III nitride semiconductor. The GaN based semiconductor region, grown on the semipolar primary surface, includes a semiconductor layer of, for example, an n-type GaN based semiconductor doped with silicon. A GaN based semiconductor layer of an oxygen concentration of 5×1016 cm?3 or more provides an active layer, grown on the primary surface, with an excellent crystal quality.

Abstract: A method and device for generating terahertz radiation comprising a plurality of layers of polar crystal material operative to emit terahertz radiation; the plurality of layers comprising transport layers and divider layers, the plane of the layers being not parallel to the polar axis, the interface between the transport layers and divider layers forming boundaries at which the internal electric polarization terminates leading to charges accumulating at the boundaries, and creation of internal electric fields oriented along the polar axis.

Abstract: A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11 20) a-plane GaN layers are grown on an r-plane (1 102) sapphire substrate using MOCVD. These non-polar (11 20) a-plane GaN layers comprise templates for producing non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices.

Abstract: An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region. The insulation film is connected to an upper surface of the second channel region and an upper surface of the barrier region. The gate electrode faces the second channel region and the barrier region via the insulation film. The first channel region and the second channel region are arranged in series in a current pathway.

Abstract: Nano-engineered structures are disclosed, incorporating nanowhiskers of high mobility conductivity and incorporating pn junctions. In one embodiment, a nanowhisker of a first semiconducting material has a first band gap, and an enclosure comprising at least one second material with a second band gap encloses said nanoelement along at least part of its length, the second material being doped to provide opposite conductivity type charge carriers in respective first and second regions along the length of the of the nanowhisker, whereby to create in the nanowhisker by transfer of charge carriers into the nanowhisker, corresponding first and second regions of opposite conductivity type charge carriers with a region depleted of free carriers therebetween.

Abstract: Provided is a method for fabricating a light emitting device. The method for fabricating the light emitting device includes forming a buffer layer including a compound semiconductor in which a rare-earth element is doped on a substrate, forming a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, which are successively stacked on the buffer layer, forming a first electrode layer on the light emitting structure, removing the substrate, and forming a second electrode layer under the light emitting structure.

Abstract: A semiconductor device includes at least one semiconductor layer, a metal layer in electrical contact with the semiconductor layer, and a carbon nanotube contact layer interposed between the metal layer and the semiconductor layer. The contact layer electrically couples the metal layer to the semiconductor layer and provides a semiconductor contact having low specific contact resistance. The contact layer can be substantially optically transparent layer in at least a portion of the visible light range.

Abstract: Aligned nanowire arrays were coated with semiconductor shell layers, and optionally with noble metal nanoparticles for use as three dimensional gas sensors. The sensors show room-temperature responses to low concentrations of various gases. Arrays containing different sensor types can discriminate among different gases, based upon changes in conductivity and response times.

Abstract: A semiconductor device includes: a semiconductor base; a hetero semiconductor region which is in contact with the semiconductor base and which has a band gap different from that of the semiconductor base; a first electrode connected to the hetero semiconductor region; and a second electrode forming an ohmic contact to the semiconductor base. The hetero semiconductor region includes a laminated hetero semiconductor region formed by laminating a plurality of semiconductor layers in which crystal alignment is discontinuous at a boundary between at least two layers.

Abstract: A semiconductor device includes a first compound semiconductor layer having a two-dimensional carrier gas channel, a second compound semiconductor layer which functions as a barrier layer and is arranged above the first compound semiconductor layer, a first main electrode connected to one end of the two-dimensional carrier gas channel, and a second main electrode connected to another end of the two-dimensional carrier gas channel, these ends being separated, wherein a compound ratio of an elemental compound of the second compound semiconductor layer is different in a direction of the two-dimensional carrier gas channel between the first main electrode and the second main electrode.

Abstract: A mesoporous silica having adjustable pores is obtained to form a template and thus a three-terminal metal-oxide-semiconductor field-effect transistor (MOSFET) photodetector is obtained. A gate dielectric of a nano-structural silicon-base membrane is used as infrared light absorber in it. Thus, a semiconductor photodetector made of pure silicon having a quantum-dot structure is obtained with excellent near-infrared optoelectronic response.

Abstract: An object of the present invention is to obtain a group III nitride compound semiconductor stacked structure where a group III nitride compound semiconductor layer having good crystallinity is stably stacked on a dissimilar substrate. The group III nitride compound semiconductor stacked structure of the present invention is a group III nitride compound semiconductor stacked structure comprising a substrate having provided thereon a first layer comprising a group III nitride compound semiconductor and a second layer being in contact with the first layer and comprising a group III nitride compound semiconductor, wherein the first layer contains a columnar crystal with a definite crystal interface and the columnar crystal density is from 1×103 to 1×105 crystals/?m2.

Abstract: The present invention provides a compound semiconductor substrate, including: a single-crystal silicon substrate having a crystal face with (111) orientation; a first buffer layer which is formed on the single-crystal silicon substrate and is constituted of an AlxGa1-xN single crystal (0<x?1); a second buffer layer which is formed on the first buffer layer and is composed of a plurality of first unit layers each having a thickness of from 250 nm to 350 nm and constituted of an AlyGa1-yN single crystal (0?y<0.1) and a plurality of second unit layers each having a thickness of from 5 nm to 20 nm and constituted of an AlzGa1-zN single crystal (0.9<z?1), said pluralities of first and second unit layers having been alternately superposed; and a semiconductor device formation region which is formed on the second buffer layer and includes at least one nitride-based semiconductor single-crystal layer.

Abstract: A nanowire light emitting diode (LED) and method of emitting light employ a plasmonic mode. The nanowire LED includes a nanowire having a semiconductor junction, a shell layer coaxially surrounding the nanowire, and an insulating layer, which is plasmonically thin, isolating the shell layer from the nanowire. The shell layer supports a surface plasmon that couples to the semiconductor junction by an evanescent field. Light is generated in a vicinity of the semiconductor junction and the surface plasmon is coupled to the semiconductor junction during light generation. The coupling enhances one or both of an efficiency of light emission and a light emission rate of the LED. A method of making the nanowire LED includes forming the nanowire, providing the insulating layer on the surface of the nanowire, and forming the shell layer on the insulating layer in the vicinity of the semiconductor junction.

Abstract: An adhesion layer of a hexagonal crystal is laid on a facet an optical resonator of a nitride semiconductor laser bar having a nitride-based III-V group compound semiconductor layer, and a facet coat is laid on the adhesion layer. In this way, a structure in which the facet coat is laid on the adhesion layer is obtained.

Abstract: A semiconductor device includes: a silicon layer (12); an intermediate silicide layer (28) that is provided on the silicon layer (12), has openings, and includes barium silicide; and an upper silicide layer (14) that covers the intermediate silicide layer (28), is positioned to be in contact with the silicon layer (12) through the openings, has a higher dopant concentration than the dopant concentration of the intermediate silicide layer (28), and includes barium silicide.

Abstract: A low resistance tunnel junction that uses a natural polarization dipole associated with dissimilar materials to align a conduction band to a valence band is disclosed. Aligning the conduction band to the valence band of the junction encourages tunneling across the junction. The tunneling is encouraged, because the dipole space charge bends the energy bands, and shortens a tunnel junction width charge carriers must traverse to tunnel across the junction. Placing impurities within or near the tunnel junction that may form deep states in the junction may also encourage tunneling in a tunnel junction. These states shorten the distance charge carriers must traverse across the tunnel junction.

Abstract: A nitride semiconductor light emitting diode (LED) is disclosed. The nitride semiconductor LED can include an active layer formed between an n-type nitride layer and a p-type nitride layer, where the active layer includes two or more quantum well layers and quantum barrier layers formed in alternation, and the quantum barrier layer formed adjacent to the p-type nitride layer is thinner than the remaining quantum barrier layers. An embodiment of the invention can be used to improve optical efficiency while providing crystallinity in the active layer.

Abstract: A quantum dot electroluminescent device that includes a substrate, a quantum dot light-emitting layer disposed on the substrate, a first electrode which injects charge carriers into the quantum dot light-emitting layer, a second electrode which injects charge carriers, which have an opposite charge than the charge carriers injected by the first electrode, into the quantum dot light-emitting layer, a hole transport layer disposed between the first electrode and the quantum dot light-emitting layer, and an electron transport layer disposed between the second electrode and the quantum dot light-emitting layer, wherein the quantum dot light-emitting layer has a first surface in contact with the hole transport layer and a second surface in contact with an electron transport layer, and wherein the first surface has an organic ligand distribution that is different from an organic ligand distribution of the second surface.

Abstract: Nano-engineered structures are disclosed, incorporating nanowhiskers of high mobility conductivity and incorporating pn junctions. In one embodiment, a nanowhisker of a first semiconducting material has a first band gap, and an enclosure comprising at least one second material with a second band gap encloses said nanoelement along at least part of its length, the second material being doped to provide opposite conductivity type charge carriers in respective first and second regions along the length of the of the nanowhisker, whereby to create in the nanowhisker by transfer of charge carriers into the nanowhisker, corresponding first and second regions of opposite conductivity type charge carriers with a region depleted of free carriers therebetween. The doping of the enclosure material may be degenerate so as to create within the nanowhisker adjacent segments having very heavy modulation doping of opposite conductivity type analogous to the heavily doped regions of an Esaki diode.

Abstract: A light-emitting diode includes a substrate, a lower cladding layer, an active layer having a quantum well of a thirty percent concentration of indium on the lower cladding layer, and an upper cladding layer. A method of manufacturing light-emitting diodes includes forming a lower cladding layer on a substrate, forming an active layer on the lower cladding layer such that the active layer has a quantum well of thirty percent indium, forming an upper cladding layer on the active layer, and forming a metal cap on the upper cladding layer.

Abstract: A GaN single-crystal substrate has a substrate surface in which polarity inversion zones are included. The number density of the polarity inversion zones in the substrate surface is not more than 20 cm?2. A GaN single crystal production method includes introducing group III and V raw material gases on a substrate, and growing a GaN single crystal on the substrate. The growth temperature is within the range of not less than 1100° C. and not more than 1400° C., the group V to III raw material gas partial pressure ratio (V/III ratio) is within the range of not less than 0.4 and not more than 1, and the number density of polarity inversion zones in a surface of the substrate is not more than 20 cm?2.

Abstract: A semiconductor chip (1) comprises a p-doped region (I) having a cladding layer (18) and a contact layer (21) between which a first interlayer (19) and a second interlayer (20) are arranged. A concentration of a first material component (B) within the first and the second interlayer (19, 20) changes in such a way that the band gap varies in a range lying between the band gap of the cladding layer (18) and the band gap of the contact layer (21). A method for producing a semiconductor chip of this type is also disclosed.

Abstract: A photo detector is provided with a plurality of quantum dot layers and first conductive type contact layers provided at both sides of the plurality of quantum dot layers so as to sandwich them; a second conductive type impurity is doped in a first semiconductor layer formed between one first conductive type contact layer and a first quantum dot layer which is closest to the one first conductive type contact layer so that it results in a barrier against a carrier positioned at the one first conductive contact layer.

Abstract: A nitride semiconductor device includes an active layer formed between an n-type cladding layer and a p-type cladding layer, and a current confining layer having a conductive area through which a current flows to the active layer. The current confining layer includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The second semiconductor layer is formed on and in contact with the first semiconductor layer and has a smaller lattice constant than that of the first semiconductor layer. The third semiconductor layer is formed on and in contact with the second semiconductor layer and has a lattice constant that is smaller than that of the first semiconductor layer and larger than that of the second semiconductor layer.

Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer in which a first semiconductor layer formed of a nitride-based compound semiconductor layer having a lattice constant smaller than a lattice constant of the substrate and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate and a second semiconductor layer formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate are alternately laminated; an intermediate layer provided between the substrate and the buffer layer, the intermediate layer being formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a t

Abstract: An inventive nitride semiconductor device includes: a substrate; a first buffer layer provided on the substrate, and having a superlattice structure which includes two types of Group III nitride semiconductor sublayers having different compositions and alternately stacked in pairs; a second buffer layer provided on the first buffer layer in contact with the first buffer layer, and having a superlattice structure which includes two types of Group III nitride semiconductor sublayers having different compositions and alternately stacked in pairs; and a device operation layer of a Group III nitride semiconductor provided on the second buffer layer; wherein an average lattice constant LC1 of the first buffer layer, an average lattice constant LC2 of the second buffer layer and an average lattice constant LC3 of the device operation layer satisfy the following expression (1): LC1<LC2<LC3??(1)

Abstract: Disclosed herein is a structure and method for manipulating a spin state, regarded as important in the field of spintronics, by which the distribution of spin-up and spin-down states of carriers in a hybrid double quantum disk structure, composed of a diluted magnetic semiconductor and a ferroelectric compound semiconductor, is manipulated through dipole polarization switching of the ferroelectric compound semiconductor without a change in bias. Giant Zeeman splitting properties of the diluted magnetic semiconductor and polarization properties of the ferroelectric compound semiconductor are applied in conjunction with the Pauli exclusion principle, thus enabling the combination or separation of carriers in spin-up and spin-down states in the hybrid double quantum disk structure. The spin relaxation time in the structure is on the order of microseconds, during which the spin state is well-defined, and therefore, the structure can be applied to microprocessors having gigahertz clock speeds.

Abstract: A method of producing silicon nanowires includes providing a substrate in the form of a doped material; formulating an etching solution; and applying an appropriate current density for an appropriate length of time. Related structures and devices composed at least in part from silicon nanowires are also described.

Abstract: Nanowire-based opto-electronic devices including nanowire lasers, photodetectors and semiconductor optical amplifiers are disclosed. The devices include nanowires grown from single crystal and/or non-single surfaces. The semiconductor optical amplifiers include nanowire arrays that act as ballast lasers to amplify a signal carried by a signal waveguide. Embodiments of the nanowire lasers and photodetectors include horizontal and vertical nanowires that can provide different polarizations.

Abstract: A nitride semiconductor laser device uses a substrate with low defect density, contains reduced strains inside a nitride semiconductor film, and thus offers a satisfactorily long useful life. On a GaN substrate (10) with a defect density as low as 106 cm?2 or less, a stripe-shaped depressed portion (16) is formed by etching. On this substrate (10), a nitride semiconductor film (11) is grown, and a laser stripe (12) is formed off the area right above the depressed portion (16). With this structure, the laser stripe (12) is free from strains, and the semiconductor laser device offers a long useful life. Moreover, the nitride semiconductor film (11) develops reduced cracks, resulting in a greatly increased yield rate.

Abstract: A device disclosed herein includes a first layer, a second layer, and a first plurality of nanowires established between the first layer and the second layer. The first plurality of nanowires is formed of a first semiconductor material. The device further includes a third layer, and a second plurality of nanowires established between the second and third layers. The second plurality of nanowires is formed of a second semiconductor material having a bandgap that is the same as or different from a bandgap of the first semiconductor material.

Abstract: A boron phosphide-based semiconductor light-emitting device includes a substrate of silicon single crystal, a first cubic boron phosphide-based semiconductor layer that is provided on a surface of the substrate and contains twins, a light-emitting layer that is composed of a hexagonal Group III nitride semiconductor and provided on the first cubic boron phosphide-based semiconductor layer and a second cubic boron phosphide-based semiconductor layer that is provided on the light-emitting layer, contains twins and has a conduction type different from that of the first cubic boron phosphide-based semiconductor layer.

Abstract: A photodetector for detecting infrared light in a wavelength range of 3-25 ?m is disclosed. The photodetector has a mesa structure formed from semiconductor layers which include a type-II superlattice formed of alternating layers of InAs and InxGa1-xSb with 0?x?0.5. Impurity doped regions are formed on sidewalls of the mesa structure to provide for a lateral conduction of photo-generated carriers which can provide an increased carrier mobility and a reduced surface recombination. An optional bias electrode can be used in the photodetector to control and vary a cut-off wavelength or a depletion width therein. The photodetector can be formed as a single-color or multi-color device, and can also be used to form a focal plane array which is compatible with conventional read-out integrated circuits.

Abstract: According to an embodiment of the present invention, a transistor includes a source electrode, a drain electrode, a graphene film formed between the source electrode and the drain electrode and having a first region and a second region, and a gate electrode formed on the first region and the second region of the graphene film via a gate insulating film. The graphene film functions as a channel. A Schottky junction is formed at a junction between the first region and the second region. The first region has a conductor property, and the second region is adjacent to the drain electrode side of the first region and has a semiconductor property.

Abstract: A method for patterning nanostructures in a semiconductor heterostructure, which has at least a first layer and a second layer, wherein the first layer has a first surface and an opposite, second surface, the second layer has a first surface and an opposite, second surface, and the first layer is deposited over the second layer such that the second surface of the first layer is proximate to the first surface of the second layer. The method includes the steps of making indentations in a pattern on the first surface of the first layer of the semiconductor heterostructure; bonding the semiconductor heterostructure to a support substrate such that the first surface of the first layer of the semiconductor heterostructure is faced to the support substrate; etching off the second layer of the semiconductor heterostructure; and depositing a third layer over the second surface of the first layer of the semiconductor heterostructure.

Abstract: A nitride semiconductor light emitting device includes: a substrate for growing nitride semiconductor of a hexagonal crystal structure; a first nitride semiconductor layer of a first conductivity type formed above the substrate; an active layer formed on the first nitride semiconductor layer for emitting light when current flows; a second nitride semiconductor layer of a second conductivity type opposite to the first conductivity type formed on the active layer; texture formed above at least a partial area of the second nitride semiconductor layer and having a plurality of protrusions of a pyramid shape, each of the protrusions including a lower layer made of nitride semiconductor doped with impurities of the second conductivity type and an upper layer made of nitride semiconductor not intentionally doped with impurities; and a transparent electrode covering surfaces of the second nitride semiconductor layer and the texture.

Abstract: Techniques for combining nanotechnology with photovoltaics are provided. In one aspect, a method of forming a photovoltaic device is provided comprising the following steps. A plurality of nanowires are formed on a substrate, wherein the plurality of nanowires attached to the substrate comprises a nanowire forest. In the presence of a first doping agent and a first volatile precursor, a first doped semiconductor layer is conformally deposited over the nanowire forest. In the presence of a second doping agent and a second volatile precursor, a second doped semiconductor layer is conformally deposited over the first doped layer. The first doping agent comprises one of an n-type doping agent and a p-type doping agent and the second doping agent comprises a different one of the n-type doping agent and the p-type doping agent from the first doping agent. A transparent electrode layer is deposited over the second doped semiconductor layer.

Abstract: Nano-engineered structures are disclosed, incorporating nanowhiskers of high mobility conductivity and incorporating pn junctions. In one embodiment, a nanowhisker of a first semiconducting material has a first band gap, and an enclosure comprising at least one second material with a second band gap encloses said nanoelement along at least part of its length, the second material being doped to provide opposite conductivity type charge carriers in respective first and second regions along the length of the of the nanowhisker, whereby to create in the nanowhisker by transfer of charge carriers into the nanowhisker, corresponding first and second regions of opposite conductivity type charge carriers with a region depleted of free carriers therebetween. The doping of the enclosure material may be degenerate so as to create within the nanowhisker adjacent segments having very heavy modulation doping of opposite conductivity type analogous to the heavily doped regions of an Esaki diode.

Abstract: A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

Abstract: The present invention discloses a light-emitting semiconductor device, includes: a first electrode that is made of a high reflective metal; a second electrode; a tunnel junction layer coupling to the first electrode through a first ohmic contact and generating a tunnel current by applying a reverse bias voltage between the first electrode and the second electrode; a light-emitting layer provided between the tunnel junction layer and the second electrode.

Abstract: A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11 20) a-plane GaN layers are grown on an r-plane (1 102) sapphire substrate using MOCVD. These non-polar (11 20) a-plane GaN layers comprise templates for producing non-polar (Al, B, In, Ga)N quantum well and heterostructure materials and devices.

Abstract: A light emitting device of the invention includes an electron transporting layer, a hole transporting layer provided mutually facing the electron transporting layer with a distance between the hole transporting layer and the electron transporting layer, a phosphor layer having a layer of a plurality of semiconductor fine particles sandwiched between the electron transporting layer and the hole transporting layer, a first electrode provided facing the electron transporting layer and connected electrically, and a second electrode provided facing the hole transporting layer and connected electrically: in which the semiconductor fine particles composing the phosphor layer have a p-type part and an n-type part inside of the particles and have a pn-junction in the interface of the p-type part and the n-type part and are arranged in a manner that the p type part is partially brought into contact with the hole transporting layer and at the same time, the n type part is partially brought into contact with the electron