Abstract: Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits.

Abstract: Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits.

Abstract: The present invention relates to a horizontal biosensor, comprising a reduced graphene oxide layer formed on a substrate; a molecular linker formed on the reduced graphene oxide layer; and a metal nanoparticle layer formed on the molecular linker.

Abstract: Semiconductor device structures and methods of fabricating semiconductor devices structures are provided that include a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate and/or a conductive layer. The semi-insulating or insulating GaN epitaxial layer has a thickness of at least about 4 ?m. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive SiC substrate and an insulating or semi-insulating GaN epitaxial layer on the conductive SiC substrate. The GaN epitaxial layer has a thickness of at least about 4 ?m.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

Abstract: An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire.

Abstract: A light emitting diode device includes a first diode structure, a second diode structure on the first diode structure, and a conductive junction between the first diode structure and the second diode structure. The conductive junction includes a transparent conductive layer between the first diode structure and the second diode structure. Low resistance heterojunction tunnel junction structures including delta-doped layers are also disclosed.

Abstract: An epitaxial structure is provided. The epitaxial structure comprises a substrate, a carbon nanotube layer and an epitaxial layer stacked in that order. The substrate has an epitaxial growth surface and defines a plurality of first grooves and first bulges on the epitaxial growth surface. The carbon nanotube layer covers the epitaxial growth surface, wherein a first part of the carbon nanotube layer is attached on top surface of the first bulges, and a second part of the carbon nanotube layer is attached on bottom surface and side surface of the first grooves. The epitaxial layer is formed on the epitaxial growth surface, and the carbon nanotube layer is sandwiched between the epitaxial layer and the substrate.

Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.

Abstract: A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits lights when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device.

Abstract: The present invention provides a substrate (1) with a bulk layer (3) and a buffer layer (4) having a thickness of less than 2 ?m arranged on the bulk layer (3) for growth of a multitude of nanowires (2) oriented in the same direction on a surface (5) of the buffer layer (4). A nanowire structure, a nanowire light emitting diode comprising the substrate (1) and a production method for fabricating the nanowire structure is also provided. The production method utilizes non-epitaxial methods for forming the buffer layer (4).

Abstract: A LED device is provided. The LED device has a conductive carrier substrate, a light-emitting structure, a plurality of pillar structures, a dielectric layer, a first electrode and a second electrode. The light-emitting structure is located on the conductive carrier substrate. The pillar structures are located on the light-emitting structure. The dielectric layer is to cover a sidewall of the pillar structure. The first electrode is located over the pillar structure, and the second electrode is located on the conductive carrier substrate.

Abstract: A semiconductor device includes: a silicon layer (12); an intermediate silicide layer (28) that is provided on the silicon layer (12), has openings, and includes barium silicide; and an upper silicide layer (14) that covers the intermediate silicide layer (28), is positioned to be in contact with the silicon layer (12) through the openings, has a higher dopant concentration than the dopant concentration of the intermediate silicide layer (28), and includes barium silicide.

Abstract: Disclosed are a growth substrate and a light emitting device. The light emitting device includes a silicon substrate, a first buffer layer disposed on the silicon substrate and having an exposing portions of the silicon substrate, a second buffer layer covering the first buffer layer and the exposed portions of the silicon substrate, wherein the second buffer layer is formed of a material causing a eutectic reaction with the silicon substrate, a third buffer layer disposed on the second buffer layer, and a light emitting structure disposed on the third buffer layer, and the second buffer layer includes voids.

Abstract: A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor comprises: a semiconductor substrate and a drain layer formed in the semiconductor substrate, in which the drain layer is first type heavily doped; an epitaxial layer formed on the drain layer, with an isolation region formed in the epitaxial layer; a buried layer formed in the epitaxial layer, in which the buried layer is second type lightly doped; a source formed in the buried layer, in which the source is second type heavily doped; a gate dielectric layer formed on the epitaxial layer, and a gate formed on the gate dielectric layer; and a source metal contact layer formed on the source, and a drain metal contact layer formed under the drain layer.

Abstract: According to one embodiment, an information recording and reproducing device includes a stacked body. The stacked body includes a first layer, a second layer and a recording layer provided between the first layer and the second layer. The recording layer includes a phase-change material and a crystal nucleus. The phase-change material is capable of reversely changing between a crystal state and an amorphous state by a current supplied via the first layer and the second layer. The crystal nucleus is provided in contact with the phase-change material and includes a crystal nucleus material having a crystal structure identical to a crystal structure of the crystal state of the phase-change material, and a crystal nucleus coating provided on a surface of the crystal nucleus material and having a composition different from a composition of the crystal nucleus material.

Abstract: Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.

Abstract: There is provided a surface treatment method of a group III nitride semiconductor including: providing a group III nitride semiconductor including a first surface having a group III polarity and a second surface opposing the first surface and having a nitrogen polarity; and irradiating a laser beam onto the second surface to change the nitrogen polarity of the second surface to the group III polarity.

Abstract: A method of forming a p-type compound semiconductor layer includes increasing a temperature of a substrate loaded into a reaction chamber to a first temperature. A source gas of a Group III element, a source gas of a p-type impurity, and a source gas of nitrogen containing hydrogen are supplied into the reaction chamber to grow the p-type compound semiconductor layer. Then, the supply of the source gas of the Group III element and the source gas of the p-type impurity is stopped and the temperature of the substrate is lowered to a second temperature. The supply of the source gas of nitrogen containing hydrogen is stopped and drawn out at the second temperature, and the temperature of the substrate is lowered to room temperature using a cooling gas. Accordingly, hydrogen is prevented from bonding to the p-type impurity in the p-type compound semiconductor layer.

Abstract: Quantum dot (QD) gate FETs and the use of quantum dot (QD) gate FETs for the purpose of sensing analytes and proteins is disclosed and described. Analytes, proteins, miRNAs, and DNAs functionalized to the QDs change the charge density in the gate and hence the current-voltage characteristics. In one embodiment, QD-FETs, such as 3-state configurations, the binding of chemical and biological species change the drain current-gate voltage characteristics resulting in detection. In one embodiment, DNA sensing is done by its binding to an existing reference DNA functionalized on to quantum dots which are located in the gate region of the FET.

Abstract: Various embodiments provide materials and methods for integrating exemplary heterostructure field-effect transistor (HFET) driver circuit or thyristor driver circuit with LED structures to reduce or eliminate resistance and/or inductance associated with their conventional connections.

Abstract: A III-nitride semiconductor device which includes a charged gate insulation body.

Abstract: One or more circuit elements such as silicon diodes, resistors, capacitors, and inductors are disposed between the semiconductor structure of a semiconductor light emitting device and the connection layers used to connect the device to an external structure. In some embodiments, the n-contacts to the semiconductor structure are distributed across multiple vias, which are isolated from the p-contacts by one or more dielectric layers. The circuit elements are formed in the contacts-dielectric layers-connection layers stack.

Abstract: Growth methods for planar, non-polar, Group-III nitride films are described. The resulting films are suitable for subsequent device regrowth by a variety of growth techniques.

Abstract: Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The discussed electronic and photonic devices and circuits rely on the nanotube arrays grown on a variety of substrates, such as glass or Si wafer. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for a large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on Si-wafers, the CNT-based devices can be combined with the Si circuit elements, thus producing hybrid Si-CNT devices and circuits.

Abstract: Exemplary embodiments provide high-quality layered semiconductor devices and methods for their fabrication. The high-quality layered semiconductor device can be formed in planar with low defect densities and with strain relieved through a plurality of arrays of misfit dislocations formed at the interface of highly lattice-mismatched layers of the device. The high-quality layered semiconductor device can be formed using various materials systems and can be incorporated into various opto-electronic and electronic devices. In an exemplary embodiment, an emitter device can include monolithic quantum well (QW) lasers directly disposed on a SOI or silicon substrate for waveguide coupled integration. In another exemplary embodiment, a superlattice (SL) photodetector and its focal plane array can include a III-Sb active region formed over a large GaAs substrate using SLS technologies.

Abstract: According to example embodiments, an electrode structure includes a graphene layer on a semiconductor layer and an electrode containing metal on the graphene layer. A field effect transistor (FET) may include the electrode structure.

Abstract: An inventive nitride semiconductor device includes: a substrate; a first buffer layer provided on the substrate, and having a superlattice structure which includes two types of Group III nitride semiconductor sublayers having different compositions and alternately stacked in pairs; a second buffer layer provided on the first buffer layer in contact with the first buffer layer, and having a superlattice structure which includes two types of Group III nitride semiconductor sublayers having different compositions and alternately stacked in pairs; and a device operation layer of a Group III nitride semiconductor provided on the second buffer layer; wherein an average lattice constant LC1 of the first buffer layer, an average lattice constant LC2 of the second buffer layer and an average lattice constant LC3 of the device operation layer satisfy the following expression (1): LC1<LC2<LC3??(1).

Abstract: A nitride-based semiconductor light-emitting device having enhanced efficiency of carrier injection to a well layer is provided. The nitride-based semiconductor light-emitting device comprises a hexagonal gallium nitride-based semiconductor substrate 5, an n-type gallium nitride-based semiconductor region 7 disposed on the principal surface S1 of the substrate 5, a light-emitting layer 11 having a single-quantum-well structure disposed on the n-type gallium nitride-based semiconductor region 7, and a p-type gallium nitride-based semiconductor region 19 disposed on the light-emitting layer 11. The light-emitting layer 11 is disposed between the n-type gallium nitride-based semiconductor region 7 and the p-type gallium nitride-based semiconductor region 19. The light-emitting layer 11 includes a well layer 15 and barrier layers 13 and 17. The well layer 15 comprises InGaN.

Abstract: A semiconductor apparatus includes a cubic silicon carbide single crystal thin film of a multilayer structure including an AlxGa1-xAs (0.6>x?0) layer and a cubic silicon carbide single crystal layer. The apparatus also includes a substrate on which a metal layer is formed. The multilayer structure is bonded to a surface of the metal layer with the AlxGa1-xAs (0.6>x?0) in direct contact with the metal layer.

Abstract: A memory includes a first tunneling field effect transistor including a first drain and a first source, the first drain coupled to a first resistive memory element. The memory includes a second tunneling field effect transistor including a second drain and sharing the first source, the second drain coupled to a second resistive memory element. The memory includes a first region coupled to the first source for providing a source node.

Abstract: A ZnSnO3/ZnO nanowire, a method of forming a ZnSnO3/ZnO nanowire, a nanogenerator including a ZnSnO3/ZnO nanowire, a method of forming a ZnSnO3 nanowire, and a nanogenerator including a ZnSnO3 nanowire are provided. The ZnSnO3/ZnO nanowire includes a core and a shell that surrounds the core, wherein the core includes ZnSnO3 and the shell includes ZnO.

Abstract: Implementations of quantum well photodetectors are provided. In one embodiment, a quantum structure includes a first barrier layer, a well layer located on the first barrier layer, and a second barrier layer located on the well layer. A metal layer is located adjacent to the quantum structure.

Abstract: A gain-clamped semiconductor optical amplifier comprises: at least one first surface; at least one second surface, each second surface facing and electrically isolated from a respective first surface; a plurality of nanowires connecting each opposing pair of the first and second surfaces in a bridging configuration; and a signal waveguide overlapping the nanowires such that an optical signal traveling along the signal waveguide is amplified by energy provided by electrical excitation of the nanowires.

Abstract: Various embodiments provide non-planar nanowires, nanowire arrays, and nanowire networks as well as methods of their formation and applications. The non-planar nanowires and their arrays can be formed in a controlled manner on surfaces having a non-planar orientation. In embodiments, two or more adjacent nanowires from different surfaces can grow to merge together forming one or more nanowire branches and thus forming a nanowire network. In embodiments, the non-planar nanowires and nanowire networks can be used for cantilever oscillation, switching and transistor actions.

Abstract: A photosensitive device (100), the photosensitive device (100) comprising a substrate (101) and a plurality of vertically aligned nanowire diodes (102 to 105) provided on and/or in the substrate (101).

Abstract: The invention relates to a method for producing a layer structure in an electronic device, especially in an organic light emitting device, the method comprising a step of producing the layer structure as a composite layer structure with free charge carriers generated by charge transfer between a first material and a second material, wherein the composite layer structure is provided as a stack of at least three non-mixed sub-layers made of the first material and the second material, respectively, wherein within the stack of the at least three non-mixed sub-layers each first material sub-layer is followed by an adjacent second material sub-layer and each second material sub-layer is followed by an adjacent first material sub-layer, and wherein the first material and the second material are selected to form a host-dopant material system for the electrical doping. The invention also relates to an electronic device.

Abstract: An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire.

Abstract: A device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads and a gate including a gate conductor surrounding the nanowire and a fully silicided material surrounding the gate conductor to radially strain the nanowire.

Abstract: The present invention is directed to a novel synthetic method for producing nanoscale heterostructures, and particularly nanoscale heterostructure particles, rods and sheets, that comprise a metal core and a monocrystalline semiconductor shell with substantial lattice mismatches between them. More specifically, the invention concerns the use of controlled soft acid-base coordination reactions between molecular complexes and colloidal nanostructures to drive the nanoscale monocrystalline growth of the semiconductor shell with a lattice structure incommensurate with that of the core. The invention also relates to more complex hybrid core-shell structures that exhibit azimuthal and radial nano-tailoring of structures. The invention is additionally directed to the use of such compositions in semiconductor devices.

Abstract: A surface plasmon-generating apparatus includes an active layer including an n-type region formed on one side and a p-type region formed on the other side, the n-type region and the p-type region being in contact with each other to form a pn junction therebetween; a first barrier layer in contact with a first surface of the active layer; a second barrier layer in contact with a second surface of the active layer, the second surface being opposite the first surface; and a metal body disposed above the pn junction of the active layer with the second barrier layer and an insulating layer therebetween.

Abstract: The present invention provides a method of forming a transistor. The method includes forming a first layer of a first semiconductor material above an insulation layer. The first semiconductor material is selected to provide high mobility to a first carrier type. The method also includes forming a second layer of a second semiconductor material above the first layer of semiconductor material. The second semiconductor material is selected to provide high mobility to a second carrier type opposite the first carrier type. The method further includes forming a first masking layer adjacent the second layer and etching the second layer through the first masking layer to form at least one feature in the second layer. Each feature in the second layer forms an inverted-T shape with a portion of the second layer.

Abstract: A semiconducting device includes a piezoelectric structure that has a first end and an opposite second end. A first conductor is in electrical communication with the first end and a second conductor is in electrical communication with the second end so as to form an interface therebetween. A force applying structure is configured to maintain an amount of strain in the piezoelectric member sufficient to generate a desired electrical characteristic in the semiconducting device.

Abstract: The invention inter alia relates to a method of fabricating a layer assembly comprising the steps of: arranging a first layer on top of a carrier; arranging a second layer on top of the first layer; locally modifying the material of the buried first layer and providing at least one modified section in the first layer, wherein the modified material changes or induces mechanical strain in a portion of the second layer which is arranged above the at least one modified section; after locally modifying the material of the buried first layer, depositing a third material on top of the second layer, at least one characteristic of the third material being sensitive to the local mechanical strain in the second layer.

Abstract: Provided is a nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed above the first nitride semiconductor layer; and a delta doped second nitride semiconductor layer formed above the active layer. According to the present invention, the optical power of the nitride semiconductor light emitting device is enhanced, optical power down phenomenon is improved and reliability against ESD (electro static discharge) is enhanced.

Abstract: A photosensitive optoelectronic device (1) comprises a plurality of organic semiconductor sub-cells (10, 11, 12, 13) arranged in a stack between electrodes (3, 5), each sub-cell comprising donor material (14, 16, 23, 25) and acceptor material (15, 17, 24, 26) providing a heterojunction. There is a recombination layer (19, 22, 28) between adjacent sub-cells. The sub-cells are arranged in two groups (20, 29). The sub-cells (10, 11; 12, 13) within a group (20; 29) are responsive over substantially the same part of the light spectrum. The groups (20, 29) differ substantially from each other in respect of the parts of the light spectrum over which their respective sub-cells are responsive.

Abstract: A semiconductor light-emitting element includes a semiconductor laminated body including a first conductivity type layer, a light-emitting layer and a second conductivity type layer in this order, a transparent electrode formed on the first conductivity type layer and comprising an oxide, and an auxiliary electrode formed between the first conductivity type layer and the transparent electrode, the auxiliary electrode having a higher reflectivity to light emitted from the light-emitting layer, a larger contact resistance with the first conductivity type layer and a smaller sheet resistance than the transparent electrode.

Abstract: A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.

Abstract: Embodiments of the present disclosure relate to a novel semiconductor. In one aspect, the semiconductor may include a transparent layer having a first surface, a first doped layer, a second doped layer, and an active layer. The first doped layer may be formed over the first surface of the transparent layer and have a plurality of first-type electrodes formed thereon. The second doped layer may be formed over the first surface of the transparent layer and have a plurality of second-type electrodes formed thereon. The active layer may be formed between the first doped layer and the second doped layer. A distance between at least one of the first-type electrodes and a nearest other one of the first-type electrodes may be greater than each of respective distances between the at least one of the first-type electrodes and more than two of the second-type electrodes.

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.