Heterojunction Patents (Class 257/12)
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Patent number: 9761686Abstract: Techniques are provided that can impart sufficient electrical conductivity to a semiconductor crystal exhibiting low doping efficiency for silicon atoms, such as InGaAs, by implanting only a small amount of silicon atoms. Such a semiconductor wafer may include a first semiconductor crystal layer, a second semiconductor crystal layer exhibiting a conductivity type that is different from the first layer, a third semiconductor crystal layer exhibiting the conductivity type of the first layer and having a larger band gap than the second semiconductor crystal layer, and a fourth semiconductor crystal layer exhibiting the conductivity type of the first layer and having a smaller band gap than the third semiconductor crystal layer. The fourth semiconductor crystal layer contains a first element that generates a first carrier of a corresponding conductivity type and a second element that generates a second carrier of a corresponding conductivity type.Type: GrantFiled: June 20, 2016Date of Patent: September 12, 2017Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Sadanori Yamanaka, Naohiro Nishikawa, Tsuyoshi Nakano
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Patent number: 9755093Abstract: Disclosed are a photoelectronic device using a hybrid structure of silica nanoparticles and graphene quantum dots and a method of manufacturing the same. The photoelectronic device according to the present disclosure has a hybrid structure including graphene quantum dots (GQDs) bonded to surfaces of silica nanoparticles (SNPs), thereby increasing energy transfer efficiency.Type: GrantFiled: July 13, 2016Date of Patent: September 5, 2017Assignee: UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITYInventors: Suk Ho Choi, Sung Kim
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Patent number: 9748976Abstract: Systems and methods are provided for quantum error correction. A quantum system includes an array of qubits configured to store an item of quantum information. The array of qubits includes a plurality of data qubits and a plurality of measurement qubits configured to extract a syndrome representing agreement among the plurality of data qubits. The quantum system further includes an integrated circuit comprising validation logic configured to determine if the syndrome is valid, decoding logic configured to determine evaluate the syndrome to determine location of errors within the plurality of data qubits, and an error register configured to store locations of the determined errors.Type: GrantFiled: May 22, 2015Date of Patent: August 29, 2017Assignee: Northrop Grumman Systems CorporationInventors: Ofer Naaman, Bryan K. Eastin
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Patent number: 9735292Abstract: A Schottky diode is formed on a silicon support. A non-doped GaN layer overlies the silicon support. An AlGaN layer overlies the non-doped GaN layer. A first metallization forming an ohmic contact and a second metallization forming a Schottky contact are provided in and on the AlGaN layer. First vias extend from the first metallization towards the silicon support. Second vias extend from the second metallization towards an upper surface.Type: GrantFiled: February 29, 2016Date of Patent: August 15, 2017Assignee: STMicroelectronics (Tours) SASInventor: Arnaud Yvon
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Patent number: 9735547Abstract: Optical devices having a structured active region configured for selected wavelengths of light emissions are disclosed.Type: GrantFiled: December 15, 2016Date of Patent: August 15, 2017Assignee: Soraa Laser Diode, Inc.Inventor: James W. Raring
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Patent number: 9722165Abstract: A thermoelectric pixel includes a micro-platform and a device layer having one or more support layers suspended at a perimeter thereof. The pixel includes structures which reduce thermal conductivity and improve platform planarity. In embodiments providing an infrared sensor, carbon nanotubes are used to enhance infrared absorption into the sensor pixel. In other embodiments, the pixel provides a thermoelectric energy harvester.Type: GrantFiled: March 29, 2016Date of Patent: August 1, 2017Inventor: William N. Carr
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Patent number: 9722058Abstract: This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base. For instance, the doping spike can be disposed within half of the thickness of the collector from the interface between the collector and the base. Such bipolar transistors can be implemented, for example, in power amplifiers.Type: GrantFiled: June 29, 2016Date of Patent: August 1, 2017Assignee: Skyworks Solutions, Inc.Inventors: Peter J. Zampardi, Jr., Kai Hay Kwok
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Patent number: 9647084Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.Type: GrantFiled: December 11, 2015Date of Patent: May 9, 2017Assignee: FUJITSU LIMITEDInventors: Shirou Ozaki, Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki
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Patent number: 9620618Abstract: A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; forming a barrier layer between the channel layer and the substrate; forming a recess that extends into the barrier layer through the channel layer; and forming a source layer in the recess.Type: GrantFiled: February 4, 2016Date of Patent: April 11, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin
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Patent number: 9614056Abstract: One illustrative method disclosed herein includes, among other things, forming a fin that is positioned above and vertically spaced apart from an upper surface of a semiconductor substrate, the fin having an upper surface, a lower surface and first and second side surfaces, wherein an axis of the fin in a height direction of the fin is oriented substantially parallel to the upper surface of the substrate, and wherein a first side surface of the fin contacts a first insulating material, forming a gate structure around the upper surface, the second side surface and the lower surface of the fin, and forming a gate contact structure that is conductively coupled to the gate structure.Type: GrantFiled: October 28, 2014Date of Patent: April 4, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Andreas Knorr
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Patent number: 9608094Abstract: A Tunnel Field-Effect Transistor (TFET) device is provided comprising at least one heterosection between the source region and the channel region. The at least one heterosection has a low dielectric constant and thickness below 10 nm. Additionally a pocket region and another heterosection may be added in between the at least one heterosection and the channel region.Type: GrantFiled: August 31, 2015Date of Patent: March 28, 2017Assignee: IMEC VZWInventors: Anne S. Verhulst, Geoffrey Pourtois, Rita Rooyackers
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Patent number: 9608075Abstract: A compound semiconductor device includes a first III-nitride buffer layer doped with carbon and/or iron, a second III-nitride buffer layer above the first III-nitride buffer layer and doped with carbon and/or iron, a first III-nitride device layer above the second III-nitride buffer layer, and a second III-nitride device layer above the first III-nitride device layer and having a different band gap than the first III-nitride device layer. A two-dimensional charge carrier gas arises along an interface between the first and second III-nitride device layers. The first III-nitride buffer layer has an average doping concentration of carbon and/or iron which is greater than that of the second III-nitride buffer layer. The second III-nitride buffer layer has an average doping concentration of carbon and/or iron which is comparable to or greater than that of the first III-nitride device layer. A method of manufacturing the compound semiconductor device is described.Type: GrantFiled: June 3, 2016Date of Patent: March 28, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Jianwei Wan, Mihir Tungare, Peter Kim, Seong-Eun Park, Scott Nelson, Srinivasan Kannan
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Patent number: 9601529Abstract: A nanowire array is described herein. The nanowire array comprises a substrate and a plurality of nanowires extending essentially vertically from the substrate; wherein: each of the nanowires has uniform chemical along its entire length; a refractive index of the nanowires is at least two times of a refractive index of a cladding of the nanowires. This nanowire array is useful as a photodetector, a submicron color filter, a static color display or a dynamic color display.Type: GrantFiled: February 26, 2015Date of Patent: March 21, 2017Assignees: ZENA TECHNOLOGIES, INC., PRESIDENT AND FELLOWS OF HARVARD COLLEGEInventors: Kwanyong Seo, Munib Wober, Paul Steinvurzel, Ethan Schonbrun, Yaping Dan, Kenneth Crozier
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Patent number: 9568750Abstract: An optical modulator includes an input port, a first waveguide region comprising silicon and optically coupled to the input port, and a waveguide splitter optically coupled to the first waveguide region and having a first output and a second output. The optical modulator also includes a first phase adjustment section optically coupled to the first output and comprising a first III-V diode and a second phase adjustment section optically coupled to the second output and comprising a second III-V diode. The optical modulator further includes a waveguide coupler optically coupled to the first phase adjustment section and the second phase adjustment section, a second waveguide region comprising silicon and optically coupled to the waveguide coupler, and an output port optically coupled to the second waveguide region.Type: GrantFiled: April 12, 2013Date of Patent: February 14, 2017Assignee: Skorpios Technologies, Inc.Inventors: John Y. Spann, Derek Van Orden, Amit Mizrahi, Timothy Creazzo, Elton Marchena, Robert J. Stone, Stephen B. Krasulick
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Patent number: 9570300Abstract: A strain relaxed buffer layer of a second semiconductor material and of a second lattice constant and containing misfit dislocation defects and threading dislocation defects is formed atop a surface of a first semiconductor material of a first lattice constant that differs from the second lattice constant. The surface of the first semiconductor material includes at least one recessed region and adjoining non-recessed regions. An anneal is then performed on the strain relaxed buffer layer to propagate and amass the misfit dislocation defects and threading dislocation defects at a sidewall of each of the non-recessed regions of the first semiconductor material.Type: GrantFiled: February 8, 2016Date of Patent: February 14, 2017Assignee: International Business Machines CorporationInventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
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Patent number: 9553426Abstract: Optical devices having a structured active region configured for selected wavelengths of light emissions are disclosed.Type: GrantFiled: May 16, 2016Date of Patent: January 24, 2017Assignee: SORAA LASER DIODE, INC.Inventor: James W. Raring
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Patent number: 9536967Abstract: A device includes a III-N layer having an upper side and a lower side, the lower side being opposite the upper side, and at least one conductive contact on the upper side of the III-N layer, the conductive contact extending into the III-N layer. The conductive contact comprises a top side facing away from the lower side of the III-N layer, and a bottom side facing towards the lower side of the III-N layer. The bottom side includes a first end and a second end opposite the first end, a first side rising from the first end to an intermediate point closer to the top side than the first end, and a second side falling from the intermediate point to the second end further from the top side than the intermediate point.Type: GrantFiled: December 16, 2014Date of Patent: January 3, 2017Assignee: Transphorm Inc.Inventors: Toshihide Kikkawa, Kenji Kiuchi, Tsutomu Hosoda, Masahito Kanamura, Akitoshi Mochizuki
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Patent number: 9523815Abstract: A thyristor may include a first optical waveguide segment in a semiconductor material, having first and second complementary longitudinal parts of opposite conductivity types configured to form a longitudinal bipolar junction therebetween. The thyristor may further include a second optical waveguide segment in a semiconductor material, adjacent the first waveguide segment and having first and second complementary longitudinal parts of opposite conductivity types configured to form a longitudinal bipolar junction therebetween. A transverse bipolar junction may be between the second longitudinal portions of the first and second waveguide segments. An electrical insulator may separate each of the first longitudinal portions from the waveguide segment adjacent thereto.Type: GrantFiled: March 4, 2015Date of Patent: December 20, 2016Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SASInventors: Jean-Robert Manouvrier, Estelle Batail
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Patent number: 9520526Abstract: A manufacturing method of an avalanche photodiode includes: forming a p-type field relaxation layer on a substrate; forming a cap layer on the p-type field relaxation layer; and forming a light absorbing layer on the cap layer, wherein a carbon is doped in the p-type field relaxation layer as a p-type dopant, the p-type field relaxation layer contains Al in a crystal composition, and a temperature-rise process from a growth temperature of the cap layer to a growth temperature of the light absorbing layer is performed in an inactive gas atmosphere without introducing a group V raw material.Type: GrantFiled: August 19, 2015Date of Patent: December 13, 2016Assignee: Mitsubishi Electric CorporationInventors: Harunaka Yamaguchi, Susumu Hatakenaka
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Patent number: 9472686Abstract: One aspect of the invention relates to a gate-tunable p-n heterojunction diode including a vertical stacked heterojunction of two ultrathin semiconductors. In one embodiment, single-layer molybdenum disulphide of an n-type semiconductor are stacked below semiconducting single-walled carbon nanotubes of a p-type semiconductor with each of them connected to a gold electrodes to form a p-n heterojunction. The electrical properties of the p-n heterojunction can be modulated by a gate voltage applied to a gate electrode and range from an insulator to a linear-response resistor to a highly rectifying diode. The gate tunability of the p-n heterojunction also allows spectral control over the photoresponse.Type: GrantFiled: August 1, 2014Date of Patent: October 18, 2016Assignee: NORTHWESTERN UNIVERSITYInventors: Mark C. Hersam, Deep M. Jariwala, Vinod K. Sangwan
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Patent number: 9466746Abstract: Using a multiple layer, varied composition barrier layer in place of the typical single layer barrier layer of an infrared photodetector results in a device with increased sensitivity and reduced dark current. A first barrier is adjacent the semiconductor contact; a second barrier layer is between the first barrier layer and the absorber layer. The barrier layers may be doped N type or P type with Beryllium, Carbon, Silicon or Tellurium. The energy bandgap is designed to facilitate minority carrier current flow in the contact region and block minority current flow outside the contact region.Type: GrantFiled: February 12, 2016Date of Patent: October 11, 2016Assignee: HRL Laboratories, LLCInventors: Terence J De Lyon, Rajesh D Rajavel, Hasan Sharifi
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Patent number: 9437725Abstract: A semiconductor device is provided, which includes a barrier layer 14 formed on a substrate 10 and made of InxAlyGa1-x-yN, a channel layer 16 formed on the barrier layer and made of GaN or InGaN, an electron supplying layer 18 formed on the channel layer and made of AlGaN, InAlN, or InAlGaN, and a gate electrode and ohmic electrodes 24 and 26 formed on the electron supplying layer. Relations between x and y for the barrier layer of x>0, y>0, x+y?1, and 0.533x<y<4.20x are satisfied.Type: GrantFiled: November 13, 2014Date of Patent: September 6, 2016Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Ken Nakata
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Patent number: 9391140Abstract: A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench.Type: GrantFiled: June 20, 2014Date of Patent: July 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Yi Qi, Xunyuan Zhang, Catherine B. Labelle
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Patent number: 9356430Abstract: Optical devices having a structured active region configured for selected wavelengths of light emissions are disclosed.Type: GrantFiled: June 29, 2015Date of Patent: May 31, 2016Assignee: Soraa Laser Diode, Inc.Inventor: James W. Raring
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Patent number: 9312442Abstract: A light emitting diode (LED) structure includes a plurality of devices arranged side by side on a support layer. Each device includes a first conductivity type semiconductor nanowire core and an enclosing second conductivity type semiconductor shell for forming a pn or pin junction that in operation provides an active region for light generation. A first electrode layer extends over the plurality of devices and is in electrical contact with at least a top portion of the devices to connect to the shell. The first electrode layer is at least partly air-bridged between the devices.Type: GrantFiled: August 18, 2015Date of Patent: April 12, 2016Assignee: GLO ABInventor: Truls Lowgren
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Patent number: 9312436Abstract: According to one embodiment, a nitride semiconductor device includes a first layer and a functional layer. The first layer is formed on an amorphous layer, includes aluminum nitride, and has a compressive strain or a tensile strain. The functional layer is formed on the first layer and includes a nitride semiconductor.Type: GrantFiled: March 15, 2013Date of Patent: April 12, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Ono, Tomonari Shioda, Naoharu Sugiyama, Toshiyuki Oka, Shinya Nunoue
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Patent number: 9293612Abstract: Using a multiple layer, varied composition barrier layer in place of the typical single layer barrier layer of an infrared photodetector results in a device with increased sensitivity and reduced dark current. A first barrier is adjacent the semiconductor contact; a second barrier layer is between the first barrier layer and the absorber layer. The barrier layers may be doped N type or P type with Beryllium, Carbon, Silicon or Tellurium. The energy bandgap is designed to facilitate minority carrier current flow in the contact region and block minority current flow outside the contact region.Type: GrantFiled: August 7, 2014Date of Patent: March 22, 2016Assignee: HRL Laboratories, LLCInventors: Terence J De Lyon, Rajesh D Rajavel, Hasan Sharifi
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Patent number: 9281363Abstract: A semiconductor structure includes a first gate-all-around (GAA) structure configured to form a first circuit and a second GAA structure configured to form a second circuit similar to the first circuit. The first GAA structure and the second GAA structure have a same of at least one of the following exemplary features: a number of GAA devices in which current flows from a first oxide definition (OD) region to a second OD region; a number of GAA devices in which current flows from the second OD region to the first OD region; a number of first OD region contact elements; a number of second OD region contact elements.Type: GrantFiled: April 8, 2015Date of Patent: March 8, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chung-Hui Chen
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Patent number: 9276084Abstract: A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; patterning the channel layer to form a recess; and forming a source layer in the recess, such that at least a portion of the channel layer protrudes to form the fin-type channel.Type: GrantFiled: October 17, 2013Date of Patent: March 1, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin
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Patent number: 9269788Abstract: A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged.Type: GrantFiled: February 22, 2013Date of Patent: February 23, 2016Assignee: Sensor Electronic Technology, Inc.Inventors: Remigijus Gaska, Michael Shur, Jinwei Yang, Alexander Dobrinsky, Maxim S Shatalov
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Patent number: 9257500Abstract: A method for fabricating a vertical GaN power device includes providing a first GaN material having a first conductivity type and forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a junction. The method further includes implanting ions through the second GaN material and into a first portion of the first GaN material to increase a doping concentration of the first conductivity type. The first portion of the junction is characterized by a reduced breakdown voltage relative to a breakdown voltage of a second portion of the junction.Type: GrantFiled: October 17, 2014Date of Patent: February 9, 2016Assignee: Avogy, Inc.Inventor: Donald R. Disney
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Patent number: 9240516Abstract: Amongst the candidates for very high efficiency electronics, solid state light sources, photovoltaics, and photoelectrochemical devices, and photobiological devices are those based upon metal-nitride nanowires. Enhanced nanowire performance typically require heterostructures, quantum dots, etc which requirement that these structures are grown with relatively few defects and in a controllable reproducible manner. Additionally flexibility according to the device design requires that the nanowire at the substrate may be either InN or GaN. Methods of growing relatively defect free nanowires and associated structures for group IIIA-nitrides are presented without the requirement for foreign metal catalysts, overcoming the non-uniform growth of prior art techniques and allowing self-organizing quantum dot, quantum well and quantum dot-in-a-dot structures to be formed.Type: GrantFiled: July 14, 2015Date of Patent: January 19, 2016Assignee: The Royal Institution for the Advancement of Learning/McGill UniversityInventors: Zetian Mi, Md Golam Kibria
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Patent number: 9209349Abstract: A method of fabricating a nitride semiconductor light emitting device is provided. The method includes growing a first group-III-nitride semiconductor layer on a substrate, the first group-III-nitride semiconductor layer having a top surface formed as a group-III-rich surface exhibiting a group-III-polarity and a bottom surface formed as a N-rich surface exhibiting a N-polarity. The method further includes selectively etching a N-polarity region in the top surface of the first group III nitride semiconductor layer, forming a second group III nitride semiconductor layer on the first group III nitride semiconductor layer to fill the etched N-polarity region and forming a light emitting structure including first and second conductivity type nitride semiconductor layers and an active layer on the second group III nitride semiconductor layer.Type: GrantFiled: February 19, 2014Date of Patent: December 8, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kee Won Lee, Jong Uk Seo, Suk Ho Yoon, Keon Hun Lee, Sang Don Lee
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Patent number: 9184274Abstract: Provided is a semiconductor apparatus including a channel layer, an upper barrier layer that is provided on the channel layer, a first barrier layer that constitutes a boundary layer on a side of the channel layer in the upper barrier layer, a second barrier layer that is provided in a surface layer of the upper barrier layer, a low-resistance region that is provided in at least a surface layer in the second barrier layer, a source electrode and a drain electrode that are connected to the second barrier layer, at positions across the low-resistance region, a gate insulating film that is provided on the low-resistance region, and a gate electrode that is provided above the low-resistance region via the gate insulating film.Type: GrantFiled: February 7, 2013Date of Patent: November 10, 2015Assignee: SONY CORPORATIONInventors: Katsuhiko Takeuchi, Satoshi Taniguchi
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Patent number: 9136419Abstract: A semiconductor structure includes a GaAs or InP substrate, an InxGa1-xAs epitaxial layer grown on the substrate, where x is greater than about 0.01 and less than about 0.53, and a wider bandgap epitaxial layer grown as a cap layer on top of the InxGa1-xAs epitaxial layer.Type: GrantFiled: December 7, 2005Date of Patent: September 15, 2015Assignee: PICOMETRIX, LLCInventors: Robert N. Sacks, Matthew M. Jazwiecki, Steven Williamson
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Patent number: 9123841Abstract: An embodiment relates to a device comprising a substrate having a front side and a back-side, a nanowire disposed on the back-side and an image sensing circuit disposed on the front side, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire.Type: GrantFiled: May 19, 2014Date of Patent: September 1, 2015Assignee: ZENA TECHNOLOGIES, INC.Inventors: Young-June Yu, Munib Wober
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Patent number: 9112085Abstract: Metal-nitride nanowires are amongst the candidates for very high efficiency electronics, solid state light sources, photovoltaics, photoelectrochemical devices, and photobiological devices. Enhanced performance typically requires heterostructures, quantum dots, etc within structures that are grown with relatively few defects and in a controllable reproducible manner. Additionally device design flexibility requires that the nanowire at the substrate be either InN or GaN. Methods of growing relatively defect free nanowires and associated structures for group IIIA-nitrides are presented without foreign metal catalysts thereby overcoming the non-uniform growth of prior art techniques and allowing self-organizing quantum dot, quantum well and quantum dot-in-a-dot structures to be formed, thereby supporting variety of high efficiency devices.Type: GrantFiled: April 19, 2013Date of Patent: August 18, 2015Assignee: The Royal Institution for the Advancement of Learning/McGill UniversityInventors: Zetian Mi, Md Golam Kibria
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Patent number: 9048346Abstract: Provided are embodiments of a light emitting device and fabrication methods thereof. The light emitting device can include a buffer layer provided between a substrate and a semiconductor layer incorporating a high fusion point metal. In a fabrication method of the light emitting device, the buffer layer incorporating a high fusion point metal can be formed on a substrate, and a semiconductor layer can be formed on the buffer layer.Type: GrantFiled: April 13, 2007Date of Patent: June 2, 2015Assignee: LG INNOTEK CO., LTD.Inventor: Kyong Jun Kim
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Publication number: 20150123073Abstract: Exemplary embodiments of the present disclosure relate to sensor technology for gases, and more specifically, to nanofiber based gas sensors capable of operating at high temperatures (e.g., hundreds, thousands of degrees Celsius). In exemplary embodiments, a combination of p-type and n-type nanofiber materials can be combined to create gas sensors that can be used to detect reducing gases with enhanced selectivity/sensitivity.Type: ApplicationFiled: November 4, 2014Publication date: May 7, 2015Applicant: UNIVERSITY OF CONNECTICUTInventors: Yu Lei, Yixin Liu
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Publication number: 20150108425Abstract: A method of fabricating a nanoshell is disclosed. The method comprises coating a nanometric core made of a first material by a second material, to form a core-shell nanostructure and applying non-chemical treatment to the core-shell nanostructure so as to at least partially remove the nanometric core, thereby fabricating a nanoshell. The disclosed nanoshell can be used in the fabrication of transistors, optical devices (such as CCD and CMOS sensors), memory devices and energy storage devices.Type: ApplicationFiled: May 21, 2013Publication date: April 23, 2015Applicant: Tower Semiconductor Ltd.Inventors: Gil Rosenman, Simon Litsyn, Yakov Roizin
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Publication number: 20150108423Abstract: Disclosed is a method to construct a device that includes a plurality of nanowires (NWs) each having a core and at least one shell. The method includes providing a plurality of radially encoded NWs where each shell contains one of a plurality of different shell materials; and differentiating individual ones of the NWs from one another by selectively removing or not removing shell material within areas to be electrically coupled to individual ones of a plurality of mesowires (MWs). Also disclosed is a nanowire array that contains radially encoded NWs, and a computer program product useful in forming a nanowire array.Type: ApplicationFiled: October 22, 2014Publication date: April 23, 2015Applicant: Brown University Research FoundationInventors: Andre Dehon, Charles M. Lieber, John E. Savage, Eric Rachlin
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Patent number: 9012953Abstract: A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits light when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device.Type: GrantFiled: February 7, 2014Date of Patent: April 21, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Steven Lester, Jeff Ramer, Jun Wu, Ling Zhang
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Patent number: 9006857Abstract: An IR sensor includes a suspended micro-platform having a support layer and a device layer disposed thereon. IR absorbers are disposed in or on the device layer. IR radiation received by the IR absorbers heats an on-platform junction of each of a plurality of series-connected thermoelectric devices operating in a Seebeck mode, the devices producing a voltage indicative of the received IR. Other thermoelectric devices are used to cool the platform, and a pressure sensing arrangement is used to detect loss of vacuum or pressure leaks.Type: GrantFiled: April 4, 2014Date of Patent: April 14, 2015Inventor: William N. Carr
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Patent number: 8993991Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor device includes a substrate including a first top surface, a second top surface lower in level than the first top surface, and a first perpendicular surface disposed between the first and second top surfaces, a first source/drain region formed under the first top surface, a first nanowire extended from the first perpendicular surface in one direction and being spaced apart from the second top surface, a second nanowire extended from a side surface of the first nanowire in the one direction, being spaced apart from the second top surface, and including a second source/drain region, a gate electrode on the first nanowire, and a dielectric layer between the first nanowire and the gate electrode.Type: GrantFiled: July 29, 2011Date of Patent: March 31, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Dongwoo Suh, Sung Bock Kim, Hojun Ryu
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Patent number: 8987780Abstract: A graphene capped HEMT device and a method of fabricating same are disclosed. The graphene capped HEMT device includes one or more graphene caps that enhance device performance and/or reliability of an exemplary AlGaN/GaN heterostructure transistor used in high-frequency, high-energy applications, e.g., wireless telecommunications. The HEMT device disclosed makes use of the extraordinary material properties of graphene. One of the graphene caps acts as a heat sink underneath the transistor, while the other graphene cap stabilizes the source, drain, and gate regions of the transistor to prevent cracking during high-power operation. A process flow is disclosed for replacing a three-layer film stack, previously used to prevent cracking, with a one-atom thick layer of graphene, without otherwise degrading device performance. In addition, the HEMT device disclosed includes a hexagonal boron nitride adhesion layer to facilitate deposition of the compound nitride semiconductors onto the graphene.Type: GrantFiled: May 31, 2013Date of Patent: March 24, 2015Assignee: STMicroelectronics, Inc.Inventors: John H Zhang, Cindy Goldberg, Walter Kleemeier
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Patent number: 8980730Abstract: Exemplary embodiments provide materials and methods of forming high-quality semiconductor devices using lattice-mismatched materials. In one embodiment, a composite film including one or more substantially-single-particle-thick nanoparticle layers can be deposited over a substrate as a nanoscale selective growth mask for epitaxially growing lattice-mismatched materials over the substrate.Type: GrantFiled: September 14, 2011Date of Patent: March 17, 2015Assignee: STC.UNMInventors: Seung-Chang Lee, Steven R. J. Brueck
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Patent number: 8962365Abstract: The present method of manufacturing a GaN-based film includes the steps of preparing a composite substrate including a support substrate dissoluble in hydrofluoric acid and a single crystal film arranged on a side of a main surface of the support substrate, a coefficient of thermal expansion in the main surface of the support substrate being more than 0.8 time and less than 1.2 times as high as a coefficient of thermal expansion of GaN crystal, forming a GaN-based film on a main surface of the single crystal film arranged on the side of the main surface of the support substrate, and removing the support substrate by dissolving the support substrate in hydrofluoric acid. Thus, the method of manufacturing a GaN-based film capable of efficiently obtaining a GaN-based film having a large main surface area, less warpage, and good crystallinity, as well as a composite substrate used therefor are provided.Type: GrantFiled: December 21, 2011Date of Patent: February 24, 2015Assignee: Sumitomo Electric Industies, Ltd.Inventors: Issei Satoh, Yuki Seki, Koji Uematsu, Yoshiyuki Yamamoto, Hideki Matsubara, Shinsuke Fujiwara, Masashi Yoshimura
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Select devices including an open volume, and related methods, memory devices, and electronic systems
Patent number: 8957403Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.Type: GrantFiled: June 27, 2013Date of Patent: February 17, 2015Assignee: Micron Technology, Inc.Inventors: Bhaskar Srinivasan, Gurtej S. Sandhu -
Patent number: 8952352Abstract: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.Type: GrantFiled: May 23, 2013Date of Patent: February 10, 2015Assignee: International Rectifier CorporationInventors: Robert Beach, Zhi He, Jianjun Cao
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Patent number: 8946675Abstract: A light emitting diode includes a substrate, a first-type semiconductor layer, a nanorod layer and a transparent planar layer. The first-type semiconductor layer is disposed over the substrate. The nanorod layer is formed on the first-type semiconductor layer. The nanorod layer includes a plurality of nanorods and each of the nanorods has a quantum well structure and a second-type semiconductor layer. The quantum well structure is in contact with the first-type semiconductor layer, and the second-type semiconductor layer is formed on the quantum well structure. The transparent planar layer is filled between the nanorods. A surface of the second-type semiconductor layer is exposed out of the transparent planar layer.Type: GrantFiled: March 12, 2013Date of Patent: February 3, 2015Assignee: Lextar Electronics CorporationInventors: Chang-Chin Yu, Hsiu-Mu Tang, Mong-Ea Lin