Quantum Well Patents (Class 257/14)
  • Patent number: 10031887
    Abstract: Techniques for improving the performance of a quantum processor are described. The techniques include reading out a fraction of the qubits in a quantum processor and utilizing one or more post-processing operations to reconstruct qubits of the quantum processor that are not read. The reconstructed qubits may be determined using a perfect sampler to provide results that are strictly better than reading all of the qubits directly from the quantum processor. The composite sample that includes read qubits and reconstructed qubits may be obtained faster than if all qubits of the quantum processor are read directly.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: July 24, 2018
    Assignee: D-WAVE SYSTEMS INC.
    Inventor: Jack Raymond
  • Patent number: 10026863
    Abstract: A method of manufacturing a sensor array includes providing a carrier glass substrate, forming an amorphous silicon layer over the carrier glass substrate, forming a first heat buffer layer over the amorphous silicon layer; forming a mirror layer over the first heat buffer layer; forming a second heat buffer layer over the mirror layer; forming a flexible substrate over the second heat buffer layer; and forming an active device layer over the flexible substrate. The method of the present invention further comprises exposing the sensor array to light from a flash lamp and then detaching the carrier glass substrate from the sensor array. The method of the present invention optionally further comprises filtering the light from the flash lamp to wavelengths below 350 nm.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: July 17, 2018
    Assignee: DPIX, LLC
    Inventors: Frank Caris, Shawn Michael O'Rourke, Byung-Kyu Park, Terri Renae Pederson
  • Patent number: 10026834
    Abstract: A method of manufacturing an enhanced device and an enhance device are provided. The method comprises: preparing a substrate, and forming a non-planar structure in the substrate; depositing a nitride channel layer on the substrate, a gate region, a source region and a drain region being defined on the nitride channel layer, the gate region of the nitride channel layer having a non-planar structure transferred from the non-planar structure of the substrate; depositing a nitride barrier layer on the nitride channel layer, the nitride barrier layer having a non-planar structure located above and corresponding to the non-planar structure of the nitride channel layer, the nitride barrier layer and the nitride channel layer forming a nitride channel layer/nitride barrier layer heterojunction.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: July 17, 2018
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 10020639
    Abstract: A laser diode arrangement comprising: at least one semiconductor substrate; at least two laser stacks based on the AlInGaN material system, each laser stack having an active zone, wherein at least one of the at least two laser stacks comprises a two-dimensional structure of laser diodes; and at least one intermediate layer. The laser stacks and the intermediate layer are grown monolithically on the semiconductor substrate. The intermediate layer is arranged between the laser stacks. The active zone of the first laser stack can be actuated separately from the active zone of the at least one further laser stack.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: July 10, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Alfred Lell, Martin Strassburg
  • Patent number: 10008543
    Abstract: Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: June 26, 2018
    Assignee: INVISAGE TECHNOLOGIES, INC.
    Inventors: Edward Hartley Sargent, Jason Paul Clifford, Gerasimos Konstantatos, Ian Howard, Ethan J. D. Klem, Larissa Levina
  • Patent number: 10000381
    Abstract: Systems and methods for MBE growing of group-III Nitride alloys, comprising establishing an average reaction temperature range from about 250 C to about 850 C; introducing a nitrogen flux at a nitrogen flow rate; introducing a first metal flux at a first metal flow rate; and periodically stopping and restarting the first metal flux according to a first flow duty cycle. According to another embodiment, the system comprises a nitrogen source that provides nitrogen at a nitrogen flow rate, and, a first metal source comprising a first metal effusion cell that provides a first metal at a first metal flow rate, and a first metal shutter that periodically opens and closes according to a first flow duty cycle to abate and recommence the flow of the first metal from the first metal source. Produced alloys include AlN, InN, GaN, InGaN, and AlInGaN.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: June 19, 2018
    Assignee: Georgia Tech Research Corporation
    Inventors: Michael William Moseley, William Alan Doolittle
  • Patent number: 9996802
    Abstract: An optical system comprising a charged quantum dot having, a charged carrier, first and second ground state levels and a plurality of excited state levels, the first and second ground state energy levels having different spin states such that the said charged carrier cannot transfer between the first and second ground state energy levels without changing its spin state, the system further comprising a controller adapted to control a first radiating beam with energy not more than 100 micro-eV from a first transition within said quantum dot from a first ground state level to a selected excited state level from the plurality of excited state levels to, the system being adapted to enhance the decay rate of a second transition within said quantum dot from the selected excited state level to a second ground state level, but not a first transition, such that a photon is produced due to scattering of a photon from the first radiating beam, wherein the controller is adapted to irradiate the quantum dot with the fir
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: June 12, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Anthony John Bennett, Andrew James Shields
  • Patent number: 9995964
    Abstract: The present invention relates to a liquid crystal display panel and a display device. The liquid crystal display panel comprises a first substrate and a second substrate assembled in an aligned manner, and further comprises a reflecting layer, a light wavelength conversion layer and a quantum dot layer; the reflecting layer is provided on the second substrate, the quantum dot layer is provided on the first substrate or the second substrate, and the reflecting layer and the quantum dot layer are arranged in a direction from the second substrate to the first substrate; the light wavelength conversion layer is made from an upconversion material and provided between the reflecting layer and the quantum dot layer. The above liquid crystal display panel has a higher utilization of ambient light, and thus has higher brightness and contrast ratio.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: June 12, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Bin Zhang, Tingting Zhou, Zhijun Lv
  • Patent number: 9991172
    Abstract: In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Jack T. Kavalieros, Suman Datta, Marko Radosavljevic
  • Patent number: 9988737
    Abstract: An epitaxial diamond layer and a method for the production thereof can be provided that comprises the following steps: providing a substrate; depositing a metal layer on at least a subarea of the substrate, wherein the metal layer contains, or consists of, at least one period 4, 5 or 6 metal having a melting point of greater than or equal to 1200 K; and depositing a diamond layer on at least a subarea of the metal layer; wherein at least one intermediate layer is deposited between the metal layer and the diamond layer and has a higher lattice constant than undoped crystalline diamond and a lower hardness than undoped crystalline diamond.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: June 5, 2018
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Christoph E Nebel, Claudia Widmann
  • Patent number: 9991370
    Abstract: High electron mobility leads to better device performance and today is achieved by fabricating “gated devices” within a high-mobility two-dimensional electron gas (2DEG. However, the fabrication techniques used to form these devices lead to rapid degradation of the 2DEG quality which then can limits the mobility of the electronic devices. Accordingly, it would be beneficial to provide a process/technique which circumvents this processing and 2DEG layer damage. By exploiting a flip-chip methodology such damaging processing steps are separated to a second die/wafer which is then coupled to the 2DEG wafer. Extensions of the technique with two or more different semiconductor materials or material systems may be employed in conjunction with one or more electronic circuits to provide 2DEG enabled circuits in 2D and/or 3D stacked configurations. Further semiconductor materials providing EG elements may incorporate one or more of 2DEG, 1DEG, and “zero” DEG structures.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: June 5, 2018
    Assignee: THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING/MCGILL UNIVERSITY
    Inventors: Guillaume Gervais, Keyan Bennaceur
  • Patent number: 9978940
    Abstract: A device is disclosed which comprises a first electrode (101), a second electrode (104) spaced from the first electrode, a switching region (102) positioned between the first electrode and the second electrode, and an intermediate region (103) positioned between the switching region and the second electrode, wherein the intermediate region is in electrical contact with the switching region and the second electrode. Preferably, the intermediate region comprises metal nanowires (105) in a polymer matrix, and the device is a memristor or a memcapacitor. In the latter case, the switching region comprises a conductive material (106) and an insulating material (107).
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: May 22, 2018
    Assignee: Provenance Asset Group LLC
    Inventors: Alexander Alexandrovich Bessonov, Dmitrii Igorevich Petukhov, Marina Nikolaevna Kirikova, Marc Bailey, Tapani Ryhanen
  • Patent number: 9966497
    Abstract: A method of fabricating a nonpolar gallium nitride-based semiconductor layer is provided. The method is a method of fabricating a nonpolar gallium nitride layer using metal organic chemical vapor deposition, and includes disposing a gallium nitride substrate with an m-plane growth surface within a chamber, raising a substrate temperature to a GaN growth temperature by heating the substrate, and growing a gallium nitride layer on the gallium nitride substrate by supplying a Ga source gas, an N source gas, and an ambient gas into the chamber at the growth temperature. The supplied ambient gas contains N2 and does not contain H2.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: May 8, 2018
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Seung Kyu Choi, Chae Hon Kim, Jung Whan Jung
  • Patent number: 9966257
    Abstract: A composition of matter comprising at least one nanowire on a graphitic substrate, said at least one nanowire having been grown epitaxially on said substrate, wherein said nanowire comprises at least one group III-V compound or at least one group II-VI compound or comprises at least one non carbon group (IV) element.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: May 8, 2018
    Assignee: Norwegian University of Science and Technology
    Inventors: Helge Weman, Bjørn-Ove Fimland, Dong Chul Kim
  • Patent number: 9960315
    Abstract: A light emitting heterostructure including a partially relaxed semiconductor layer is provided. The partially relaxed semiconductor layer can be included as a sublayer of a contact semiconductor layer of the light emitting heterostructure. A dislocation blocking structure also can be included adjacent to the partially relaxed semiconductor layer.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 1, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9958145
    Abstract: A lighting device includes a light-emitting diode (LED). A first carbon nanotube (CNT) is coupled to and extends from the LED. A second CNT is coupled to and extends from the LED. The first and second CNTs are configured to generate a voltage difference across the LED when the first and second CNTs are exposed to an electromagnetic (EM) field having a frequency within a predetermined range. The LED is configured to emit light when the voltage difference is greater than or equal to a threshold voltage.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: May 1, 2018
    Assignee: THE BOEING COMPANY
    Inventors: Keith D. Humfeld, Morteza Safai
  • Patent number: 9960567
    Abstract: A laser device includes a silicon substrate, a buffer layer on the silicon substrate, a laser cavity on the buffer layer including a first active region based on group III-V semiconductor quantum dots, and a semiconductor optical amplifier that is integrated with the laser cavity on the buffer layer, includes a second active region based on group III-V semiconductor quantum dots, and amplifies light emitted from the laser cavity.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: May 1, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Taek Kim
  • Patent number: 9954138
    Abstract: An LED element is provided with: a first semiconductor layer formed of an n-type nitride semiconductor; a second semiconductor layer formed on top of the first semiconductor layer and formed of quaternary mixed crystals of Alx1Gay1Inz1N (0<x1<1, 0<y1<1, 0<z1<1 and x1+y1+z1=1); a heterostructure formed on top of the second semiconductor layer and constituted of a laminate structure of a third semiconductor layer formed of Inx2Ga1-x2N (0<x2<1) having a film thickness of greater than or equal to 10 nm, and a fourth semiconductor layer formed of Alx3Gay3Inz3N (0<x3<1, 0<y3<1, 0?z3<1 and x3+y3+z3=1); and a fifth semiconductor layer formed on top of the heterostructure and formed of a p-type nitride semiconductor.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: April 24, 2018
    Assignee: USHIO DENKI KABUSHIKI KAISHA
    Inventors: Kohei Miyoshi, Masashi Tsukihara
  • Patent number: 9952693
    Abstract: The present invention provides a touch panel, including a lower substrate, an organic light-emitting component, disposed on the lower substrate, a nano silver sensing layer, disposed on the organic light emitting component, and an upper substrate, disposed on the nano silver sensing layer.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: April 24, 2018
    Assignee: TPK Touch Solutions Inc.
    Inventors: Chen-Yu Liu, Li-Wei Kung, Hsi-Chien Lin
  • Patent number: 9947869
    Abstract: The present disclosure relates to a method for making nanoscale heterostructure. The method includes: providing a support and forming a first carbon nanotube layer on the support, and the first carbon nanotube layer comprises a plurality of first source carbon nanotubes; forming a semiconductor layer on the first carbon nanotube layer; covering a second carbon nanotube layer on the semiconductor layer, and the second carbon nanotube layer comprises a plurality of second source carbon nanotubes; finding and labeling a first carbon nanotube in the first carbon nanotube layer and a second carbon nanotube in the second carbon nanotube layer; removing the plurality of first source carbon nanotubes and the plurality of second source carbon nanotubes; and annealing the multilayer structure.
    Type: Grant
    Filed: June 3, 2017
    Date of Patent: April 17, 2018
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jin Zhang, Yang Wei, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 9939970
    Abstract: A touch substrate and a display device are disclosed. The touch substrate includes a plurality of first electrodes and second electrodes disposed as intersecting each other, wherein the first electrodes and the second electrodes contact each other at intersecting positions and form heterojunction therein. The touch substrate of the invention takes advantage of unidirectional conductive feature of the heterojunction to prevent the interference between the first electrodes and the second electrodes, thereby guaranteeing the good performance of the touch substrate.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: April 10, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Ting Zeng, Ming Hu, Hongqiang Luo, Kefeng Li
  • Patent number: 9940212
    Abstract: Methods and apparatus for automatic qubit calibration. In one aspect, a method includes obtaining a plurality of qubit parameters and data describing dependencies of the plurality of qubit parameters on one or more other qubit parameters; identifying a qubit parameter; selecting a set of qubit parameters that includes the identified qubit parameter and one or more dependent qubit parameters; processing one or more parameters in the set of qubit parameters in sequence according to the data describing dependencies, comprising, for a parameter in the set of qubit parameters: performing a calibration test on the parameter; and performing a first calibration experiment or a diagnostic calibration algorithm on the parameter when the calibration test fails.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: April 10, 2018
    Assignee: Google LLC
    Inventor: Julian Shaw Kelly
  • Patent number: 9939510
    Abstract: A solid state electronic spin system contains electronic spins disposed within a solid state lattice and coupled to an electronic spin bath and a nuclear spin bath, where the electronic spin bath composed of electronic spin impurities and the nuclear spin bath composed of nuclear spin impurities. The concentration of nuclear spin impurities in the nuclear spin bath is controlled to a value chosen so as to allow the nuclear spin impurities to effect a suppression of spin fluctuations and spin decoherence caused by the electronic spin bath. Sensing devices such as magnetic field detectors can exploit such a spin bath suppression effect, by applying optical radiation to the electronic spins for initialization and readout, and applying RF pulses to dynamically decouple the electronic spins from the electronic spin bath and the nuclear spin bath.
    Type: Grant
    Filed: October 22, 2017
    Date of Patent: April 10, 2018
    Assignee: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Ronald L. Walsworth, Nir Bar-Gill, Chinmay Belthangady, Linh My Pham
  • Patent number: 9934973
    Abstract: The invention relates in particular to a method for producing subsequent patterns in an underlying layer (120), the method comprising at least one step of producing prior patterns in a carbon imprintable layer (110) on top of the underlying layer (120), the production of the prior patterns involving nanoimprinting of the imprintable layer (110) and leave in place a continuous layer formed by the imprintable layer (110) and covering the underlying layer (120), characterized in that it comprises the following step: at least one step of modifying the underlying layer (120) via ion implantation (421) in the underlying layer (120), the implantation (421) being carried out through the imprintable layer (110) comprising the subsequent patterns, the parameters of the implantation (421) being chosen in such a way as to form, in the underlying layer (120), implanted zones (122) and non-implanted zones, the non-Implanted zones defining the subsequent patterns and having a geometry that is dependent on the prior pattern
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 3, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stefan Landis, Nicolas Posseme, Sebastien Barnola, Thibaut David, Lamia Nouri
  • Patent number: 9923117
    Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher. In one embodiment, the semiconductor layer is used to form an optoelectronic device.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: March 20, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Alexander Lunev, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Patent number: 9905724
    Abstract: An optical material comprising quantum confined semiconductor nanoparticles, wherein at least a portion of the nanoparticles are in a charge neutral state is disclosed. Also disclosed is an optical component including an optical material comprising quantum confined semiconductor nanoparticles, wherein at least a portion of the nanoparticles are in a charge neutral state. Further disclosed is an optical material obtainable by at least partially encapsulating an optical material comprising quantum confined semiconductor nanoparticles and irradiating the at least partially encapsulated optical material with a light flux for a period of time sufficient to neutralize the charge on at least a portion of the nanoparticles.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: February 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Rohit Modi, Patrick Landreman, John R. Linton, Emily M. Squires
  • Patent number: 9905719
    Abstract: A multi-junction solar cell that is lattice-matched with a base, and that includes a sub-cell having a desirable band gap is provided. A plurality of sub-cells are laminated, each including first and second compound semiconductor layers. At least one predetermined sub-cell is configured of first layers and a second layer. In each of the first layers, a 1-A layer and a 1-B layer are laminated. In the second layer, a 2-A layer and a 2-B layer are laminated. A composition A of the 1-A layer and the 2-A layer is determined based on a value of a band gap of the predetermined sub-cell. A composition B of the 1-B layer and the 2-B layer is determined based on a difference between a base lattice constant of the base and a lattice constant of the composition A. Thicknesses of 1-B layer and 2-B layer are determined based on difference between base lattice constant and a lattice constant of composition B, and on thickness of the 1-A layer and thickness of 2-A layer.
    Type: Grant
    Filed: September 3, 2012
    Date of Patent: February 27, 2018
    Assignee: Sony Corporation
    Inventors: Hiroshi Yoshida, Masao Ikeda, Shiro Uchida, Takashi Tange, Masaru Kuramoto, Masayuki Arimochi, Hui Yang, Shulong Lu, Xinhe Zheng
  • Patent number: 9899434
    Abstract: A light-receiving device includes a silicon semiconductor substrate, a plurality of first serial connections each of which includes a first avalanche photodiode (APD) and a first resistor connected in series, and a plurality of second serial connections each of which includes a second avalanche photodiode (APD) and a second resistor connected in series. The first APDs and the first resistors are formed on the silicon semiconductor substrate, and the first APDs is formed of silicon. The second APDs and the second resistors are formed on the silicon semiconductor substrate, and the second APDs is formed of a material having a smaller band gap than silicon. The plurality of first and second serial connections is connected in parallel between an anode terminal and a cathode terminal.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: February 20, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koichi Kokubun
  • Patent number: 9871343
    Abstract: This photonic transmitter includes a layer made of dielectric material, a sublayer made of doped III-V crystalline material extending directly over the layer made of dielectric material, a laser source including the sublayer made of doped III-V crystalline material, a modulator including a waveguide formed by proximal ends facing first and second electrodes and that segment of the layer made of dielectric material which is interposed between these proximal ends, and a zone composed only of one or more solid dielectric materials, which extends from a distal end of the second electrode to a substrate, and under the entirety of the distal end of the second electrode.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: January 16, 2018
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventor: Sylvie Menezo
  • Patent number: 9865771
    Abstract: A semiconductor light-emitting element includes: a lower clad layer 12 that is provided on a substrate 10; an active layer 20 that is provided on the lower clad layer 12 and includes a quantum well layer 24 and a plurality of quantum dots 28 sandwiching a second barrier layer 22b together with the quantum well layer 24; and an upper clad layer 14 that is provided on the active layer 20, wherein a distance D between the quantum well layer 24 and the plurality of quantum dots 28 is smaller than an average of distances X between centers of the plurality of quantum dots 28.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: January 9, 2018
    Assignees: QD LASER, INC., UNIVERSITY OF SHEFFIELD
    Inventors: Kenichi Nishi, Takeo Kageyama, Keizo Takemasa, Mitsuru Sugawara, Richard Hogg, Siming Chen
  • Patent number: 9859115
    Abstract: Semiconductor devices comprising two-dimensional (2D) materials and methods of manufacture thereof are described. In an embodiment, a method for manufacturing a semiconductor device comprising 2D materials may include: epitaxially forming a first 2D material layer on a substrate; and epitaxially forming a second 2D material layer over the first 2D material layer, the first 2D material layer and the second 2D material layer differing in composition.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: January 2, 2018
    Assignees: National Taiwan University, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Yu Lin, Shih-Yen Lin, Si-Chen Lee, Samuel C. Pan
  • Patent number: 9848113
    Abstract: A system and method for authenticating a user of a device. A multi-band biometric iris scan camera system is capable of obtaining an iris image using near-infrared (NIR) light and/or visible wavelength (VW) light. The camera system can initially image a user to detect the iris color of the user and, based on the iris color, determine whether to use the NIR iris scan or the VW iris scan. Additionally, NIR and VW systems can be operated as integrated camera systems. The iris scan camera system can take a series of images and compare against a database of anonymous iris images captured at different illumination conditions, for selecting a preferred illumination condition for capturing the iris and performing authentication.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: December 19, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gerard Dirk Smits, Steven David Oliver
  • Patent number: 9829557
    Abstract: A solid state electronic spin system contains electronic spins disposed within a solid state lattice and coupled to an electronic spin bath and a nuclear spin bath, where the electronic spin bath composed of electronic spin impurities and the nuclear spin bath composed of nuclear spin impurities. The concentration of nuclear spin impurities in the nuclear spin bath is controlled to a value chosen so as to allow the nuclear spin impurities to effect a suppression of spin fluctuations and spin decoherence caused by the electronic spin bath. Sensing devices such as magnetic field detectors can exploit such a spin bath suppression effect, by applying optical radiation to the electronic spins for initialization and readout, and applying RF pulses to dynamically decouple the electronic spins from the electronic spin bath and the nuclear spin bath.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: November 28, 2017
    Assignee: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Ronald L. Walsworth, Nir Bar-Gill, Chinmay Belthangady, Linh My Pham
  • Patent number: 9831331
    Abstract: A heterojunction structure of semiconductor material, for a high electron mobility transistor includes a substrate, a buffer layer, arranged on the substrate, of a large bandgap semiconductor material, based on a nitride from column III, where the buffer layer is not intentionally doped with n-type carriers, a barrier layer arranged above the buffer layer, of a large bandgap semiconductor material based on a nitride from column III, where the width of the bandgap of the barrier layer is less than the width of the bandgap of the buffer layer. The heterojunction structure additionally comprises an intentionally doped area, of a material based on a nitride from column III identical to the material of the buffer layer, in a plane parallel to the plane of the substrate and a predefined thickness along a direction orthogonal to the plane of the substrate, where the area is comprised in the buffer layer.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: November 28, 2017
    Assignees: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE—CNRS, UNIVERSITE LIBANAISE
    Inventors: Frédéric Morancho, Saleem Hamady, Bilal Beydoun
  • Patent number: 9826214
    Abstract: A photosensor having a plurality of light sensitive pixels each of which comprises a light sensitive region and a plurality of storage regions for accumulating photocharge generated in the light sensitive region, a transfer gate for each storage region that is selectively electrifiable to transfer photocharge from the light sensitive region to the storage region, and an array of microlenses that for each storage region directs a different portion of light incident on the pixel to a region of the light sensitive region closer to the storage region than to other storage regions.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: November 21, 2017
    Assignee: Microsoft Technology Licensing, LLC.
    Inventors: David Cohen, Erez Tadmor, Giora Yahav
  • Patent number: 9825154
    Abstract: The tunneling channel of a field effect transistor comprising a plurality of tunneling elements contacting a channel substrate. Applying a source-drain voltage of greater than a turn-on voltage produces a source-drain current of greater than about 10 pA. Applying a source-drain voltage of less than a turn-on voltage produces a source-drain current of less than about 10 pA. The turn-on voltage at room temperature is between about 0.1V and about 40V.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: November 21, 2017
    Assignee: Michigan Technological University
    Inventor: Yoke Khin Yap
  • Patent number: 9816920
    Abstract: A method for producing an integrated micromechanical fluid sensor component includes forming a first wafer with a first Bragg reflector and with a light-emitting device on a first substrate. The light-emitting device is configured to emit light rays in an emission direction from a surface of the light-emitting device facing away from the first Bragg reflector. The method further includes forming a second wafer with a second Bragg reflector and with a photodiode on a second substrate. The photodiode is arranged on a surface of the second Bragg reflector facing towards the second substrate. The method also includes bonding or gluing the first wafer to the second wafer such that there is formed a cavity into which a fluid is introduced and through which the light rays can pass. The method further includes separating the fluid sensor component from the first and the second wafer.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: November 14, 2017
    Assignee: Robert Bosch GmbH
    Inventors: Richard Fix, Rene Hartke, Jochen Beintner
  • Patent number: 9806227
    Abstract: In various embodiments, light-emitting devices incorporate graded layers with compositional offsets at one or both end points of the graded layer to promote formation of two-dimensional carrier gases and polarization doping, thereby enhancing device performance.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: October 31, 2017
    Assignee: CRYSTAL IS, INC.
    Inventors: Craig Moe, James R. Grandusky, Shawn R. Gibb, Leo J. Schowalter, Kosuke Sato, Tomohiro Morishita
  • Patent number: 9806131
    Abstract: Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: October 31, 2017
    Assignee: INVISAGE TECHNOLOGIES, INC.
    Inventors: Edward Hartley Sargent, Jason Paul Clifford, Gerasimos Konstantatos, Ian Howard, Ethan J. D. Klem, Larissa Levina
  • Patent number: 9786797
    Abstract: An electronic device, includes: a graphene nanoribbon having a first graphene and a second graphene; a first electrode coupled to the first graphene; and a second electrode coupled to the second graphene, wherein the first graphene is terminated on an edge by a first terminal group and has a first polarity and the second graphene is terminated on an edge by a second terminal group different to the first terminal group and has a second polarity different from the first polarity.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: October 10, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Naoki Harada, Hideyuki Jippo
  • Patent number: 9772329
    Abstract: Described herein are systems and methods for detecting a target analyte in a sample with electrodes, comprising a linker and an antibody attached to the linker, and measuring an electrocatalytic signal changes generated by binding of an analyte in the sample to the antibody. Also disclosed herein are kits for electrochemical detection of protein analytes.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: September 26, 2017
    Assignee: The Governing Council of the University of Toronto
    Inventors: Jagotamoy Das, Shana O. Kelley
  • Patent number: 9766071
    Abstract: Waveguide includes fork with first and second bifurcated ends coupled to loop section and separated by angle determined based on velocities of portions of quantum mechanical wavefunction of atoms traveling above waveguide. Waveguide propagates blue-detuned laser having first evanescent field that repels atoms away from waveguide and red-detuned laser having second evanescent field that attracts atoms toward waveguide, together creating potential minimum/well. Laser cooling atoms, causing atoms positioned in potential minimum/well to move toward first fork section following potential minimum/well. Atomic state initialization section initializes atomic states of atoms to known ground-state configuration.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: September 19, 2017
    Assignee: Honeywell International Inc.
    Inventors: Robert Compton, Karl D. Nelson, Chad Fertig
  • Patent number: 9768349
    Abstract: A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another. Furthermore, the superlattice layer can be configured to be at least partially transparent to radiation, such as ultraviolet radiation.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: September 19, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Alexander Dobrinsky
  • Patent number: 9748473
    Abstract: An apparatus includes a substrate having a planar top surface, a sequence of crystalline semiconductor layers located on the planar surface, and first and second sets of electrodes located over the sequence. The sequence of crystalline semiconductor layers has a 2D quantum well therein. The first set of electrodes border opposite sides of a lateral region of the sequence and are controllable to vary a width of a non-depleted portion of the quantum well along the top surface. The second set of electrodes border first and second channels between the lateral region and first and second adjacent lateral areas of the sequence and are controllable to vary widths of non-depleted segments of the quantum well in the channels. The electrodes are located such that straight lines connecting the first and second lateral areas via the channels either pass between one of the electrodes and the substrate or are misaligned to an effective [1 1 0] lattice direction of the sequence.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: August 29, 2017
    Assignee: Alcatel Lucent
    Inventor: Robert L. Willett
  • Patent number: 9732273
    Abstract: Described are ZnxCd1-xSySe1-y/ZnSzSe1-z core/shell nanocrystals, CdTe/CdS/ZnS core/shell/shell nanocrystals, optionally doped Zn(S,Se,Te) nano- and quantum wires, and SnS quantum sheets or ribbons, methods for making the same, and their use in biomedical and photonic applications, such as sensors for analytes in cells and preparation of field effect transistors.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: August 15, 2017
    Assignee: Arizona Board of Regents
    Inventors: Hao Yan, Zhengtao Deng, Yan Liu
  • Patent number: 9735236
    Abstract: This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded with a thin layer serving as an energy barrier. The quantum dot channel (QDC) may consist of one or more layers of cladded dots. These dots are realized on a single or polycrystalline substrate. When QDC FETs are realized on polycrystalline or nanocrystalline thin films they may yield higher mobility than in conventional nano- or microcrystalline thin films. These FETs can be used as thin film transistors (TFTs) in a variety of applications. In another embodiment QDC-FETs are combined with: (a) coupled quantum well SWS channels, (b) quantum dot gate 3-state like FETs, and (c) quantum dot gate nonvolatile memories.
    Type: Grant
    Filed: March 12, 2016
    Date of Patent: August 15, 2017
    Inventor: Faquir Chand Jain
  • Patent number: 9720067
    Abstract: A solid state electronic spin system contains electronic spins disposed within a solid state lattice and coupled to an electronic spin bath and a nuclear spin bath, where the electronic spin bath composed of electronic spin impurities and the nuclear spin bath composed of nuclear spin impurities. The concentration of nuclear spin impurities in the nuclear spin bath is controlled to a value chosen so as to allow the nuclear spin impurities to effect a suppression of spin fluctuations and spin decoherence caused by the electronic spin bath. Sensing devices such as magnetic field detectors can exploit such a spin bath suppression effect, by applying optical radiation to the electronic spins for initialization and readout, and applying RF pulses to dynamically decouple the electronic spins from the electronic spin bath and the nuclear spin bath.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: August 1, 2017
    Assignee: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Ronald L. Walsworth, Nir Bar-Gill, Chinmay Belthangady, Linh My Pham
  • Patent number: 9704101
    Abstract: A quantum device is provided that includes controllably quantum mechanically coupled dangling bonds extending from a surface of a semiconductor material. Each of the controllably quantum mechanically coupled dangling bonds has a separation of at least one atom of the semiconductor material. At least one electrode is provided for selectively modifying an electronic state of the controllably quantum mechanically coupled dangling bonds. By providing at least one additional electron within the controllably quantum mechanically coupled dangling bonds with the proviso that there exists at least one unoccupied dangling bond for each one additional electron present, the inventive device is operable at least to 293 degrees Kelvin and is largely immune to stray electrostatic perturbations. Room temperature operable quantum cellular automata and qubits are constructed therefrom.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: July 11, 2017
    Assignees: National Research Council of Canada, The Governors of the University of Alberta
    Inventors: Gino A. Dilabio, Robert A. Wolkow, Jason L. Pitters, Paul G. Piva
  • Patent number: 9705081
    Abstract: Generally discussed herein are techniques for and systems and apparatuses configured to control phonons using an electric field. In one or more embodiments, an apparatus can include electrical contacts, two quantum dots embedded in a semiconductor such that when an electrical bias is applied to the electrical contacts, the electric field produced by the electrical bias is substantially parallel to an axis through the two quantum dots, and a phononic wave guide coupled to the semiconductor, the phononic wave guide configured to transport phonons therethrough.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: July 11, 2017
    Assignee: The Regents of the University of California
    Inventor: Michael Scheibner
  • Patent number: 9698286
    Abstract: A quantum well infrared photodetector (QWIP) and method of making is disclosed. The QWIP includes a plurality of epi-layers formed into multiple periods of quantum wells, each of the quantum wells being separated by a barrier, the quantum wells and barriers being formed of II-VI semiconductor materials. A multiple wavelength QWIP is also disclosed and includes a plurality of QWIPs stacked onto a single epitaxial structure, in which the different QWIPs are designed to respond at different wavelengths. A dual wavelength QWIP is also disclosed and includes two QWIPs stacked onto a single epitaxial structure, in which one QWIP is designed to respond at 10 ?m and the other at 3-5 ?m wavelengths.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: July 4, 2017
    Assignees: THE RESEARCH FOUNDATION OF THE CITY UNIVERSITY OF NEW YORK, THE TRUSTEES OF PRINCETON UNIVERSITY
    Inventors: Arvind Ravikumar, Claire Gmachl, Aidong Shen, Maria Tamargo