Quantum Well Patents (Class 257/14)
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Patent number: 10304535Abstract: A switch activated by a single control photon for routing a single target photon from either of two switch inputs to either of two switch outputs. The device is based on a single quantum emitter, such as an atom, coupled to a fiber-coupled, chip-based optical micro-resonator. A single reflected control photon toggles the switch from high reflection to high transmission mode, with no additional control fields required. The control and target photons are both in-fiber and practically identical, for compatibility with scalable architectures for quantum information processing.Type: GrantFiled: March 30, 2016Date of Patent: May 28, 2019Assignee: YEDA RESEARCH AND DEVELOPMENT CO. LTD.Inventors: Barak Dayan, Itay Shomroni, Serge Rosenblum
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Patent number: 10290779Abstract: A light emitting element includes a light emitting member that is formed of at least two kinds of an oxide material and has a plate shape; and a light transmitting member that collimates a light emitted from the light emitting member and has a plano-convex shape, in which a contact portion between the light transmitting member and the light emitting member is continuous.Type: GrantFiled: November 28, 2017Date of Patent: May 14, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shinnosuke Akiyama, Kei Toyota, Masato Mori
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Patent number: 10277010Abstract: A semiconductor laser includes a mesa structure disposed on a principal surface of a substrate, the mesa structure extending in a direction of an axis parallel to the principal surface, the mesa structure including an active region that includes a quantum well, the active region having top and bottom surfaces, and first, second, third and fourth side surfaces; an emitter region disposed on at least one of the first and second side surfaces, and the top and bottom surfaces; and a collector region including a quantum filter structure disposed on at least one of the side surfaces. The collector region is separated from the emitter region on the mesa structure. The first and second side surfaces extend in the direction of the axis. The third side surface extends in a direction intersecting the axis.Type: GrantFiled: January 29, 2018Date of Patent: April 30, 2019Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Tsukuru Katsuyama, Takashi Kato
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Patent number: 10271385Abstract: The invention of the application relates to obtaining a three dimensional coating on fabrics with dip coating method of silver nanowires, which allow fabric to breathe, do not limit the flexibility or restrict the use of the fabric, and heating these coatings with an applied voltage. Moreover, this coating also enables fabrics to be antibacterial and flame retardant.Type: GrantFiled: August 23, 2016Date of Patent: April 23, 2019Inventors: Husnu Emrah Unalan, Doga Doganay, Sahin Coskun
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Patent number: 10263041Abstract: Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described.Type: GrantFiled: May 24, 2018Date of Patent: April 16, 2019Assignee: InVisage Technologies, Inc.Inventors: Edward Hartley Sargent, Jason Paul Clifford, Gerasimos Konstantatos, Ian Howard, Ethan J.D. Klem, Larissa Levina
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Patent number: 10255556Abstract: The present disclosure provides a quantum processor realized in a semiconductor material and method to operate the quantum processor to implement adiabatic quantum computation. The quantum processor comprises a plurality of qubit elements disposed in a two-dimensional matrix arrangement. The qubits are implemented using the nuclear or electron spin of phosphorus donor atoms. Further, the processor comprises a control structure with a plurality of control members, each arranged to control a plurality of qubits disposed along a line or a column of the matrix. The control structure is controllable to perform adiabatic quantum error corrected computation.Type: GrantFiled: November 3, 2015Date of Patent: April 9, 2019Assignees: NEWSOUTH INNOVATIONS PTY LIMITED, UNIVERSITY OF MELBOURNEInventors: Lloyd Christopher Leonard Hollenberg, Charles David Hill, Michelle Yvonne Simmons, Eldad Peretz, Sven Rogge, Martin Fuechsle, Samuel James Hile
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Patent number: 10249684Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.Type: GrantFiled: March 5, 2018Date of Patent: April 2, 2019Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Thomas Rueckes, X. M. Henry Huang, C. Rinn Cleavelin
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Patent number: 10243101Abstract: A light emitting diode can include a metal support layer: a GaN-based semiconductor structure having a less than 5 microns thickness on the metal support layer, the GaN-based semiconductor structure including a p-type GaN-based semiconductor layer, an active layer on the p-type GaN-based semiconductor layer, and an n-type GaN-based semiconductor layer on the active layer; a p-type electrode on the metal support layer and including a plurality of metal layers; an n-type electrode on a flat portion of an upper surface of the GaN-based semiconductor structure, and the n-type electrode contacts the flat portion; a metal pad layer on the n-type electrode; and an insulating layer including a first part disposed on the upper surface of the GaN-based semiconductor structure, and a second part disposed on an entire side surface of the GaN-based semiconductor structure, in which the metal pad layer includes a first portion having a flat bottom surface on the n-type electrode, and a second portion having stepped surfaceType: GrantFiled: December 4, 2017Date of Patent: March 26, 2019Assignee: LG INNOTEK CO., LTD.Inventors: Jong Lam Lee, In-kwon Jeong, Myung Cheol Yoo
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Patent number: 10233390Abstract: Light-emitting materials are made from a porous light-emitting semiconductor having quantum dots (QDs) disposed within the pores. According to some embodiments, the QDs have diameters that are essentially equal in size to the width of the pores. The QDs are formed in the pores by exposing the porous semiconductor to gaseous QD precursor compounds, which react within the pores to yield QDs. According to certain embodiments, the pore size limits the size of the QDs produced by the gas-phase reactions. The QDs absorb light emitted by the light-emitting semiconductor material and reemit light at a longer wavelength than the absorbed light, thereby “down-converting” light from the semiconductor material.Type: GrantFiled: February 17, 2017Date of Patent: March 19, 2019Assignee: Nanoco Technologies Ltd.Inventors: Nigel Pickett, Nathalie Gresty
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Patent number: 10229365Abstract: The present disclosure provides a quantum processor realized in a semiconductor material and method to operate the quantum processor to implement error corrected quantum computation. The quantum processor comprises a plurality of qubit elements disposed in a two-dimensional matrix arrangement. The qubits are implemented using the nuclear or electron spin of phosphorus donor atoms. Further, the processor comprises a control structure with a plurality of control members, each arranged to control a plurality of qubits disposed along a line or a column of the matrix. The control structure is controllable to perform topological quantum error corrected computation.Type: GrantFiled: November 3, 2015Date of Patent: March 12, 2019Assignees: NewSouth Innovations Pty Limited, University of MelbourneInventors: Martin Fuechsle, Samuel James Hile, Charles David Hill, Lloyd Christopher Leonard Hollenberg, Matthew Gregory House, Eldad Peretz, Sven Rogge, Michelle Yvonne Simmons
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Patent number: 10222314Abstract: A flow channel device, a complex permittivity measuring apparatus, and a dielectric cytometry system are provided which can improve the measurement accuracy. A constriction portion having a constricted space is disposed between an inflow port and an outflow port of a flow channel. Electrodes are arranged between the inflow port and the constriction portion and between the outflow port and the constriction portion. The conductance of the constriction portion at a low-limit frequency is less than the combined conductance of an inflow channel portion and an outflow channel portion. The capacitance of the constriction portion at a high-limit frequency is less than the combined capacitance of the inflow channel portion and the outflow channel portion.Type: GrantFiled: January 7, 2010Date of Patent: March 5, 2019Assignee: Sony CorporationInventors: Yoichi Katsumoto, Shinji Omori
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Patent number: 10217896Abstract: An optoelectronic semiconductor chip is disclosed. In an embodiment the optoelectronic semiconductor chip includes a p-type semiconductor region, an n-type semiconductor region, and an active layer arranged between the p-type semiconductor region and the n-type semiconductor region. The active layer is designed as a multiple quantum well structure, wherein the multiple quantum well structure has a first region of alternating first quantum well layers and first barrier layers and a second region having at least one second quantum well layer and at least one second barrier layer. The at least one second quantum well layer has an electronic band gap (EQW2) that is less than the electronic band gap (EQW1) of the first quantum well layers, and the at least one second barrier layer has an electronic band gap (EB2) that is greater than the electronic band gap (EB1) of the first barrier layers.Type: GrantFiled: November 25, 2015Date of Patent: February 26, 2019Assignee: OSRAM Opto Semiconductors GmbHInventors: Andreas Rudolph, Petrus Sundgren, Ivar Tangring
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Patent number: 10217632Abstract: A method of forming a semiconductor device is provided. The method includes depositing an aluminum-base interlayer on a silicon substrate, the aluminum-base interlayer having a thickness of less than about 100 nanometers; and growing a III-V compound material on the aluminum-base interlayer. The aluminum-base interlayer deposited directly on silicon allows for continuous and planar growth of III-V compound materials on the interlayer, which facilitates the manufacture of high quality electronic devices.Type: GrantFiled: June 9, 2016Date of Patent: February 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cheng-Wei Cheng, Sanghoon Lee, Kuen-Ting Shiu
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Patent number: 10205432Abstract: A piezoelectric thin film resonator includes: a piezoelectric film located on a substrate, and formed of stacked lower and upper piezoelectric films; lower and upper electrodes facing each other across at least a part of the piezoelectric film; and an insertion film inserted between the lower and upper piezoelectric films, wherein an air gap including a resonance region where the lower and upper electrodes face each other across the piezoelectric film and being larger than the resonance region is located under the lower electrode, and a multilayered film formed of the lower piezoelectric film, the insertion film, and the upper piezoelectric film is located in at least a part of a region located further out than an outer outline of the resonance region, further in than an outer outline of the air gap, and surrounding the resonance region, and is not located in a center region of the resonance region.Type: GrantFiled: November 18, 2016Date of Patent: February 12, 2019Assignee: TAIYO YUDEN CO., LTD.Inventors: Tsuyoshi Yokoyama, Jiansong Liu
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Patent number: 10204181Abstract: Systems and methods of modeling the structure and behavior of the quantum continuum based on geometrical principles are provided. In some embodiments, systems and methods of modeling quantum structure and behavior may include modeling a region of space as a three-dimensional projection of a field of N-dimensional hard-spheres, modeling a stable particle within the region of space as a locally stably packed set of hard-spheres, defining an energy subspace comprising one or more additional dimensions, and modeling an energy of the stable particle as an amount of hard-sphere geometry shifted out of the three spatial dimensions into the energy subspace sufficient for the set of hard-spheres to pack stably.Type: GrantFiled: July 8, 2016Date of Patent: February 12, 2019Assignee: Omnisent LLCInventors: Joseph Eric Henningsen, Clifford Tureman Lewis
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Patent number: 10205861Abstract: A transmissive optical shutter and a method of fabricating the same are provided. The transmissive optical shutter includes a first contact layer, an epitaxial layer disposed over the first contact layer, the epitaxial layer being configured to modulate intensity of incident light having a specific wavelength, a second contact layer disposed on the epitaxial layer, a first electrode disposed on the first contact layer, at least one second electrode disposed on the second contact layer, and a substrate disposed under the first contact layer.Type: GrantFiled: May 22, 2015Date of Patent: February 12, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sanghun Lee, Changyoung Park, Yonghwa Park
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Patent number: 10193067Abstract: Generally discussed herein are techniques for and systems and apparatuses configured to control phonons using an electric field. In one or more embodiments, an apparatus can include electrical contacts, two quantum dots embedded in a semiconductor such that when an electrical bias is applied to the electrical contacts, the electric field produced by the electrical bias is substantially parallel to an axis through the two quantum dots, and a phononic wave guide coupled to the semiconductor, the phononic wave guide configured to transport phonons therethrough.Type: GrantFiled: July 7, 2017Date of Patent: January 29, 2019Assignee: The Regents of the University of CaliforniaInventor: Michael Scheibner
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Patent number: 10186835Abstract: The monolithic integration of optically-pumped and electrically-injected III-nitride light-emitting devices. This structure does not involve the growth of p-type layers after an active region for a first III-nitride light-emitting device, and thus avoids high temperature growth steps after the fabrication of the active region for the first III-nitride light emitting device. Since electrical injection in such a structure cannot be possible, a second III-nitride light-emitting device is used to optically pump the first III-nitride light emitting device. This second III-nitride light emitting device emits light at a shorter wavelength region of the optical spectrum than the first III-nitride light emitting device, so that it can be absorbed by the active region of the first III-nitride light-emitting device, which in turn emits light at a longer wavelength region of the optical spectrum than the second III-nitride light emitting device.Type: GrantFiled: December 30, 2014Date of Patent: January 22, 2019Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Robert M. Farrell, Shuji Nakamura, Claude C. A. Weisbuch
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Patent number: 10186676Abstract: Embodiments related to emissive devices for displays are discussed. Some embodiments include light emitting diodes including an electron transport layer core having a tube shape with an inner and an outer sidewall, an emission layer on the inner and outer sidewalls, and a hole transport layer on the emission layer, displays and systems including such light emitting diodes, and methods for fabricating them. Other embodiments include emissive laser devices having an emission layer between a hole transport layer and an electron transport layer and first and second metasurface mirrors adjacent to the hole transport layer and the electron transport layer, respectively, displays and systems including such emissive laser devices, and methods for fabricating them.Type: GrantFiled: March 12, 2018Date of Patent: January 22, 2019Assignee: Intel CorporationInventors: Khaled Ahmed, Ali Khakifirooz, Richmond Hicks
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Patent number: 10173454Abstract: The invention relates to a security and/or value document having a security feature, to an ink for making the security feature, to a method for making such a security and/or value document, and to a method for verifying such a security and/or value document.Type: GrantFiled: July 7, 2016Date of Patent: January 8, 2019Inventor: Malte Pflughoefft
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Patent number: 10162210Abstract: The present disclosure provides a touch panel, a method for producing the same and a display apparatus. The touch panel includes: a first substrate, a second substrate opposed to the first substrate, a display medium layer between the first substrate and the second substrate, a black matrix arranged on one of the first substrate and the second substrate, a plurality of driving electrode units and a plurality of inductive electrode units arranged alternatively on the other one of the first substrate and the second substrate, and each of the plurality of driving electrode units or the plurality of inductive electrode units includes a plurality of transparent electrodes and projections of boundaries of the transparent electrodes onto the substrate having the black matrix are covered by the black matrix or coincide with the range of the black matrix.Type: GrantFiled: October 28, 2014Date of Patent: December 25, 2018Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Xiangxiang Zou
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Patent number: 10153273Abstract: A semiconductor device is provided that comprises a base structure, a first channel layer overlying the base structure, a second channel layer overlying the first channel layer, and first, second, and third ohmic contacts overlying the second channel layer. The semiconductor device further comprises a metal-semiconductor heterodimension field effect transistor that is formed between the first and second ohmic contacts, the metal-semiconductor heterodimension field effect transistor including a first gate formed through the first and second channel layers. The semiconductor device yet further comprises a high electron mobility transistor formed between the second and third ohmic contacts, the high electron mobility transistor including a second gate formed through the second channel layer without extending through the first channel layer.Type: GrantFiled: December 5, 2017Date of Patent: December 11, 2018Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Roger S. Tsai, Weidong Liu, Yeong-Chang Chou
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Patent number: 10146070Abstract: An optical phase modulator 100 according to an embodiment of this disclosure comprises a rib-type waveguide structure 110 comprising: a PN junction 106 comprising Si and formed in a lateral direction on a substrate; and a Si1-xGex layer 108 that is doped with a p-type impurity and comprises at least one layer laminated on the PN junction 106, so as to be electrically connected to the PN junction 106.Type: GrantFiled: February 2, 2016Date of Patent: December 4, 2018Assignee: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATIONInventors: Junichi Fujikata, Shigeki Takahashi, Mitsuru Takenaka, Younghyun Kim
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Patent number: 10141437Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.Type: GrantFiled: June 16, 2017Date of Patent: November 27, 2018Assignee: Intel CorporationInventors: Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Amlan Majumdar, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
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Patent number: 10141500Abstract: A magnetoelectric converting element includes a substrate, a magnetosensitive layer, a first insulating layer, an underlying conductive layer, a second insulating layer, and a terminal conductor. The magnetosensitive layer is formed on the substrate. The first insulating layer is formed with first opening for exposing a part of the magnetosensitive layer. The underlying conductive layer is formed on the exposed part of the magnetosensitive layer. The second insulating layer is formed with a second opening for exposing a part of the underlying conductive layer. The terminal conductor is formed on the exposed part of the underlying conductive layer. The second opening is arranged to be located inside the first opening in plan view.Type: GrantFiled: July 3, 2017Date of Patent: November 27, 2018Assignee: ROHM CO., LTD.Inventors: Isamu Nishimura, Michihiko Mifuji, Satoshi Nakagawa
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Patent number: 10128439Abstract: A phononic transistor can be realized by arranging a row of cantilevered structures with attached magnets, elastically extending upward upon application of a magnetic repulsive force to the magnets. In the extended configuration, the phonons are transmitted from source to drain, while in the flattened configuration the phonons are blocked from transmission. A gate element controls the ON and OFF states of the phononic transistor.Type: GrantFiled: April 17, 2018Date of Patent: November 13, 2018Assignees: CALIFORNIA INSTITUTE OF TECHNOLOGY, ETH ZUERICHInventors: Osama R. Bilal, Chiara Daraio, Andre Foehr
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Patent number: 10128417Abstract: Embodiments of a display device including barrier layer coated quantum dots and a method of making the barrier layer coated quantum dots are described. Each of the barrier layer coated quantum dots includes a core-shell structure and a hydrophobic barrier layer disposed on the core-shell structure. The hydrophobic barrier layer is configured to provide a distance between the core-shell structure of one of the quantum dots with the core-shell structures of other quantum dots that are in substantial contact with the one of the quantum dots. The method for making the barrier layer coated quantum dots includes forming reverse micro-micelles using surfactants and incorporating quantum dots into the reverse micro-micelles. The method further includes individually coating the incorporated quantum dots with a barrier layer and isolating the barrier layer coated quantum dots with the surfactants of the reverse micro-micelles disposed on the barrier layer.Type: GrantFiled: December 2, 2016Date of Patent: November 13, 2018Assignee: Nanosys, Inc.Inventors: Jason Hartlove, Veeral Hardev, Shihai Kan, Jian Chen, Jay Yamanaga, Christian Ippen, Wenzhuo Guo, Charles Hotz, Robert Wilson
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Patent number: 10115859Abstract: A symmetrical quantum well active layer provides enhanced internal quantum efficiency. The quantum well active layer includes an inner (central) layer and a pair of outer layers sandwiching the inner layer. The inner and outer layers have different thicknesses and bandgap characteristics. The outer layers are relatively thick and include a relatively low bandgap material, such as InGaN. The inner layer has a relatively lower bandgap material and is sufficiently thin to act as a quantum well delta layer, e.g., comprising approximately 6 ? or less of InN. Such a quantum well structure advantageously extends the emission wavelength into the yellow/red spectral regime, and enhances spontaneous emission. The multi-layer quantum well active layer is sandwiched by barrier layers of high bandgap materials, such as GaN.Type: GrantFiled: December 15, 2010Date of Patent: October 30, 2018Assignee: Lehigh UniversityInventors: Nelson Tansu, Hongping Zhao, Guangyu Liu, Gensheng Huang
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Patent number: 10109762Abstract: A light source includes an upper electrode layer, a lower electrode layer, and an active layer interposed therebetween. At least one of the upper and lower electrode layers is divided into a plurality of electrodes separated from each other in an in-plane direction of the active layer. The separated electrodes independently inject current into a plurality of different regions in the active layer. The light source emits light by injecting current from the upper and lower electrode layers into the active layer, guide the light in the in-plane direction, and output the light. The plurality of different regions in the active layer include a first region not including a light exit end and a second region including the light exit end, and the second region is configured to emit light of at least first-order level. The active layer has an asymmetric multiple quantum well structure.Type: GrantFiled: September 26, 2013Date of Patent: October 23, 2018Assignee: Canon Kabushiki KaishaInventors: Kenji Yamagata, Toshimitsu Matsuu, Takeshi Yoshioka, Takeshi Uchida
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Patent number: 10103328Abstract: According to one embodiment, a nonvolatile memory device includes a first conductive layer, a second conductive layer, and an intermediate layer. The first conductive layer includes a first element. The first element includes a at least one selected from the group consisting of Ag, Cu, Ni, Co, Ti, Al, and Au. The intermediate layer is provided between the first conductive layer and the second conductive layer. The intermediate layer includes an oxide. The oxide includes a second element and a third element. The second element includes at least one second element being selected from the group consisting of Ti, Ta, Hf, W, Mg, Al, and Zr. The third element is different from the second element and includes at least one selected from the group consisting of Si, Ge, Hf, Al, Ta, W, Zr, Ti, and Mg.Type: GrantFiled: December 21, 2016Date of Patent: October 16, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takayuki Ishikawa, Harumi Seki, Shosuke Fujii, Masumi Saitoh
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Patent number: 10101520Abstract: The present disclosure provides a light conversion film and a preparation method thereof, and a liquid crystal display device. The light conversion film comprises a first substrate, a thin film layer, a quantum dot layer in which quantum dots are distributed, and a second substrate, which are all successively stacked, wherein said thin film layer is a transparent sheet having an electric field on a surface thereof, and said quantum dots are orderly arrayed due to said electric field.Type: GrantFiled: April 4, 2016Date of Patent: October 16, 2018Assignees: HISENSE ELECTRIC CO., LTD., HISENSE USA CORPORATION, HISENSE INTERNATIONAL CO., LTD.Inventors: Xuhai Liu, Jianwei Cao, Shunming Huang, Fulin Li
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Patent number: 10096748Abstract: Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting devices, and associated systems and methods are disclosed. A solid state radiative semiconductor structure in accordance with a particular embodiment includes a first region having a first value of a material characteristic and being positioned to receive radiation at a first wavelength. The structure can further include a second region positioned adjacent to the first region to emit radiation at a second wavelength different than the first wavelength. The second region has a second value of the material characteristic that is different than the first value, with the first and second values of the characteristic forming a potential gradient to drive electrons, holes, or both electrons and holes in the radiative structure from the first region to the second region. In a further particular embodiment, the material characteristic includes material polarization.Type: GrantFiled: March 28, 2016Date of Patent: October 9, 2018Assignee: Micron Technology, Inc.Inventors: Martin F. Schubert, Vladimir Odnoblyudov
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Patent number: 10074056Abstract: Systems and methods are provided for performing noise-resilient quantum operations. A set of control signals are applied to a system to provide a first Hamiltonian for the system. The system includes an array of physical qubits and a plurality of coupling mechanisms configured such that each pair of neighboring physical qubits within the array is coupled by an associated coupling mechanism. The first Hamiltonian represents, for each coupling mechanism, a coupling strength between zero and a maximum value. An adiabatic interpolation of the Hamiltonian of the system from the first Hamiltonian to a second Hamiltonian is performed. The second Hamiltonian represents, for at least one of the plurality of coupling mechanisms, a coupling strength different from that of the first Hamiltonian.Type: GrantFiled: August 1, 2016Date of Patent: September 11, 2018Assignee: Northrop Grumman Systems CorporationInventor: Ryan J. Epstein
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Patent number: 10069035Abstract: One embodiment relates to a light-emitting device, a method for manufacturing the light-emitting device, a light-emitting device package, and a lighting system. The light-emitting device, according to the one embodiment, can comprise: a first conductive semiconductor layer; an active layer on the first conductive semiconductive layer; a gallium nitride based superlattice layer on the active layer; and a second conductive semiconductor layer on the gallium nitride based superlattice layer. The gallium nitride based superlattice layer can comprise: a first gallium nitride based superlattice layer on the active layer; and a second gallium nitride based superlattice layer on the first gallium nitride based superlattice layer.Type: GrantFiled: July 24, 2015Date of Patent: September 4, 2018Assignee: LG INNOTEK CO., LTD.Inventors: Chan Keun Park, Jae Woong Han
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Patent number: 10050414Abstract: An array of monolithic wavelength division multiplexed (WDM) vertical cavity surface emitting lasers (VCSELs) is provided with quantum well intermixing. Each VCSEL includes a bottom distributed Bragg reflector (DBR), an upper distributed Bragg reflector, and a laser cavity therebetween. The laser cavity includes a multiple quantum well (MQW) layer sandwiched between a lower separate confinement heterostructure (SCH) and an upper SCH layer. Each MQW region experiences a different amount of quantum well intermixing and concomitantly a different lasing wavelength shift.Type: GrantFiled: January 22, 2015Date of Patent: August 14, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Sagi Varghese Mathai, Michael Renne Ty Tan
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Patent number: 10031887Abstract: Techniques for improving the performance of a quantum processor are described. The techniques include reading out a fraction of the qubits in a quantum processor and utilizing one or more post-processing operations to reconstruct qubits of the quantum processor that are not read. The reconstructed qubits may be determined using a perfect sampler to provide results that are strictly better than reading all of the qubits directly from the quantum processor. The composite sample that includes read qubits and reconstructed qubits may be obtained faster than if all qubits of the quantum processor are read directly.Type: GrantFiled: September 3, 2015Date of Patent: July 24, 2018Assignee: D-WAVE SYSTEMS INC.Inventor: Jack Raymond
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Patent number: 10026863Abstract: A method of manufacturing a sensor array includes providing a carrier glass substrate, forming an amorphous silicon layer over the carrier glass substrate, forming a first heat buffer layer over the amorphous silicon layer; forming a mirror layer over the first heat buffer layer; forming a second heat buffer layer over the mirror layer; forming a flexible substrate over the second heat buffer layer; and forming an active device layer over the flexible substrate. The method of the present invention further comprises exposing the sensor array to light from a flash lamp and then detaching the carrier glass substrate from the sensor array. The method of the present invention optionally further comprises filtering the light from the flash lamp to wavelengths below 350 nm.Type: GrantFiled: April 20, 2017Date of Patent: July 17, 2018Assignee: DPIX, LLCInventors: Frank Caris, Shawn Michael O'Rourke, Byung-Kyu Park, Terri Renae Pederson
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Patent number: 10026834Abstract: A method of manufacturing an enhanced device and an enhance device are provided. The method comprises: preparing a substrate, and forming a non-planar structure in the substrate; depositing a nitride channel layer on the substrate, a gate region, a source region and a drain region being defined on the nitride channel layer, the gate region of the nitride channel layer having a non-planar structure transferred from the non-planar structure of the substrate; depositing a nitride barrier layer on the nitride channel layer, the nitride barrier layer having a non-planar structure located above and corresponding to the non-planar structure of the nitride channel layer, the nitride barrier layer and the nitride channel layer forming a nitride channel layer/nitride barrier layer heterojunction.Type: GrantFiled: June 23, 2016Date of Patent: July 17, 2018Assignee: ENKRIS SEMICONDUCTOR, INC.Inventor: Kai Cheng
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Patent number: 10020639Abstract: A laser diode arrangement comprising: at least one semiconductor substrate; at least two laser stacks based on the AlInGaN material system, each laser stack having an active zone, wherein at least one of the at least two laser stacks comprises a two-dimensional structure of laser diodes; and at least one intermediate layer. The laser stacks and the intermediate layer are grown monolithically on the semiconductor substrate. The intermediate layer is arranged between the laser stacks. The active zone of the first laser stack can be actuated separately from the active zone of the at least one further laser stack.Type: GrantFiled: May 26, 2017Date of Patent: July 10, 2018Assignee: OSRAM Opto Semiconductors GmbHInventors: Alfred Lell, Martin Strassburg
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Patent number: 10008543Abstract: Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described.Type: GrantFiled: October 3, 2017Date of Patent: June 26, 2018Assignee: INVISAGE TECHNOLOGIES, INC.Inventors: Edward Hartley Sargent, Jason Paul Clifford, Gerasimos Konstantatos, Ian Howard, Ethan J. D. Klem, Larissa Levina
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Patent number: 10000381Abstract: Systems and methods for MBE growing of group-III Nitride alloys, comprising establishing an average reaction temperature range from about 250 C to about 850 C; introducing a nitrogen flux at a nitrogen flow rate; introducing a first metal flux at a first metal flow rate; and periodically stopping and restarting the first metal flux according to a first flow duty cycle. According to another embodiment, the system comprises a nitrogen source that provides nitrogen at a nitrogen flow rate, and, a first metal source comprising a first metal effusion cell that provides a first metal at a first metal flow rate, and a first metal shutter that periodically opens and closes according to a first flow duty cycle to abate and recommence the flow of the first metal from the first metal source. Produced alloys include AlN, InN, GaN, InGaN, and AlInGaN.Type: GrantFiled: September 21, 2015Date of Patent: June 19, 2018Assignee: Georgia Tech Research CorporationInventors: Michael William Moseley, William Alan Doolittle
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Patent number: 9996802Abstract: An optical system comprising a charged quantum dot having, a charged carrier, first and second ground state levels and a plurality of excited state levels, the first and second ground state energy levels having different spin states such that the said charged carrier cannot transfer between the first and second ground state energy levels without changing its spin state, the system further comprising a controller adapted to control a first radiating beam with energy not more than 100 micro-eV from a first transition within said quantum dot from a first ground state level to a selected excited state level from the plurality of excited state levels to, the system being adapted to enhance the decay rate of a second transition within said quantum dot from the selected excited state level to a second ground state level, but not a first transition, such that a photon is produced due to scattering of a photon from the first radiating beam, wherein the controller is adapted to irradiate the quantum dot with the firType: GrantFiled: February 16, 2017Date of Patent: June 12, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Anthony John Bennett, Andrew James Shields
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Patent number: 9995964Abstract: The present invention relates to a liquid crystal display panel and a display device. The liquid crystal display panel comprises a first substrate and a second substrate assembled in an aligned manner, and further comprises a reflecting layer, a light wavelength conversion layer and a quantum dot layer; the reflecting layer is provided on the second substrate, the quantum dot layer is provided on the first substrate or the second substrate, and the reflecting layer and the quantum dot layer are arranged in a direction from the second substrate to the first substrate; the light wavelength conversion layer is made from an upconversion material and provided between the reflecting layer and the quantum dot layer. The above liquid crystal display panel has a higher utilization of ambient light, and thus has higher brightness and contrast ratio.Type: GrantFiled: June 11, 2015Date of Patent: June 12, 2018Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Bin Zhang, Tingting Zhou, Zhijun Lv
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Patent number: 9988737Abstract: An epitaxial diamond layer and a method for the production thereof can be provided that comprises the following steps: providing a substrate; depositing a metal layer on at least a subarea of the substrate, wherein the metal layer contains, or consists of, at least one period 4, 5 or 6 metal having a melting point of greater than or equal to 1200 K; and depositing a diamond layer on at least a subarea of the metal layer; wherein at least one intermediate layer is deposited between the metal layer and the diamond layer and has a higher lattice constant than undoped crystalline diamond and a lower hardness than undoped crystalline diamond.Type: GrantFiled: January 15, 2016Date of Patent: June 5, 2018Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Christoph E Nebel, Claudia Widmann
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Patent number: 9991172Abstract: In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.Type: GrantFiled: April 13, 2015Date of Patent: June 5, 2018Assignee: Intel CorporationInventors: Mantu K. Hudait, Jack T. Kavalieros, Suman Datta, Marko Radosavljevic
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Patent number: 9991370Abstract: High electron mobility leads to better device performance and today is achieved by fabricating “gated devices” within a high-mobility two-dimensional electron gas (2DEG. However, the fabrication techniques used to form these devices lead to rapid degradation of the 2DEG quality which then can limits the mobility of the electronic devices. Accordingly, it would be beneficial to provide a process/technique which circumvents this processing and 2DEG layer damage. By exploiting a flip-chip methodology such damaging processing steps are separated to a second die/wafer which is then coupled to the 2DEG wafer. Extensions of the technique with two or more different semiconductor materials or material systems may be employed in conjunction with one or more electronic circuits to provide 2DEG enabled circuits in 2D and/or 3D stacked configurations. Further semiconductor materials providing EG elements may incorporate one or more of 2DEG, 1DEG, and “zero” DEG structures.Type: GrantFiled: December 9, 2015Date of Patent: June 5, 2018Assignee: THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING/MCGILL UNIVERSITYInventors: Guillaume Gervais, Keyan Bennaceur
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Patent number: 9978940Abstract: A device is disclosed which comprises a first electrode (101), a second electrode (104) spaced from the first electrode, a switching region (102) positioned between the first electrode and the second electrode, and an intermediate region (103) positioned between the switching region and the second electrode, wherein the intermediate region is in electrical contact with the switching region and the second electrode. Preferably, the intermediate region comprises metal nanowires (105) in a polymer matrix, and the device is a memristor or a memcapacitor. In the latter case, the switching region comprises a conductive material (106) and an insulating material (107).Type: GrantFiled: October 23, 2014Date of Patent: May 22, 2018Assignee: Provenance Asset Group LLCInventors: Alexander Alexandrovich Bessonov, Dmitrii Igorevich Petukhov, Marina Nikolaevna Kirikova, Marc Bailey, Tapani Ryhanen
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Patent number: 9966497Abstract: A method of fabricating a nonpolar gallium nitride-based semiconductor layer is provided. The method is a method of fabricating a nonpolar gallium nitride layer using metal organic chemical vapor deposition, and includes disposing a gallium nitride substrate with an m-plane growth surface within a chamber, raising a substrate temperature to a GaN growth temperature by heating the substrate, and growing a gallium nitride layer on the gallium nitride substrate by supplying a Ga source gas, an N source gas, and an ambient gas into the chamber at the growth temperature. The supplied ambient gas contains N2 and does not contain H2.Type: GrantFiled: May 8, 2015Date of Patent: May 8, 2018Assignee: Seoul Viosys Co., Ltd.Inventors: Seung Kyu Choi, Chae Hon Kim, Jung Whan Jung
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Patent number: 9966257Abstract: A composition of matter comprising at least one nanowire on a graphitic substrate, said at least one nanowire having been grown epitaxially on said substrate, wherein said nanowire comprises at least one group III-V compound or at least one group II-VI compound or comprises at least one non carbon group (IV) element.Type: GrantFiled: December 13, 2011Date of Patent: May 8, 2018Assignee: Norwegian University of Science and TechnologyInventors: Helge Weman, Bjørn-Ove Fimland, Dong Chul Kim
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Patent number: 9960315Abstract: A light emitting heterostructure including a partially relaxed semiconductor layer is provided. The partially relaxed semiconductor layer can be included as a sublayer of a contact semiconductor layer of the light emitting heterostructure. A dislocation blocking structure also can be included adjacent to the partially relaxed semiconductor layer.Type: GrantFiled: December 21, 2016Date of Patent: May 1, 2018Assignee: Sensor Electronic Technology, Inc.Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska