Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

Abstract: A light emitting device includes: a first layer made of a semiconductor of a first conductivity type; a second layer made of a semiconductor of a second conductivity type; an active layer including a multiple quantum well provided between the first layer and the second layer, impurity concentration of the first conductivity type in each barrier layer of the multiple quantum well having a generally flat distribution or increasing toward the second layer, average of the impurity concentration in the barrier layer on the second layer side as viewed from each well layer of the multiple quantum well being equal to or greater than average of the impurity concentration in the barrier layer on the first layer side, and average of the impurity concentration in the barrier layer nearest to the second layer being higher than average of the impurity concentration in the barrier layer nearest to the first layer.

Abstract: An epitaxial substrate for an electronic device having a Si single crystal substrate, a buffer as an insulating layer formed on the Si single crystal substrate, and a main laminated body formed by plural group III nitride layers epitaxially grown on the buffer, wherein a lateral direction of the epitaxial substrate is defined as an electric current conducting direction. The buffer including at least an initially grown layer in contact with the Si single crystal substrate and a superlattice laminate constituted of a superlattice multilayer structure on the initially grown layer.

Abstract: An inventive nitride semiconductor device includes: a substrate; a first buffer layer provided on the substrate, and having a superlattice structure which includes two types of Group III nitride semiconductor sublayers having different compositions and alternately stacked in pairs; a second buffer layer provided on the first buffer layer in contact with the first buffer layer, and having a superlattice structure which includes two types of Group III nitride semiconductor sublayers having different compositions and alternately stacked in pairs; and a device operation layer of a Group III nitride semiconductor provided on the second buffer layer; wherein an average lattice constant LC1 of the first buffer layer, an average lattice constant LC2 of the second buffer layer and an average lattice constant LC3 of the device operation layer satisfy the following expression (1): LC1<LC2<LC3??(1).

Abstract: A reflecting light emitting structure includes a substrate having a plurality of grooves formed in a first face of the substrate is disclosed. The first face is in a first crystallographic plane. Each of the plurality of grooves includes a first sidewall that is coplanar with a second crystallographic plane and a second sidewall that is coplanar with a third crystallographic plane. A buffer layer is provided on the substrate to reduce mechanical strain between the substrate and a light emitting diode (LED) fabricated on the buffer layer.

Abstract: A nitride semiconductor element includes: a strain suppression layer formed on a silicon substrate via an initial layer; and an operation layer formed on the strain suppression layer. The strain suppression layer includes a first spacer layer, a second spacer layer formed on and in contact with the first spacer layer, and a superlattice layer formed on and in contact with the second spacer layer. The first spacer layer is larger in lattice constant than the second spacer layer. The superlattice layer has first layers and second layers smaller in lattice constant than the first layers stacked alternately on top of one another. The average lattice constant of the superlattice layer is smaller than the lattice constant of the first spacer layer and larger than the lattice constant of the second spacer layer.

Abstract: An LED semiconductor body includes a semiconductor layer sequence which comprises a quantum structure which is intended to produce radiation and comprises at least one quantum layer and at least one barrier layer, wherein the quantum layer and the barrier layer are strained with mutually opposite mathematical signs.

Abstract: A method of manufacturing a quantum dot layer, and a quantum dot optoelectronic device including the quantum dot layer. The method includes sequentially stacking a self-assembled monolayer, a sacrificial layer, and a quantum dot layer on a source substrate; disposing a stamp on the quantum dot layer; picking up the sacrificial layer, the quantum dot layer and the stamp; and removing the sacrificial layer from the quantum dot layer using a solution that dissolves the sacrificial layer.

Abstract: The present invention relates to growth of vertically-oriented crystalline nanowire arrays upon a transparent conductive or other substrate for use in 3rd generation photovoltaic and other applications. A method of growing crystalline anatase nanowires includes the steps of: deposition of titania onto a substrate; conversion of the titania into titanate nanowires; and, treatment of the titanate nanowires to produce crystalline anatase nanowires.

Abstract: A semiconductor structure includes a substrate, a nucleation layer on the substrate, a compositionally graded layer on the nucleation layer, and a layer of a nitride semiconductor material on the compositionally graded layer. The layer of nitride semiconductor material includes a plurality of substantially relaxed nitride interlayers spaced apart within the layer of nitride semiconductor material. The substantially relaxed nitride interlayers include aluminum and gallium and are conductively doped with an n-type dopant, and the layer of nitride semiconductor material including the plurality of nitride interlayers has a total thickness of at least about 2.0 ?m.

Abstract: A laterally contacted blue LED device involves a PAN structure disposed over an insulating substrate. The substrate may be a sapphire substrate that has a template layer of GaN grown on it. The PAN structure includes an n-type GaN layer, a light-emitting active layer involving indium, and a p-type GaN layer. The n-type GaN layer has a thickness of at least 500 nm. A Low Resistance Layer (LRL) is disposed between the substrate and the PAN structure such that the LRL is in contact with the bottom of the n-layer. In one example, the LRL is an AlGaN/GaN superlattice structure whose sheet resistance is lower than the sheet resistance of the n-type GnA layer. The LRL reduces current crowding by conducting current laterally under the n-type GaN layer. The LRL reduces defect density by preventing dislocation threads in the underlying GaN template from extending up into the PAN structure.

Abstract: Embodiments of a material having low cross-plane thermal conductivity are provided. Preferably, the material is a thermoelectric material. In general, the thermoelectric material is designed to block phonons, which reduces or eliminates heat transport due to lattice vibrations and thus cross-plane thermal conductivity. By reducing the thermal conductivity of the thermoelectric material, a figure-of-merit (ZT) of the thermoelectric material is improved. In one embodiment, the thermoelectric material includes multiple superlattice periods that block, or reflect, multiple phonon wavelengths.

Abstract: A light emitting element includes a semiconductor substrate, a light emitting part having a first and second conductivity type cladding layers and an active layer sandwiched between the cladding layers. A reflecting part is disposed between the substrate and the light emitting part. A current dispersing layer disposed on a side of the light emitting part opposite to the reflecting. The reflecting part has at least three pair layers of first and second semiconductor layers, the first semiconductor layer has a first thickness, the second semiconductor layer has a second thickness and a plurality of pair layers of the reflecting part have a different thickness to each other as values of the incident angle of light are different with respect to each pair layer. At least one pair layer is defined by the incident angle of light being not less than 50 degrees.

Abstract: A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed.

Abstract: The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly.

Abstract: Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.

Abstract: A matrix with at least one embedded array of nanowires and method thereof. The matrix includes nanowires and one or more fill materials located between the nanowires. Each of the nanowires including a first end and a second end. The nanowires are substantially parallel to each other and are fixed in position relative to each other by the one or more fill materials. Each of the one or more fill materials is associated with a thermal conductivity less than 50 Watts per meter per degree Kelvin. And, the matrix is associated with at least a sublimation temperature and a melting temperature, the sublimation temperature and the melting temperature each being above 350° C.

Abstract: An embodiment of the invention relates to a memory comprising a strained double-heterostructure having an inner semiconductor layer which is sandwiched between two outer semiconductor layers, wherein the lattice constant of the inner semiconductor layer differs from the lattice constants of the outer semiconductor layers, the resulting lattice strain in the double-heterostructure inducing the formation of at least one quantum dot inside the inner semiconductor layer, said at least one quantum dot being capable of storing charge carriers therein, and wherein, due to the lattice strain, the at least one quantum dot has an emission barrier of 1.15 eV or higher, and provides an energy state density of at least three energy states per 1000 nm3, all said at least three energy states being located in an energy band of 50 meV or less.

Abstract: A semiconductor light emitting device includes a first layer made of at least one of n-type GaN and n-type AlGaN; a second layer made of Mg-containing p-type AlGaN; and a light emitting section provided between the first layer and the second layer. The light emitting section included a plurality of barrier layers made of Si-containing AlxGa1-x-yInyN (0?x, 0?y, x+y?1), and a well layer provided between each pair of the plurality of barrier layers and made of GaInN or AlGaInN. The plurality of barrier layers have a nearest barrier layer and a far barrier layer. The nearest barrier layer is nearest to the second layer among the plurality of barrier layers. The nearest barrier layer includes a first portion and a second portion. The first portion is made of Si-containing AlxGa1-x-yInyN (0?x, 0?y, x+y?1). The second portion is provided between the first portion and the second layer and is made of AlxGa1-x-yInyN (0?x, 0?y, x+y?1).

Abstract: A radiation-emitting semiconductor body includes a contact layer and an active zone. The semiconductor body has a tunnel junction arranged between the contact layer and the active zone. The active zone has a multi-quantum well structure containing at least two active layers that emit electromagnetic radiation when an operating current is impressed into the semiconductor body.

Abstract: A method for manufacturing a field effect transistor, includes: forming a mask of an insulating film on a semiconductor layer containing Si formed on a semiconductor substrate; forming the semiconductor layer into a mesa structure by performing etching with the use of the mask, the mesa structure extending in a direction parallel to an upper face of the semiconductor substrate; narrowing a distance between two sidewalls of the mesa structure and flattening the sidewalls by performing a heat treatment in a hydrogen atmosphere, the two sidewalls extending in the direction and facing each other; forming a gate insulating film covering the mesa structure having the sidewalls flattened; forming a gate electrode covering the gate insulating film; and forming source and drain regions at portions of the mesa structure, the portions being located on two sides of the gate electrode.

Abstract: The present invention relates to a light-emitting device using a clad layer consisting of asymmetric units, wherein the clad layer is provided by repeatedly stacking a unit having an asymmetric energy bandgap on upper and lower portions of an active layer, and the inflow of both electrons and holes into the active layer is arbitrarily controlled through the clad layer, so that the internal quantum efficiency can be improved. The light-emitting device using the clad layer consisting of the asymmetric units according to the present invention is characterized in that the clad layer is provided on at least one of the upper and lower portions of the active layer and consists of one or plural units, wherein the unit has a structure in which the first to nth unit layers (n is a natural number equal to or greater than three) having different energy bandgaps are sequentially stacked and has an asymmetric energy band diagram.

Abstract: The invention relates to a process for deposition of elongated nanoparticles from a liquid carrier onto a substrate, and to electronic devices prepared by this process.

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

Abstract: Devices (e.g., optoelectronic devices such as solar cells and infrared or THz photodetectors) with a nanomaterial having vertically correlated quantum dots with built-in charge (VC Q-BIC) and methods of making such devices. The VC Q-BIC material has two or more quantum dot layers, where the layers have quantum dots (individual quantum dots or quantum dot clusters) in a semiconductor material, and adjacent quantum dot layers are separated by a spacer layer of doped semiconductor material. The VC-QBIC nanomaterial provides long photocarrier lifetime, which improves the responsivity and sensitivity of detectors or conversion efficiency in solar cells as compared to previous comparable devices.

Abstract: Provided is a nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed above the first nitride semiconductor layer; and a delta doped second nitride semiconductor layer formed above the active layer. According to the present invention, the optical power of the nitride semiconductor light emitting device is enhanced, optical power down phenomenon is improved and reliability against ESD (electro static discharge) is enhanced.

Abstract: An optoelectronic device includes a first electrode, a quantum dot layer disposed on the first electrode including a plurality of quantum dots, a fullerene layer disposed directly on the quantum dot layer wherein the quantum dot layer and the fullerene layer form an electronic heterojunction, and a second electrode disposed on the fullerene layer. The device may include an electron blocking layer. The quantum dot layer may be modified by a chemical treatment to exhibit in creased charge carrier mobility.

Abstract: There is provided a nitride semiconductor light emitting device. A nitride semiconductor light emitting device according to an aspect of the invention may include: an n-type nitride semiconductor layer provided on a substrate; an active layer provided on the n-type nitride semiconductor layer, and including quantum barrier layers and quantum well layers; and a p-type nitride semiconductor layer provided on the active layer, wherein each of the quantum barrier layers includes a plurality of InxGa(1-x)N layers (0<x<1) and at least one AlyGa(1-y)N layer (0?y<1), and the AlyGa(1-y)N layer is stacked between the InxGa(1-x)N layers.

Abstract: A fabrication method of a surface-emitting laser element includes a step of preparing a conductive GaN multiple-region substrate including a high dislocation density high conductance region, a low dislocation density high conductance region and a low dislocation density low conductance region, as a conductive GaN substrate; a semiconductor layer stack formation step of forming a group III-V compound semiconductor layer stack including an emission layer on the substrate; and an electrode formation step of forming a semiconductor layer side electrode and a substrate side electrode. The semiconductor layer and electrodes are formed such that an emission region into which carriers flow in the emission layer is located above and within the span of the low dislocation density high conductance region. Thus, a surface-emitting laser element having uniform light emission at the emission region can be obtained with favorable yield.

Abstract: A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.

Abstract: According to one embodiment, a nitride semiconductor device includes a substrate, an Alx1Ga1-x1N first buried layer, an InyAlzGa1-y-zN buried layer and an Alx2Ga1-x2N second buried layer. The substrate has protrusions formed in an in-plane direction on a first major surface, and a depression between adjacent ones of the protrusions. The first buried layer is formed on the depression and one of the protrusions. The InyAlzGa1-y-zN buried layer is formed on the first buried layer. The second buried layer is formed on the InyAlzGa1-y-zN buried layer. A portion of the first buried layer formed on the depression and a portion of the first buried layer formed on the one of the protrusions are not connected to each other. A portion of the InyAlzGa1-y-zN buried layer formed above the depression and a portion of the InyAlzGa1-y-zN buried layer formed above the one of the protrusions are connected to each other.

Abstract: Provided are a ZnO-based thin film and a ZnO-based semiconductor device which allow: reduction in a burden on a manufacturing apparatus; improvement of controllability and reproducibility of doping; and obtaining p-type conduction without changing a crystalline structure. In order to be formed into a p-type ZnO-based thin film, a ZnO-based thin film is formed by employing as a basic structure a superlattice structure of a MgZnO/ZnO super lattice layer 3. This superlattice component is formed with a laminated structure which includes acceptor-doped MgZnO layers 3b and acceptor-doped ZnO layers 3a. Hence, it is possible to improve controllability and reproducibility of the doping, and to prevent a change in a crystalline structure due to a doping material.

Abstract: The invention is a vertical geometry light emitting diode capable of emitting light in the electromagnetic spectrum having a substrate, a lift-off layer, a strain relieved superlattice layer, a first doped layer, a multilayer quantum wells comprising alternating layers quantum wells and barrier layers, a second doped layer, a third doped layer and a metallic contact that is in a vertical geometry orientation. The different layers consist of a compound with the formula AlxlnyGa(1-x-y)N, wherein x is more than 0 and less than or equal to 1, y is from 0 to 1 and x+y is greater than 0 and less than or equal to 1. The barrier layer on each surface of the quantum well has a band gap larger than a quantum well bandgap. The first and second doped layers have different conductivities. The contact layer has a different conductivity than the third doped layer.

Abstract: An optical device. The optical device comprises a GaN substrate having a non-polar surface region, an n-type GaN cladding layer, an n-type SCH layer comprised of InGaN, a multiple quantum-well active region comprised of five InGaN quantum well layers separated by four InGaN barrier layers, a p-type guide layer comprised of GaN, an electron blocking layer comprised of AlGaN, a p-type GaN cladding layer, and a p-type GaN contact layer.

Abstract: The present invention discloses an LED structure, wherein an N-type current spreading layer is interposed between N-type semiconductor layers to uniformly distribute current flowing through the N-type semiconductor layer. The N-type current spreading layer includes at least three sub-layers stacked in a sequence of from a lower band gap to a higher band gap, wherein the sub-layer having the lower band gap is near the substrate, and the sub-layer having the higher band gap is near the light emitting layer. Each sub-layer of the N-type current spreading layer is expressed by a general formula InxAlyGa(1-x-y)N, wherein 0?x?1, 0?y?1, and 0?x+y?1.

Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.

Abstract: A light emitting diode is provided having a Group III nitride based superlattice and a Group III nitride based active region on the superlattice. The active region has at least one quantum well stricture. The quantum well structure includes a first Group III nitride based barrier layer, a Group III nitride based quantum well layer on the first barrier layer and a second Group III nitride based barrier layer. A Group III nitride based semiconductor device and methods of fabricating a Group III nitride based semiconductor device having an active region comprising at least one quantum well structure are provided. The quantum well structure includes a well support layer comprising a Group III nitride, a quantum well layer comprising a Group III nitride on the well support layer and a cap layer comprising a Group III nitride on the quantum well layer.

Abstract: A superlattice-based infrared absorber and the matching electron-blocking and hole-blocking unipolar barriers, absorbers and barriers with graded band gaps, high-performance infrared detectors, and methods of manufacturing such devices are provided herein. The infrared absorber material is made from a superlattice (periodic structure) where each period consists of two or more layers of InAs, InSb, InSbAs, or InGaAs. The layer widths and alloy compositions are chosen to yield the desired energy band gap, absorption strength, and strain balance for the particular application. Furthermore, the periodicity of the superlattice can be “chirped” (varied) to create a material with a graded or varying energy band gap.

Abstract: To provide an epitaxial substrate for electronic devices, in which current flows in a lateral direction, which enables accurate measurement of the sheet resistance of HEMTs without contact, and to provide a method of efficiently producing the epitaxial substrate for electronic devices, the method characteristically includes the steps of forming a barrier layer against impurity diffusion on one surface of a high-resistance Si-single crystal substrate, forming a buffer as an insulating layer on the other surface of the high-resistance Si-single crystal substrate, producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate, and measuring resistance of the main laminate of the epitaxial substrate without contact.

Abstract: An embodiment of the invention relates to a memory comprising a strained double-heterostructure having an inner semiconductor layer which is sandwiched between two outer semiconductor layers, wherein the lattice constant of the inner semiconductor layer differs from the lattice constants of the outer semiconductor layers, the resulting lattice strain in the double-heterostructure inducing the formation of at least one quantum dot inside the inner semiconductor layer, said at least one quantum dot being capable of storing charge carriers therein, and wherein, due to the lattice strain, the at least one quantum dot has an emission barrier of 1.15 eV or higher, and provides an energy state density of at least three energy states per 1000 nm3, all said at least three energy states being located in an energy band of 50 meV or less.

Abstract: A method for reduction of efficiency droop using an (Al, In, Ga)N/AlxIn1-xN superlattice electron blocking layer (SL-EBL) in nitride based light emitting diodes.

Abstract: Precision quantum dot clusters and methods for producing and tuning quantum dot clusters are described herein. Also described herein are materials and devices, including photovoltaic devices, that may include one or more quantum dot clusters.

Abstract: An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region. The insulation film is connected to an upper surface of the second channel region and an upper surface of the barrier region. The gate electrode faces the second channel region and the barrier region via the insulation film. The first channel region and the second channel region are arranged in series in a current pathway.

Abstract: A light emitting device may include a light emitting structure that includes a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the active layer includes a light emitting layer adjacent to the second semiconductor layer and that includes a well layer and a barrier layer and a super-lattice layer between the light emitting layer and the first semiconductor layer, the super-lattice layer including at least six pairs of a first layer and a second layer, wherein a composition of the first layer includes indium (In) and the second layer includes indium (In), and the composition of the first layer is different from the composition of the second layer.

Abstract: An ohmic contact to a semiconductor layer including a heterostructure barrier layer and a metal layer adjacent to the heterostructure barrier layer is provided. The heterostructure barrier layer can form a two dimensional free carrier gas for the contact at a heterointerface of the heterostructure barrier layer and the semiconductor layer. The metal layer is configured to form a contact with the two dimensional free carrier gas.

Abstract: An optoelectronic semiconductor chip is specified, which has an active zone (20) containing a multi quantum well structure provided for generating electromagnetic radiation, which comprises a plurality of successive quantum well layers (210, 220, 230). The multi quantum well structure comprises at least one first quantum well layer (210), which is n-conductively doped and which is arranged between two n-conductively doped barrier layers (250) adjoining the first quantum well layer. It comprises a second quantum well layer (220), which is undoped and is arranged between two barrier layers (250, 260) adjoining the second quantum well layer, of which one is n-conductively doped and the other is undoped. In addition, the multi quantum well structure comprises at least one third quantum well layer (230), which is undoped and which is arranged between two undoped barrier layers (260) adjoining the third quantum well layer.

Abstract: A GaN-based semiconductor light-emitting device includes (A) a first GaN-based compound semiconductor layer 13 having n-type conductivity, (B) an active layer 15 having a multi-quantum well structure including well layers and barrier layers for separating between the well layers, and (C) a second GaN-based compound semiconductor layer 17 having p-type conductivity. The well layers are disposed in the active layer 15 so as to satisfy the relation d1<d2 wherein d1 is the well layer density on the first GaN-based compound semiconductor layer side in the active layer and d2 is the well layer density on the second GaN-based compound semiconductor layer side.

Abstract: A semiconductor device includes at least one semiconductor layer, a metal layer in electrical contact with the semiconductor layer, and a carbon nanotube contact layer interposed between the metal layer and the semiconductor layer. The contact layer electrically couples the metal layer to the semiconductor layer and provides a semiconductor contact having low specific contact resistance. The contact layer can be substantially optically transparent layer in at least a portion of the visible light range.

Abstract: A high speed miniature tera- and gigahertz electromagnetic radiation on-chip spectrometer that comprises a tunable solid state 2D charge carrier layer or a quasi 2D charge carrier layer with incorporated single or multiple defects, at least first and second contacts to the charge carrier layer. Also the device includes an apparatus for measuring the device response between the first and second contacts, and an apparatus for a controllable tuning of at least one of the charge carrier layer parameters. The operation principle is based on the fact that radiation of different wavelengths excites distinct sets of plasma modes in the charge carrier layer.

Abstract: A light emitting diode (LED) for minimizing crystal defects in an active region and enhancing recombination efficiency of electrons and holes in the active region includes non-polar GaN-based semiconductor layers grown on a non-polar substrate. The semiconductor layers include a non-polar N-type semiconductor layer, a non-polar P-type semiconductor layer, and non-polar active region layers positioned between the N-type semiconductor layer and the P-type semiconductor layer. The non-polar active region layers include a well layer and a barrier layer with a superlattice structure.