Superlattice Patents (Class 257/15)
  • Publication number: 20120074385
    Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.
    Type: Application
    Filed: September 19, 2011
    Publication date: March 29, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-jo Tak, Jae-won Lee, Young-soo Park, Jun-youn Kim
  • Publication number: 20120068152
    Abstract: A graphene light-emitting device and a method of manufacturing the same are provided. The graphene light-emitting device includes a p-type graphene doped with a p-type dopant; an n-type graphene doped with an n-type dopant; and an active graphene that is disposed between the type graphene and the n-type graphene and emits light, wherein the p-type graphene, the n-type graphene, and the active graphene are horizontally disposed.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 22, 2012
    Applicant: SAMSUNG LED CO., LTD.
    Inventors: Sung-won HWANG, Geun-woo KO, Sung-hyun SIM, Hun-jae CHUNG, Han-kyu SEONG, Cheol-soo SONE, Jin-hyun LEE, Hyung-duk KO, Suk-ho CHOI, Sung KIM
  • Publication number: 20120068157
    Abstract: A transistor device having a graphene base for the transport of electrons into a collector is provided. The transistor consists of a heterostructure comprising an electron emitter, an electron collector, and a graphene material base layer consisting of one or more sheets of graphene situated between the emitter and the collector. The transistor also can further include an emitter transition layer at the emitter interface with the base and/or a collector transition layer at the base interface with the collector. The electrons injected into the graphene material base layer can be “hot electrons” having an energy E substantially greater than EF, the Fermi energy in the graphene material base layer or can be “non-hot electrons” having an energy E approximately equal to than EF. The electrons can have the properties of ballistic transit through the base layer.
    Type: Application
    Filed: September 21, 2011
    Publication date: March 22, 2012
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventor: Francis J. Kub
  • Patent number: 8138494
    Abstract: The present invention relates to a GaN series light-emitting diode structure, which includes a substrate; at least one GaN series layer formed over the substrate; subsequently an interface blocking structure composed of an n-type GaN series superlattice structure and a GaN series light-emitting layer, and a GaN series light-emitting layer are formed over the GaN series layer; and a p-type GaN series layer formed over the GaN series light-emitting layer. In the present invention, the radiative recombination efficiency is improved by introducing an interface blocking structure before the light-emitting layer under the epitaxial conditions of low temperature and pure nitrogen atmosphere.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: March 20, 2012
    Assignee: Chang Gung University
    Inventors: Ray-Ming Lin, Jhong-Hao Jiang, Bor-Ren Fang
  • Publication number: 20120061648
    Abstract: Disclosed is a method to construct a device that includes a plurality of nanowires (NWs) each having a core and at least one shell. The method includes providing a plurality of radially encoded NWs where each shell contains one of a plurality of different shell materials; and differentiating individual ones of the NWs from one another by selectively removing or not removing shell material within areas to be electrically coupled to individual ones of a plurality of mesowires (MWs). Also disclosed is a nanowire array that contains radially encoded NWs, and a computer program product useful in forming a nanowire array.
    Type: Application
    Filed: November 21, 2011
    Publication date: March 15, 2012
    Inventors: Andre DEHON, Charles M. Lieber, John E. Savage, Eric Rachlin
  • Patent number: 8129710
    Abstract: A nanowire light emitting diode (LED) and method of emitting light employ a plasmonic mode. The nanowire LED includes a nanowire having a semiconductor junction, a shell layer coaxially surrounding the nanowire, and an insulating layer, which is plasmonically thin, isolating the shell layer from the nanowire. The shell layer supports a surface plasmon that couples to the semiconductor junction by an evanescent field. Light is generated in a vicinity of the semiconductor junction and the surface plasmon is coupled to the semiconductor junction during light generation. The coupling enhances one or both of an efficiency of light emission and a light emission rate of the LED. A method of making the nanowire LED includes forming the nanowire, providing the insulating layer on the surface of the nanowire, and forming the shell layer on the insulating layer in the vicinity of the semiconductor junction.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: March 6, 2012
    Inventors: Hans Cho, David Fattal, Nathaniel Quitoriano
  • Patent number: 8124989
    Abstract: The present invention provides an optoelectronic device with an epi-stacked structure, which includes a substrate, a buffer layer that is formed on the substrate, in which the buffer layer includes a first nitrogen-containing compound layer, an II/V group compound layer is provided on the first nitrogen-containing compound layer, a second nitrogen-containing compound layer is provided on the II/V group compound layer, and a third nitrogen-containing compound layer is provided on the second nitrogen-containing compound layer, an epi-stacked structure with a multi-layer structure is formed on the buffer layer, which includes a first semiconductor conductive layer is formed on the buffer layer, an active layer is formed on the first semiconductor conductive layer, a multi-layer structure is formed between the first semiconductor conductive layer and the active layer, and a second semiconductor conductive layer is formed on the active layer.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: February 28, 2012
    Assignee: HUGA Optotech Inc.
    Inventor: Tzong-Liang Tsai
  • Patent number: 8124960
    Abstract: A nitride semiconductor light emitting diode (LED) is disclosed. The nitride semiconductor LED can include an active layer formed between an n-type nitride layer and a p-type nitride layer, where the active layer includes two or more quantum well layers and quantum barrier layers formed in alternation, and the quantum barrier layer formed adjacent to the p-type nitride layer is thinner than the remaining quantum barrier layers. An embodiment of the invention can be used to improve optical efficiency while providing crystallinity in the active layer.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: February 28, 2012
    Assignee: Samsung LED Co., Ltd.
    Inventors: Sang-Duk Yoo, Ho-Il Jung, Chul-Kyu Lee, Sung-Hwan Jang, Won-Shin Lee
  • Patent number: 8120008
    Abstract: A carbon nano-tube based photoelectric device includes a substrate and a carbon nanotube (CNT) over the substrate. The CNT comprises a first end and a second end, wherein the CNT has a CNT work function. A high work-function electrode over the substrate is in electric contact with the first end of the CNT. The high work-function electrode has a first work function higher than the CNT work function. A low work-function electrode over the substrate is in electric contact with the second end of the CNT. The low work-function electrode has a second work function lower than the CNT work function. The CNT can form a conductive channel between the high work-function electrode and the low work-function electrode. The carbon nano-tube based photoelectric device also includes a dielectric material is in contact with a side surface of the CNT and a conductive material in contact with the dielectric material.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: February 21, 2012
    Assignee: Peking University
    Inventors: Lianmao Peng, Xuelei Liang, Zhiyong Zhang, Sheng Wang, Qing Chen
  • Publication number: 20120039350
    Abstract: Semiconductor structures and laser devices including the semiconductor structures are provided. The semiconductor structures have a quantum cascade laser (QCL) structure including an electron injector, an active region, and an electron extractor. The active region of the semiconductor structures includes a configuration of quantum wells and barriers that virtually suppresses electron leakage, thereby providing laser devices including such structures with superior electro-optical characteristics.
    Type: Application
    Filed: August 12, 2010
    Publication date: February 16, 2012
    Applicant: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Dan Botez, Jae Cheol Shin
  • Publication number: 20120007048
    Abstract: A semiconductor structure includes a substrate and a conductive carrier-tunneling layer over and contacting the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm; and second III-nitride layers having a second bandgap lower than the first bandgap, wherein the first III-nitride layers and the second III-nitride layers are stacked in an alternating pattern. The semiconductor structure is free from a III-nitride layer between the substrate and the conductive carrier-tunneling layer. The semiconductor structure further includes an active layer over the conductive carrier-tunneling layer.
    Type: Application
    Filed: September 20, 2011
    Publication date: January 12, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Lin Yu, Ding-Yuan Chen, Chen-Hua Yu, Wen-Chih Chiou
  • Patent number: 8093583
    Abstract: A light emitting diode (LED) having a barrier layer with a superlattice structure is disclosed. In an LED having an active region between an GaN-based N-type compound semiconductor layer and a GaN-based P-type compound semiconductor layer, the active region comprises a well layer and a barrier layer with a superlattice structure. As the barrier layer with the superlattice structure is employed, it is possible to reduce occurrence of defects caused by lattice mismatch between the well layer and the barrier layer.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: January 10, 2012
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Sang Joon Lee, Duck Hwan Oh, Kyung Hae Kim, Chang Seok Han
  • Publication number: 20110315959
    Abstract: Optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit an array of conductive regions; and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a method of forming a nanocrystalline film includes fabricating a plurality of nanocrystals having a plurality of first ligands attached to their outer surfaces; exchanging the first ligands for second ligands of different chemical composition than the first ligands; forming a film of the ligand-exchanged nanocrystals; removing the second ligands; and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals.
    Type: Application
    Filed: September 7, 2011
    Publication date: December 29, 2011
    Applicant: InVisage Technologies, Inc.
    Inventors: Edward Sargent, Gerasimos Konstantatos, Larissa Levina, Ian Howard, Ethan J.D. Klem, Jason Clifford
  • Publication number: 20110309329
    Abstract: According to one embodiment, a nitride semiconductor device includes a substrate, an Alx1Ga1-x1N first buried layer, an InyAlzGa1-y-zN buried layer and an Alx2Ga1-x2N second buried layer. The substrate has protrusions formed in an in-plane direction on a first major surface, and a depression between adjacent ones of the protrusions. The first buried layer is formed on the depression and one of the protrusions. The InyAlzGa1-y-zN buried layer is formed on the first buried layer. The second buried layer is formed on the InyAlzGa1-y-zN buried layer. A portion of the first buried layer formed on the depression and a portion of the first buried layer formed on the one of the protrusions are not connected to each other. A portion of the InyAlzGa1-y-zN buried layer formed above the depression and a portion of the InyAlzGa1-y-zN buried layer formed above the one of the protrusions are connected to each other.
    Type: Application
    Filed: November 23, 2010
    Publication date: December 22, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hideto Sugawara
  • Patent number: 8080820
    Abstract: Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: December 20, 2011
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Mantu Hudalt, Been-Yih Jin, Benjamin Chu-Kung, Robert Chau
  • Patent number: 8080818
    Abstract: A light emitting device includes: a first layer made of a semiconductor of a first conductivity type; a second layer made of a semiconductor of a second conductivity type; an active layer including a multiple quantum well provided between the first layer and the second layer, impurity concentration of the first conductivity type in each barrier layer of the multiple quantum well having a generally flat distribution or increasing toward the second layer, average of the impurity concentration in the barrier layer on the second layer side as viewed from each well layer of the multiple quantum well being equal to or greater than average of the impurity concentration in the barrier layer on the first layer side, and average of the impurity concentration in the barrier layer nearest to the second layer being higher than average of the impurity concentration in the barrier layer nearest to the first layer.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: December 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akira Tanaka
  • Publication number: 20110284824
    Abstract: A light emitting diode structure and a method of forming a light emitting diode structure are provided. The structure comprises a superlattice comprising, a first barrier layer; a first quantum well layer comprising a first metal-nitride based material formed on the first barrier layer; a second barrier layer formed on the first quantum well layer; and a second quantum well layer comprising the first metal-nitride based material formed on the second barrier layer; and wherein a difference between conduction band energy of the first quantum well layer and conduction band energy of the second quantum well layer is matched to a single or multiple longitudinal optical phonon energy for reducing electron kinetic energy in the superlattice.
    Type: Application
    Filed: November 20, 2009
    Publication date: November 24, 2011
    Applicant: Agency for Science, Technology and Research
    Inventors: Wei Liu, Chew Beng Soh, Soo Jin Chua, Jing Hua Teng
  • Patent number: 8048703
    Abstract: A method of fabricating a light emitting device includes modulating a crystal growth parameter to grow a quantum well layer that is inhomogeneous and that has a non-random composition fluctuation across the quantum well layer.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: November 1, 2011
    Assignee: Palo Alto Research Center Incorporation
    Inventors: Christopher L. Chua, Zhihong Yang, John E. Northrup, Noble Marshall Johnson
  • Publication number: 20110253975
    Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).
    Type: Application
    Filed: June 17, 2011
    Publication date: October 20, 2011
    Inventors: Maxim S. Shatalov, Remigijus Gaska, Jinwei Yang, Michael Shur
  • Patent number: 8039830
    Abstract: A semiconductor light emitting device includes a first layer made of at least one of n-type GaN and n-type AlGaN; a second layer made of Mg-containing p-type AlGaN; and a light emitting section provided between the first layer and the second layer. The light emitting section included a plurality of barrier layers made of Si-containing AlxGa1-x-yInyN (0?x, 0?y, x+y?1), and a well layer provided between each pair of the plurality of barrier layers and made of GaInN or AlGaInN. The plurality of barrier layers have a nearest barrier layer and a far barrier layer. The nearest barrier layer is nearest to the second layer among the plurality of barrier layers. The nearest barrier layer includes a first portion and a second portion. The first portion is made of Si-containing AlxGa1-x-yInyN (0?x, 0?y, x+y?1). The second portion is provided between the first portion and the second layer and is made of AlxGa1-x-yInyN (0?x, 0?y, x+y?1).
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: October 18, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Kaneko, Yasuo Ohba, Hiroshi Katsuno, Mitsuhiro Kushibe
  • Publication number: 20110248241
    Abstract: A nitride semiconductor element includes: a strain suppression layer formed on a silicon substrate via an initial layer; and an operation layer formed on the strain suppression layer. The strain suppression layer includes a first spacer layer, a second spacer layer formed on and in contact with the first spacer layer, and a superlattice layer formed on and in contact with the second spacer layer. The first spacer layer is larger in lattice constant than the second spacer layer. The superlattice layer has first layers and second layers smaller in lattice constant than the first layers stacked alternately on top of one another. The average lattice constant of the superlattice layer is smaller than the lattice constant of the first spacer layer and larger than the lattice constant of the second spacer layer.
    Type: Application
    Filed: December 6, 2010
    Publication date: October 13, 2011
    Inventors: Jun Shimizu, Shinichi Kohda, Yasuhiro Yamada, Naohide Wakita, Masahiro Ishida
  • Publication number: 20110240962
    Abstract: An epitaxial substrate for an electronic device having a Si single crystal substrate, a buffer as an insulating layer formed on the Si single crystal substrate, and a main laminated body formed by plural group III nitride layers epitaxially grown on the buffer, wherein a lateral direction of the epitaxial substrate is defined as an electric current conducting direction. The buffer including at least an initially grown layer in contact with the Si single crystal substrate and a superlattice laminate constituted of a superlattice multilayer structure on the initially grown layer.
    Type: Application
    Filed: December 14, 2009
    Publication date: October 6, 2011
    Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Tetsuya Ikuta, Jo Shimizu, Tomohiko Shibata
  • Patent number: 8030640
    Abstract: A nitride semiconductor light emitting device includes a substrate, a first conductivity type nitride semiconductor layer disposed on the substrate and including a plurality of V-pits placed in a top surface thereof, a silicon compound formed in the vertex region of each of the V-pits, an active layer disposed on the first conductivity type nitride semiconductor layer and including depressions conforming to the shape of the plurality of V-pits, and a second conductivity type nitride semiconductor layer disposed on the active layer. The nitride semiconductor light emitting device, when receiving static electricity achieves high resistance to electrostatic discharge (ESD) since current is concentrated in the V-pits and the silicon compound placed on dislocations caused by lattice defects.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: October 4, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Jeong Tak Oh, Yong Chun Kim, Dong Joon Kim, Dong Ju Lee
  • Patent number: 8030110
    Abstract: A nitride semiconductor laser device uses a substrate with low defect density, contains reduced strains inside a nitride semiconductor film, and thus offers a satisfactorily long useful life. On a GaN substrate (10) with a defect density as low as 106 cm?2 or less, a stripe-shaped depressed portion (16) is formed by etching. On this substrate (10), a nitride semiconductor film (11) is grown, and a laser stripe (12) is formed off the area right above the depressed portion (16). With this structure, the laser stripe (12) is free from strains, and the semiconductor laser device offers a long useful life. Moreover, the nitride semiconductor film (11) develops reduced cracks, resulting in a greatly increased yield rate.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: October 4, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takeshi Kamikawa, Eiji Yamada, Masahiro Araki, Yoshika Kaneko
  • Publication number: 20110233519
    Abstract: Defect selective passivation in semiconductor fabrication for reducing defects.
    Type: Application
    Filed: March 23, 2010
    Publication date: September 29, 2011
    Applicant: ACADEMIA SINICA
    Inventors: Yuh-Jen Cheng, Ming-Hua Lo, Hao-chung Kuo
  • Patent number: 8026567
    Abstract: A thermoelectric structure for cooling an integrated circuit (IC) chip comprises a first type superlattice layer formed on top of the IC chip connected to a first voltage, and a second type superlattice layer formed on the bottom of the IC chip connected to a second voltage, the second voltage being different from the first voltage, wherein an power supply current flows through the first and second type superlattice layer for cooling the IC chip.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: September 27, 2011
    Assignee: Taiwan Semiconductor Manufactuirng Co., Ltd.
    Inventors: Shih-Cheng Chang, Hsin-Yu Pan
  • Publication number: 20110227034
    Abstract: Disclosed are a quantum dot-block copolymer hybrid, methods of fabricating and dispersing the same, a light emitting device including the same, and a fabrication method thereof. The quantum dot-block copolymer hybrid includes; a quantum dot, and a block copolymer surrounding the quantum dot, wherein the block copolymer has a functional group comprising sulfur (S) and forms a chemical bond with the quantum dot.
    Type: Application
    Filed: September 21, 2010
    Publication date: September 22, 2011
    Applicants: SAMSUNG ELECTRONICS CO., LTD., SNU R&DB FOUNDATION
    Inventors: Jong Hyuk KANG, Junghan SHIN, Jae Byung PARK, Dong-Hoon LEE, Kookheon CHAR, Seonghoon LEE, WanKi BAE, Jaehoon LIM
  • Patent number: 8022390
    Abstract: A photodetector for detecting infrared light in a wavelength range of 3-25 ?m is disclosed. The photodetector has a mesa structure formed from semiconductor layers which include a type-II superlattice formed of alternating layers of InAs and InxGa1-xSb with 0?x?0.5. Impurity doped regions are formed on sidewalls of the mesa structure to provide for a lateral conduction of photo-generated carriers which can provide an increased carrier mobility and a reduced surface recombination. An optional bias electrode can be used in the photodetector to control and vary a cut-off wavelength or a depletion width therein. The photodetector can be formed as a single-color or multi-color device, and can also be used to form a focal plane array which is compatible with conventional read-out integrated circuits.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: September 20, 2011
    Assignee: Sandia Corporation
    Inventors: Jin K. Kim, Malcolm S. Carroll
  • Patent number: 8013320
    Abstract: A nitride semiconductor device includes a semiconductor stacked structure which is formed of a nitride semiconductor having a first principal surface and a second principal surface opposed to the first principal surface and which includes an active layer. The first principal surface of the semiconductor stacked structure is formed with a plurality of indentations whose plane orientations are the {0001} plane, and the plane orientation of the second principal surface is the {1-101} plane. The active layer is formed along the {1-101} plane.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: September 6, 2011
    Assignee: Panasonic Corporation
    Inventors: Hisayoshi Matsuo, Tatsuo Morita, Tetsuzo Ueda, Daisuke Ueda
  • Patent number: 8008647
    Abstract: There is provided a nitride semiconductor device including an active layer of a superlattice structure. The nitride semiconductor device including: a p-type nitride semiconductor layer; an n-type nitride semiconductor layer; and an active layer disposed between the p-type and n-type nitride layers, the active layer comprising a plurality of quantum barrier layers and quantum well layers deposited alternately on each other, wherein the active layer has a superlattice structure where the quantum barrier layer has a thickness for enabling a carrier injected from the p-type and n-type nitride semiconductor layers to be tunneled therethrough, and at least one of the quantum barrier layers has an energy band gap greater than another quantum barrier layer adjacent to the n-type nitride semiconductor layer.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: August 30, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Seong Eun Park, Min Ho Kim, Jae Woong Han
  • Publication number: 20110204330
    Abstract: Nanostructures are joined using one or more of a variety of materials and approaches. As consistent with various example embodiments, two or more nanostructures are joined at a junction between the nanostructures. The nanostructures may touch or be nearly touching at the junction, and a joining material is deposited and nucleates at the junction to couple the nanostructures together. In various applications, the nucleated joining material facilitates conductivity (thermal and/or electric) between the nanostructures. In some embodiments, the joining material further enhances conductivity of the nanostructures themselves, such as by growing along the nanostructures and/or doping the nanostructures.
    Type: Application
    Filed: January 21, 2011
    Publication date: August 25, 2011
    Inventors: Melburne C. LeMieux, Ajay Virkar, Zhenan Bao
  • Publication number: 20110198569
    Abstract: A method for patterning nanostructures in a semiconductor heterostructure, which has at least a first layer and a second layer, wherein the first layer has a first surface and an opposite, second surface, the second layer has a first surface and an opposite, second surface, and the first layer is deposited over the second layer such that the second surface of the first layer is proximate to the first surface of the second layer. The method includes the steps of making indentations in a pattern on the first surface of the first layer of the semiconductor heterostructure; bonding the semiconductor heterostructure to a support substrate such that the first surface of the first layer of the semiconductor heterostructure is faced to the support substrate; etching off the second layer of the semiconductor heterostructure; and depositing a third layer over the second surface of the first layer of the semiconductor heterostructure.
    Type: Application
    Filed: March 6, 2009
    Publication date: August 18, 2011
    Applicant: BOARD OF TRUSTEES OF THE UNIVERSITY OF ARKANSAS
    Inventors: Ajay P. Malshe, Curtis R. Taylor, Gregory Salamo, Eric Stach, Robin Prince, Zhiming Wang
  • Publication number: 20110180783
    Abstract: A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed.
    Type: Application
    Filed: March 13, 2009
    Publication date: July 28, 2011
    Inventor: Pu-Xian Gao
  • Patent number: 7981710
    Abstract: A light emitting device of the invention includes an electron transporting layer, a hole transporting layer provided mutually facing the electron transporting layer with a distance between the hole transporting layer and the electron transporting layer, a phosphor layer having a layer of a plurality of semiconductor fine particles sandwiched between the electron transporting layer and the hole transporting layer, a first electrode provided facing the electron transporting layer and connected electrically, and a second electrode provided facing the hole transporting layer and connected electrically: in which the semiconductor fine particles composing the phosphor layer have a p-type part and an n-type part inside of the particles and have a pn-junction in the interface of the p-type part and the n-type part and are arranged in a manner that the p type part is partially brought into contact with the hole transporting layer and at the same time, the n type part is partially brought into contact with the electron
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: July 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Eiichi Satoh, Shogo Nasu, Reiko Taniguchi, Masayuki Ono, Masaru Odagiri
  • Publication number: 20110168978
    Abstract: Growth of thermoelectric materials in the form of quantum well superlattices on three-dimensionally structured substrates provide the means to achieve high conversion efficiency of the thermoelectric module combined with inexpensiveness of fabrication and compatibility with large scale production. Thermoelectric devices utilizing thermoelectric materials in the form of quantum well semiconductor superlattices grown on three-dimensionally structured substrates provide improved thermoelectric characteristics that can be used for power generation, cooling and other applications.
    Type: Application
    Filed: January 12, 2010
    Publication date: July 14, 2011
    Inventor: Vladimir Kochergin
  • Patent number: 7977665
    Abstract: A nitride-based light emitting device capable of achieving an enhancement in light emission efficiency and an enhancement in reliability is disclosed. The nitride-based light emitting device includes a light emitting layer including a quantum well layer and a quantum barrier layer, and a stress accommodating layer arranged on at least one surface of the quantum well layer of the light emitting layer.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: July 12, 2011
    Assignee: LG Electronics Inc. & LG Innotek Co., Ltd.
    Inventor: Yong Tae Moon
  • Patent number: 7977666
    Abstract: The present invention is disclosed that a device capable of normal incident detection of infrared light to efficiently convert infrared light into electric signals. The device includes a substrate, a first contact layer formed on the substrate, an active layer formed on the first contact layer, a barrier layer formed on the active layer and a second contact layer formed on the barrier layer, wherein the active layer includes multiple quantum dot layers.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: July 12, 2011
    Assignee: Academia Sinica
    Inventors: Shiang-Yu Wang, Hong-Shi Ling, Ming-Cheng Lo, Chien-Ping Lee
  • Publication number: 20110140083
    Abstract: A semiconductor device may include a doped semiconductor region having a modulated dopant concentration. The doped semiconductor region may be a silicon doped Group III nitride semiconductor region with a dopant concentration of silicon being modulated in the Group III nitride semiconductor region. In addition, a semiconductor active region may be configured to generate light responsive to an electrical signal therethrough. Related methods, devices, and structures are also discussed.
    Type: Application
    Filed: December 16, 2009
    Publication date: June 16, 2011
    Inventors: Daniel Carleton Driscoll, Ashonita Chavan, Adam William Saxler
  • Patent number: 7955881
    Abstract: In the method of fabricating a quantum well structure which includes a well layer and a barrier layer, the well layer is grown at a first temperature on a sapphire substrate. The well layer comprises a group III nitride semiconductor which contains indium as a constituent. An intermediate layer is grown on the InGaN well layer while monotonically increasing the sapphire substrate temperature from the first temperature. The group III nitride semiconductor of the intermediate layer has a band gap energy larger than the band gap energy of the InGaN well layer, and a thickness of the intermediate layer is greater than 1 nm and less than 3 nm in thickness. The barrier layer is grown on the intermediate layer at a second temperature higher than the first temperature. The barrier layer comprising a group III nitride semiconductor and the group III nitride semiconductor of the barrier layer has a band gap energy larger than the band gap energy of the well layer.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: June 7, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Akita, Takamichi Sumitomo, Yohei Enya, Takashi Kyono, Masaki Ueno
  • Publication number: 20110127489
    Abstract: Example embodiments relate to a light emitting device and a method of fabricating the light emitting device. The light emitting device may include an n-type clad layer including a plurality of nitride semiconductor layers, at least one interlayer disposed between the plurality of nitride semiconductor layers, a via hole in which a first electrode is formed, a p-type clad layer, and an active layer between the n-type clad layer and the p-type clad layer.
    Type: Application
    Filed: June 1, 2010
    Publication date: June 2, 2011
    Inventors: Jae-won Lee, Su-hee Chae, Jun-youn Kim, Young-jo Tak
  • Patent number: 7935956
    Abstract: A device having an optically active region includes a silicon substrate and a SiGe cladding layer epitaxially grown on the silicon substrate. The SiGe cladding layer includes a plurality of arrays of quantum dots separated by at least one SiGe spacing layer, the quantum dots being formed from a compound semiconductor material.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: May 3, 2011
    Assignee: The Regents of the University of California
    Inventor: Ya-Hong Xie
  • Publication number: 20110079768
    Abstract: The present invention provides photoactive materials that include quantum-confined semiconductor nanostructures in combination with non-quantum confined and bulk semiconductor structures to enhance or create a type II band offset structure. The photoactive materials are well-suited for use as the photoactive layer in photoactive devices, including photovoltaic devices, photoconductors and photodetectors.
    Type: Application
    Filed: December 10, 2010
    Publication date: April 7, 2011
    Inventors: Dmytro Poplavskyy, Sanjai Sinha, David Jurbergs, Homer Antoniadis
  • Patent number: 7920322
    Abstract: Provided are a reflective semiconductor optical amplifier (R-SOA) and a superluminescent diode (SLD). The R-SOA includes: a substrate; an optical waveguide including a lower clad layer, an active layer independent of the polarization of light, and an upper clad layer sequentially stacked on the substrate, the optical waveguide comprising linear, curved, and tapered waveguide areas; and a current blocking layer formed around the optical waveguide to block a flow of current out of the active layer, wherein the linear and curved waveguide areas have a single buried hetero (BH) structure, and the tapered waveguide area has a dual BH structure.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: April 5, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Su Hwan Oh, Sahnggi Park, Yongsoon Baek, Kwang-Ryong Oh
  • Patent number: 7915640
    Abstract: A metamorphic buffer layer is formed on a semi-insulating substrate by an epitaxial growth method, a collector layer, a base layer, an emitter layer and an emitter cap layer are sequentially laminated on the metamorphic buffer layer, and a collector electrode is provided in contact with an upper layer of the metamorphic buffer layer. The metamorphic buffer layer is doped with an impurity, in a concentration equivalent to or higher than that in a conventional sub-collector layer, by an impurity doping process during crystal growth so that the metamorphic buffer layer will be able to play the role of guiding the collector current to the collector electrode. Since the sub-collector layer, which is often formed of a ternary mixed crystal or the like having a high thermal resistance, can be omitted, the heat generated in the semiconductor device can be rapidly released into the substrate.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: March 29, 2011
    Assignee: Sony Corporation
    Inventor: Masaya Uemura
  • Publication number: 20110064101
    Abstract: A low voltage laser device having an active region configured for one or more selected wavelengths of light emissions.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 17, 2011
    Applicant: Kaai, Inc.
    Inventors: James W. Raring, Mathew Schmidt, Christiane Poblenz
  • Patent number: 7906775
    Abstract: Fabrication of metallic or non-metallic wires with nanometer widths and nanometer separation distances without the use of lithography. Wires are created in a two-step process involving forming the wires at the desired dimensions and transferring them to a planar substrate. The dimensions and separation of the wires are determined by the thicknesses of alternating layers of different materials that are in the form of a superlattice. Wires are created by evaporating the desired material onto the superlattice that has been selectively etched to provide height contrast between layers. The wires thus formed upon one set of superlattice layers are then transferred to a substrate.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: March 15, 2011
    Assignee: California Institute of Technology
    Inventors: James R. Heath, Pierre M. Petroff, Nicholas A. Melosh
  • Patent number: 7903708
    Abstract: A nitride semiconductor laser device uses a substrate with low defect density, contains reduced strains inside a nitride semiconductor film, and thus offers a satisfactorily long useful life. On a GaN substrate (10) with a defect density as low as 106 cm?2 or less, a stripe-shaped depressed portion (16) is formed by etching. On this substrate (10), a nitride semiconductor film (11) is grown, and a laser stripe (12) is formed off the area right above the depressed portion (16). With this structure, the laser stripe (12) is free from strains, and the semiconductor laser device offers a long useful life. Moreover, the nitride semiconductor film (11) develops reduced cracks, resulting in a greatly increased yield rate.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: March 8, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takeshi Kamikawa, Eiji Yamada, Masahiro Araki, Yoshika Kaneko
  • Patent number: 7902561
    Abstract: The present invention relates to a nitride semiconductor light emitting device including: a first nitride semiconductor layer having a super lattice structure of AlGaN/n-GaN or AlGaN/GaN/n-GaN; an active layer formed on the first nitride semiconductor layer to emit light; a second nitride semiconductor layer formed on the active layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. According to the present invention, the crystallinity of the active layer is enhanced, and optical power and reliability are also enhanced.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: March 8, 2011
    Assignee: LG Innotek Co., Ltd.
    Inventor: Suk Hun Lee
  • Patent number: 7903707
    Abstract: A nitride semiconductor light-emitting device wherein a substrate or nitride semiconductor layer has a defect concentration region and a low defect density region other than the defect concentration region. A portion including the defect concentration region of the nitride semiconductor layer or substrate has a trench region deeper than the low defect density region. Thus by digging the trench in the defect concentration region, the growth detection is uniformized, and the surface planarity is improved. The uniformity of the characteristic in the wafer surface leads to improvement of the yield.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: March 8, 2011
    Assignees: Sharp Kabushiki Kaisha, Sumitomo Electric Industries, Ltd.
    Inventors: Takeshi Kamikawa, Yoshika Kaneko, Kensaku Motoki
  • Patent number: 7884351
    Abstract: In a nitride semiconductor light-emitting device (11), an emission region (17) has a quantum well structure (19), and lies between an n-type gallium nitride semiconductor region (13) and a p-type gallium nitride semiconductor region (15). The quantum well structure (19) includes a plurality of first well layers (21) composed of InxGa1-xN, one or a plurality of second well layers (23) composed of InyGa1-yN, and barrier layers (25). The first and second well layers (21) and (23) are arranged in alternation with the barrier layers (25). The second well layers (23) lie between the first well layers (21) and the p-type gallium nitride semiconductor region (15). The indium component y of the second well layers (23) is smaller than indium component x of the first well layers (21), and the thickness DW2 of the second well layers (23) is greater than the thickness DW1 of the first well layers (21).
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: February 8, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Kyono, Katsushi Akita, Yusuke Yoshizumi