Variable Threshold (e.g., Floating Gate Memory Device) Patents (Class 257/314)
- With additional contacted control electrode (Class 257/316)
- With irregularities on electrode to facilitate charging or discharging of floating electrode (Class 257/317)
- Additional control electrode is doped region in semiconductor substrate (Class 257/318)
- Plural additional contacted control electrodes (Class 257/319)
- With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling (Class 257/321)
- With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction) (Class 257/322)
- With means to facilitate light erasure (Class 257/323)
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Patent number: 11411081Abstract: The disclosure provides a field effect transistor (FET) stack with methods to form the same. The FET stack includes a first transistor over a substrate. The first transistor includes a first active semiconductor material including a first channel region between a first set of source/drain terminals, and a first gate structure over the first channel region. The first gate structure includes a first gate insulator of a first thickness above the first channel region. A second transistor is over the substrate and horizontally separated from the first transistor. A second gate structure of the second transistor may include a second gate insulator of a second thickness above a second channel region, the second thickness being greater than the first thickness. A shared gate node may be coupled to each of the first gate structure and the second gate structure.Type: GrantFiled: April 22, 2020Date of Patent: August 9, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Steven M. Shank, Anthony K. Stamper, Vibhor Jain, John J. Ellis-Monaghan
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Patent number: 11404430Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate; a first conductor layer provided above the semiconductor substrate and including silicon; a plurality of second conductor layers provided above first conductor layer and stacked apart from each other in the first direction; and a first pillar extending in the first direction through the second conductor layers and including intersection portions where the first pillar intersects the second conductor layer, the intersection portions each functioning as a memory cell transistor, wherein the first conductor layer includes a first region which is in contact with the first pillar and includes at least one element of arsenic (As), phosphorus (P), carbon (C), or boron (B).Type: GrantFiled: September 9, 2019Date of Patent: August 2, 2022Assignee: Kioxia CorporationInventor: Ken Komiya
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Patent number: 11404570Abstract: A method includes providing a structure having a substrate, gate stacks and source/drain (S/D) features over the substrate, S/D contacts over the S/D features, one or more dielectric layers over the gate stacks and the S/D contacts, and a via structure penetrating the one or more dielectric layers and electrically connecting to one of the gate stacks and the S/D contacts. The method further includes forming a ferroelectric (FE) stack over the structure, wherein the FE stack includes an FE layer and a top electrode layer over the FE layer, wherein the FE stack directly contacts the via structure; and patterning the FE stack, resulting in a patterned FE stack including a patterned FE feature and a patterned top electrode over the patterned FE feature.Type: GrantFiled: July 27, 2020Date of Patent: August 2, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao Chang, Lin-Yu Huang, Han-Jong Chia, Bo-Feng Young, Yu-Ming Lin
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Patent number: 11404583Abstract: An apparatus comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, a first channel material extending vertically through the stack, and a second channel material adjacent the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure adjacent to each of the first channel material and the second channel material, and a conductive line structure adjacent to the conductive plug structure. Methods of forming the apparatus, memory devices, and electronic systems are also described.Type: GrantFiled: February 4, 2020Date of Patent: August 2, 2022Assignee: Micron Technology, Inc.Inventors: Akira Goda, Marc Aoulaiche
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Patent number: 11404441Abstract: In a method for manufacturing a memory device, a plurality of first insulating layers and a bottom select gate (BSG) layer are formed over a substrate, where the first insulating layers are disposed between the substrate and the BSG layer. One or more first dielectric trenches are formed to pass through the BSG layer and the first insulating layers, and extend in a length direction of the substrate. A plurality of word line layers and a plurality of second insulating layers are formed over the BSG layer, where the second insulating layers are disposed between the BSG layer and the word line layers. One or more common source regions are formed over the substrate to extend in the length direction of the substrate, and further extend through the BSG layer, the first insulating layers, the word line layers, and the second insulating layers.Type: GrantFiled: January 21, 2021Date of Patent: August 2, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yali Song, Li Hong Xiao, Ming Wang
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Patent number: 11404428Abstract: A semiconductor device includes: a stacked structure comprising a plurality of dielectric layers and a plurality of conductive layers, wherein the dielectric layers are alternately stacked with the conductive layers; a groove formed for each conductive layer by recessing the conductive layer to the inside of the stacked structure; and an isolation structure formed through the stacked structure so as to isolate the stacked structure into a first block and a second block. The isolation structure comprises a first isolation structure and a second isolation structure adjacent to the first isolation structure with a gap provided between the first and second isolation structures, and one end of the first isolation structure and the other end of the second isolation structure, which face each other, have a vortex shape when viewed from above.Type: GrantFiled: July 2, 2020Date of Patent: August 2, 2022Assignee: SK hynix Inc.Inventor: Dae Sung Eom
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Patent number: 11404438Abstract: A memory device includes a substrate; and a stack structure, including alternately arranged first dielectric layers and electrode layers. In a first lateral direction, the memory device includes array regions and a staircase region arranged between array regions. In a second lateral direction, the stack structure includes a first block and a second block, each including a wall-structure region and extending along the first lateral direction. The wall-structure regions of the first block and the second block are adjacent to each other and together form a wall structure in the staircase region. The memory device also includes a first separation structure, formed through the stack structure and positioned between the first block and the second block in array regions along the first lateral direction; and second dielectric layers positioned between the first block and the second block in the staircase region, and alternated with the first dielectric layers.Type: GrantFiled: September 4, 2020Date of Patent: August 2, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Kai Han, Yali Guo, Zhipeng Wu, Lu Zhang, Hang Yin, Simin Liu, Bo Xu
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Patent number: 11398490Abstract: This invention provides a three-dimensional junctionless neuron network device and a manufacturing method thereof. The device comprises: a substrate; and a stack structure is formed on the surface of the substrate, the stack structure comprises alternately stacked gate electrode layers and isolation layers and has a channel hole penetrating the substrate; a weighting gate layer is formed on the surface of the channel hole, and the weighting gate layer has a gap from the bottom of the channel hole; a gate dielectric layer is located on the weight gate between the layer and the gate electrode layer; a tunneling dielectric layer on the surface of the weighting gate layer; a channel layer filled in the channel hole, the channel layer being in contact with the substrate. The invention adopts a vertically stacked isolation layer and gate layer design. The stack structure has an array of channel holes.Type: GrantFiled: November 6, 2020Date of Patent: July 26, 2022Assignee: SiEn (QingDao) Integrated Circuits Co., LtdInventor: Deyuan Xiao
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Patent number: 11393909Abstract: A semiconductor device comprising a gate electrode on a substrate, a source/drain pattern on the substrate on a side of the gate electrode, and a gate contact plug on the gate electrode are disclosed. The gate contact plug may include a first gate contact segment, and a second gate contact segment that extends in a vertical direction from a top surface of the first gate contact segment. An upper width of the first gate contact segment may be greater than a lower width of the second gate contact segment.Type: GrantFiled: July 17, 2019Date of Patent: July 19, 2022Inventors: Doohyun Lee, Hyun-Seung Song, Yeongchang Roh, Heonjong Shin, Sora You, Yongsik Jeong
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Patent number: 11393847Abstract: To provide a semiconductor storage apparatus, a product-sum calculation apparatus, and electronic equipment in which memory cells are highly integrated and highly densified. A semiconductor storage apparatus including: a first transistor including a first gate electrode via a ferroelectric film on an activation region including source or drain regions; and a second transistor including source or drain regions in an activation layer provided on the first gate electrode and a second gate electrode on the activation layer via an insulating film.Type: GrantFiled: February 27, 2019Date of Patent: July 19, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Masanori Tsukamoto
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Patent number: 11387253Abstract: A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the conducType: GrantFiled: June 24, 2020Date of Patent: July 12, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sunggil Kim, Sungjin Kim, Seulye Kim, Junghwan Kim, Chanhyoung Kim
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Patent number: 11387142Abstract: A semiconductor structure includes a semiconductor device, bit lines electrically connected to the semiconductor device, air gaps located between the bit lines, a capping-level material layer, a via-level dielectric material layer located between the bit lines and the capping-level material layer, and conductive via structures extending through the via-level dielectric material layer and contacting a top surface of a respective one of the bit lines. The capping-level material layer contains cavity-containing openings exposing the air gaps. The capping-level material layer contains protruding portions that extend into peripheral regions of the cavity-containing openings.Type: GrantFiled: March 22, 2021Date of Patent: July 12, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Koichi Matsuno, Masaaki Higashitani, Johann Alsmeier
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Patent number: 11380709Abstract: A memory element is provided that includes a portion of a bit line plug, a portion of a source line plug, a portion of a word line, a portion of a vertical semiconductor pillar disposed between the bit line plug, the source line plug and adjacent the word line, and a gate oxide including a ferroelectric material disposed between the vertical semiconductor pillar and the word line.Type: GrantFiled: September 3, 2019Date of Patent: July 5, 2022Assignee: SanDisk Technologies LLCInventors: Yingda Dong, James Kai, Christopher J. Petti
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Patent number: 11374015Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.Type: GrantFiled: July 30, 2020Date of Patent: June 28, 2022Assignee: Kioxia CorporationInventors: Wataru Sakamoto, Ryota Suzuki, Tatsuya Okamoto, Tatsuya Kato, Fumitaka Arai
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Patent number: 11362196Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.Type: GrantFiled: April 7, 2020Date of Patent: June 14, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hongsik Shin, Hyunjoon Roh, Heungsik Park, Sughyun Sung, Dohaing Lee, Wonhyuk Lee
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Patent number: 11362105Abstract: A vertical memory device includes gate electrode structures, channels, first to third division patterns, and a first support layer. The gate electrode structure includes gate electrodes stacked in a first direction, and extends in a second direction. The gate electrode structures are spaced apart from one another in a third direction. The first division pattern extends in the second direction between the gate electrode structures. The second and third division patterns are alternately disposed in the second direction between the gate electrode structures. The first support layer is on the gate electrode structures at substantially the same height as upper portions of the first and second division patterns, and contacts the upper portions of the first and second division patterns. The upper portions of the first and second division patterns are arranged in a zigzag pattern in the second direction in a plan view.Type: GrantFiled: June 16, 2020Date of Patent: June 14, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seungmin Song, Kangmin Kim, Joongshik Shin, Geunwon Lim
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Patent number: 11355632Abstract: A semiconductor structure includes a substrate having a top surface, pillar structures formed on top of the substrate, a gate conductor, a drain/source region and a source/drain region. Each pillar structure of the pillar structures includes a first end and a second end, and the first end is closer to the substrate than the second end. The gate conductor surrounds each of the pillar structures disposed between the first end and the second end. The drain/source region is at the top surface of the substrate and in contact with the first end of a first pillar structure of the pillar structures, and the source/drain region is at the top surface of the substrate and in contact with the first end of a second pillar structure of the pillar structures.Type: GrantFiled: July 29, 2019Date of Patent: June 7, 2022Assignee: Avago Technologies International Sales Pte. LimitedInventor: Qing Liu
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Patent number: 11355515Abstract: Fabricating a three-dimensional memory device may include forming an alternating stack of insulating layers and sacrificial material layers over a substrate. Stepped surfaces are formed by patterning the alternating stack. Sacrificial pads are formed on physically exposed horizontal surfaces of the sacrificial material layers. A retro-stepped dielectric material portion is formed over the sacrificial pads. After memory stack structures extending through the alternating stack are formed, the sacrificial material layers and the sacrificial pads can be replaced with replacement material portions that include electrically conductive layers. The electrically conductive layers can be formed with thicker end portions. Contact via structures can be formed on the thicker end portions.Type: GrantFiled: May 21, 2020Date of Patent: June 7, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Naoto Hojo, Takahiro Tabira, Yoshitaka Otsu
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Patent number: 11342430Abstract: A semiconductor device has a split-gate type MONOS structure using a FinFET, and it includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel forming layer which is formed under a control gate and is formed of a semiconductor layer doped with a p-type impurity, and a second channel forming layer which is formed under a memory gate and is formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate.Type: GrantFiled: October 29, 2020Date of Patent: May 24, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Digh Hisamoto, Yoshiyuki Kawashima, Takashi Hashimoto
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Patent number: 11342264Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate, where the connection region is arranged between the first and second array regions. A second staircase is formed in the connection region of the stack over the substrate, and the connection region in the stack includes a separation region between the first and second staircases.Type: GrantFiled: April 21, 2020Date of Patent: May 24, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhongwang Sun, Zhong Zhang, Wenxi Zhou, Zhiliang Xia
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Patent number: 11342342Abstract: A semiconductor device may include a source layer, a stack structure, a channel layer, a slit, and a source pick-up line. The source layer may include at least one groove in an upper surface thereof. The stack structure may be formed over the source layer. The channel layer may pass through the stack structure. The channel layer may be in contact with the source layer. The slit may pass through the stack structure. The slit may expose the groove of the source layer therethrough. The source pick-up line may be formed in the slit and the groove. The source pick-up line may be contacted with the source layer.Type: GrantFiled: September 30, 2019Date of Patent: May 24, 2022Assignee: SK hynix inc.Inventor: Ki Hong Lee
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Patent number: 11322512Abstract: A semiconductor device including a stacked body that includes insulating layers and conductive layers that are alternately stacked, a first film provided inside a recess portion that penetrates through the stacked body, a second film provided on a surface of the first film, a third film provided on a surface of the second film, and a fourth film provided on a surface of the third film. An average concentration of a halogen element per unit area in the third film and the fourth film is lower than an average concentration of the halogen element per unit area at an interface between the third film and the fourth film.Type: GrantFiled: March 1, 2019Date of Patent: May 3, 2022Assignee: KIOXIA CORPORATIONInventor: Shuto Yamasaka
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Patent number: 11322509Abstract: A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.Type: GrantFiled: August 24, 2020Date of Patent: May 3, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Ashish Baraskar, Raghuveer S. Makala, Peter Rabkin
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Patent number: 11322623Abstract: A non-volatile memory structure includes a substrate, a tunnel dielectric layer on the substrate, and several separate gate structures on the substrate. The gate structures are disposed within an array region of the substrate. Each gate structure includes a floating gate and a control gate on the floating gate. A first dielectric layer is formed above the substrate and covers the top surface of the tunnel dielectric layer. The first dielectric layer also covers the side surfaces and the top surface of each gate structure. Gaps between portions of the first dielectric layer on the side surfaces of two adjacent gate structures are fully filled with the air to form air gaps. Several insulating blocks are formed on the first dielectric layer, and they correspond to the gate structures. A second dielectric layer is formed on the insulating blocks and covers the insulating blocks and the air gaps.Type: GrantFiled: September 29, 2020Date of Patent: May 3, 2022Assignee: WINBOND ELECTRONICS CORP.Inventors: Ping-Lung Yu, Po-Chun Shao
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Patent number: 11315942Abstract: The present disclosure provides a SONOS memory structure and a manufacturing method therefor. The SONOS memory structure including a substrate and a select transistor gate and a memory transistor gate formed on the substrate, wherein the substrate is a composite substrate including a base silicon layer, a buried oxide layer and a surface silicon layer, wherein the upper portion of the base silicon layer has a memory transistor well region formed therein; the select transistor gate and the memory transistor gate are formed on the surface silicon layer; the select transistor gate comprises a first select transistor gate and a second select transistor gate, the first select transistor gate and the second select transistor gate are respectively located at two sides of the memory transistor gate, and are electrically isolated from the memory transistor gate by first spacers on both sides of the memory transistor gate.Type: GrantFiled: October 29, 2019Date of Patent: April 26, 2022Assignee: Shanghai Huali Integrated Circuit Mfg. Co. Ltd.Inventors: Xiaoliang Tang, Guanglong Chen, Naoki Tsuji, Hua Shao
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Patent number: 11309322Abstract: A semiconductor memory device according to an embodiment includes a semiconductor substrate; a laminated body formed by laminating a plurality of electrode layers on the semiconductor substrate; a memory film provided in the laminated body and including a first block insulation film disposed in a direction perpendicular to the electrode layer, a charge storage film facing the first block insulation film, a tunnel insulation film facing the charge storage film, and a channel film facing the tunnel insulation film; and a barrier layer provided at at least one of interface between the plurality of electrode layers and the memory film and an interface in the memory film and mainly composed of carbon.Type: GrantFiled: September 12, 2019Date of Patent: April 19, 2022Assignee: KIOXIA CORPORATIONInventors: Ryota Fujitsuka, Kenta Yamada, Takanori Yamanaka, Takayuki Okada, Hirokazu Ishigaki, Hiroki Kishi, Nobushi Matsuura, Takashi Yamane, Ryota Suzuki
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Patent number: 11309321Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.Type: GrantFiled: November 30, 2020Date of Patent: April 19, 2022Assignee: Micron Technology, Inc.Inventors: Haitao Liu, Chandra Mouli, Sergei Koveshnikov, Dimitrios Pavlopoulos, Guangyu Huang
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Patent number: 11296094Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.Type: GrantFiled: December 23, 2019Date of Patent: April 5, 2022Assignee: Micron Technology, Inc.Inventors: Kamal M. Karda, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Haitao Liu
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Patent number: 11296117Abstract: The disclosed technology relates generally to semiconductor memory devices, and more particularly to three-dimensional (3D) ferroelectric memory devices, methods of fabricating 3D ferroelectric memory devices, and methods of conditioning 3D ferroelectric memory devices. The 3D ferroelectric memory device exploits programmed memory cells as selector devices. In one aspect, a 3D ferroelectric memory device comprises a stack comprising a plurality of gate electrode layers and spacer layers, which are alternatingly arranged. The 3D ferroelectric memory device additionally comprises a semiconductor channel extending through the stack and a ferroelectric layer arranged between the gate electrode layers and the semiconductor channel. The gate electrode layers form, in combination with the channel and the ferroelectric layer, a string of ferroelectric transistors, wherein each ferroelectric transistor is associated with one cell of the memory device.Type: GrantFiled: December 4, 2020Date of Patent: April 5, 2022Assignee: IMEC vzwInventor: Jan Van Houdt
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Patent number: 11296028Abstract: A structure, such as a semiconductor device, includes metal line structures located over a substrate and laterally spaced apart from each other. Each of the metal line structures includes planar metallic liner including a first metal element and a metal line body portion includes a second metal element that is different from the first metal element. Metal-organic framework (MOF) material portions are located between neighboring pairs of the metal line structures and contain metal ions or clusters of the first metal element and organic ligands connected to the metal ions or clusters of the first metal element. Air gaps may be formed in the MOF material portions to further reduce the effective dielectric constant.Type: GrantFiled: December 20, 2019Date of Patent: April 5, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Ramy Nashed Bassely Said, Senaka Kanakamedala, Fei Zhou, Raghuveer S. Makala, Yao-Sheng Lee
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Patent number: 11289416Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.Type: GrantFiled: November 26, 2019Date of Patent: March 29, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Masanori Tsutsumi, Naohiro Hosoda, Shuichi Hamaguchi, Kazuki Isozumi, Genta Mizuno, Yusuke Mukae, Ryo Nakamura, Yu Ueda
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Patent number: 11289647Abstract: A memory cell includes: a first electrode; a resistive material layer comprising one horizontal portion and two vertical portions that are respectively coupled to ends of the horizontal portion; and a second electrode, wherein the second electrode is partially surrounded by a top boundary of the U-shaped profile and the first electrode extends along part of a bottom boundary of the U-shaped profile.Type: GrantFiled: October 19, 2017Date of Patent: March 29, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Chieh Mo, Shih-Chi Kuo
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Patent number: 11282846Abstract: Various embodiments of the present application are directed to a method for forming an integrated circuit (IC), and the associated integrated circuit. In some embodiments, a substrate is provided including a logic region having a plurality of logic sub-regions including a low-voltage logic sub-region and a high-voltage logic sub-region. The method further comprises forming a stack of gate dielectric precursor layers on the plurality of logic sub-regions and removing the stack of gate dielectric precursor layers from the low-voltage logic sub-region and the high-voltage logic sub-region. The method further comprises forming a high-voltage gate dielectric precursor layer on the low-voltage logic sub-region and the high-voltage logic sub-region and removing the high-voltage gate dielectric precursor layer from the low-voltage logic sub-region. The low-voltage logic sub-region has a logic device configured to operate at a voltage smaller than that of another logic device of the high-voltage logic sub-region.Type: GrantFiled: June 4, 2019Date of Patent: March 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Feng Teng, Wei Cheng Wu
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Patent number: 11264452Abstract: A transistor device includes a channel, a first source/drain region positioned on a first side of the channel, a second source/drain region positioned on a second side of the channel opposite the first side of the channel, and a tunnel barrier disposed between the channel and the first source/drain region, the tunnel barrier adapted to suppress band-to-band tunneling while the transistor device is in an off state.Type: GrantFiled: December 29, 2015Date of Patent: March 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Aryan Afzalian
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Patent number: 11256605Abstract: A nonvolatile memory device includes a memory cell region including first metal pads, and a peripheral circuit region. The peripheral circuit region includes second metal pads, a signal storage circuit that stores control signals and a data signal received from external of the nonvolatile memory device, a debugging information generator that generates debugging information based on the stored control signals and the stored data signal, and a debugging information register that outputs the debugging information in response to a debugging information external of the nonvolatile memory device. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads.Type: GrantFiled: August 12, 2020Date of Patent: February 22, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-Kil Jung, Hyunggon Kim, Donghoon Jeong, Myung-Hoon Choi
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Patent number: 11251201Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.Type: GrantFiled: October 16, 2020Date of Patent: February 15, 2022Assignee: Intel CorporationInventors: Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti
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Patent number: 11251191Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, where each of the memory stack structures contains a respective memory film and a respective vertical semiconductor channel, drain regions contacting an upper end of a respective one of the vertical semiconductor channels, first contact via structures directly contacting a first subset of the drain regions and each having a first horizontal cross-sectional area, and second contact via structures directly contacting a second subset of the drain regions and each having a second horizontal cross-sectional area that is greater than the first horizontal cross-sectional area.Type: GrantFiled: December 24, 2018Date of Patent: February 15, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Lishan Weng, Fumiaki Toyama, Mohan Dunga
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Patent number: 11244725Abstract: Various embodiments include methods and apparatuses, such as memory cells formed on two or more stacked decks. A method includes forming a first deck with first levels of conductor material and first levels of dielectric material over a substrate. Each level of the conductor material is separated from an adjacent level of conductor material by at least one of the first levels of dielectric material. A first opening is formed through the first levels of conductor material and dielectric material. A sacrificial material is formed at least partially filling the first opening. A second deck is formed over the first deck. The second deck has second levels of conductor material and second levels of dielectric material with each level of the conductor material being separated from an adjacent level of conductor material by at least one of the second levels of dielectric material. Additional apparatuses and methods are disclosed.Type: GrantFiled: December 9, 2019Date of Patent: February 8, 2022Assignee: Micron Technology, Inc.Inventors: Akira Goda, Roger W. Lindsay
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Patent number: 11244942Abstract: An apparatus comprises an antifuse cell comprising first and second nodes, an antifuse element, and a transistor. The antifuse element and the transistor are coupled in series between the first and second nodes. The antifuse element comprises an antifuse gate. The transistor comprises a transistor gate comprising a substantially-annular structure substantially surrounding the antifuse gate.Type: GrantFiled: May 8, 2019Date of Patent: February 8, 2022Assignee: Micron Technology, Inc.Inventors: Toshinao Ishii, Yasuhiko Tanuma
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Patent number: 11233063Abstract: A semiconductor device, and method of manufacturing a semiconductor device, includes second conductive patterns separated from each other above a first stack structure which is penetrated by first channel structures and enclosing second channel structures coupled to the first channel structures, respectively. Each of the second conductive patterns includes electrode portions stacked in a first direction and at least one connecting portion extending in the first direction to be coupled to the electrode portions.Type: GrantFiled: April 17, 2019Date of Patent: January 25, 2022Assignee: SK hynix Inc.Inventors: Young Geun Jang, Wan Sup Shin, Ki Hong Lee, Jae Jung Lee
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Patent number: 11227934Abstract: According to one embodiment, a semiconductor device includes a substrate, a plurality of insulating films and a plurality of electrode films provided alternately on the substrate. The semiconductor device further includes a first insulating film, a first charge storage film, a third insulating film, a second charge storage film, a second insulating film, and a first semiconductor film that are sequentially provided along at least one side surface of each of the electrode films. The first charge storage film includes either (i) molybdenum, or (ii) titanium and nitrogen, and the second charge storage film includes a semiconductor film.Type: GrantFiled: March 2, 2020Date of Patent: January 18, 2022Assignee: KIOXIA CORPORATIONInventors: Mitsuo Ikeda, Daisuke Ikeno, Akihiro Kajita
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Patent number: 11222965Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.Type: GrantFiled: December 24, 2019Date of Patent: January 11, 2022Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTDInventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam G Geha
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Patent number: 11222920Abstract: A magnetic device includes a first electrode, a second electrode, a plurality of magnetic junctions each containing a ferromagnetic reference layer and a ferromagnetic free layer located between the first electrode and the second electrode, and a plurality of magnetoelectric multiferroic portions having different structural defect densities located between the first electrode and the second electrode. Each of the plurality of magnetoelectric multiferroic portions is magnetically coupled to the ferromagnetic free layer of a respective one of the plurality of magnetic junctions.Type: GrantFiled: February 4, 2020Date of Patent: January 11, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Bhagwati Prasad, Alan Kalitsov
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Patent number: 11222842Abstract: A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.Type: GrantFiled: July 27, 2018Date of Patent: January 11, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Wen Chang, Yi-Hsiung Lin
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Patent number: 11217601Abstract: A microelectronic device comprises a stack structure, at least one staircase structure, contact structures, and support structures. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures. The at least one staircase structure is within the stack structure and has steps comprising edges of at least some of the tiers. The contact structures are on the steps of the at least one staircase structure. The support structures horizontally alternate with the contact structures in a first horizontal direction and vertically extend through the stack structure. The support structures have oblong horizontal cross-sectional shapes. Additional microelectronic devices, memory devices, and electronic systems are also described.Type: GrantFiled: October 29, 2019Date of Patent: January 4, 2022Assignee: Micron Technology, Inc.Inventors: Shuangqiang Luo, Xuan Li, Adeline Yii
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Patent number: 11211402Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.Type: GrantFiled: January 23, 2020Date of Patent: December 28, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kohji Kanamori, Seo-Goo Kang, Younghwan Son, Kwonsoon Jo
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Patent number: 11211400Abstract: A 3D flash memory device includes a substrate having a substantial planar surface. A plurality of active columns of semiconducting material is disposed above the substrate. Each of the plurality of active columns extends along a first direction orthogonal to the planar surface of the substrate. The plurality of active columns is arranged in a two-dimensional array. Each of the plurality of active columns may comprise multiple local bit lines and multiple local source lines extending along the first direction. Multiple channel regions are disposed between the multiple local bit lines and multiple local source lines. A word line stack wraps around the plurality of active columns. A charge-storage element is disposed between the word line stack and each of the plurality of active columns.Type: GrantFiled: November 29, 2019Date of Patent: December 28, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Min She, Qiang Tang
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Patent number: 11201170Abstract: A semiconductor device includes conductive patterns stacked and spaced apart from each other in a first direction to form a stepped structure, a stepped insulating layer overlapping the stepped structure, contact plugs extending through the stepped insulating layer in the first direction to contact respective contact portions of the conductive patterns, and barrier patterns disposed on sidewalls of the stepped insulating layer.Type: GrantFiled: September 24, 2020Date of Patent: December 14, 2021Assignee: SK hynix Inc.Inventor: Dae Sung Eom
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Patent number: 11183507Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.Type: GrantFiled: August 22, 2017Date of Patent: November 23, 2021Assignee: Toshiba Memory CorporationInventors: Katsuyuki Sekine, Tatsuya Kato, Fumitaka Arai, Toshiyuki Iwamoto, Yuta Watanabe, Wataru Sakamoto, Hiroshi Itokawa, Akio Kaneko
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Patent number: 11177202Abstract: A multilayer structure includes a substrate and a plurality of sub-stacks extending along a first direction respectively and disposed on an upper surface of the substrate along a second direction. Each of the sub-stacks includes insulating layers and patterned sacrificial layers alternately stacked on the upper surface along a third direction; conductive layers alternately stacked on the upper surface with the insulating layers along the third direction; and interlayer connectors extending along the third direction; wherein the patterned sacrificial layers have first sides and second sides opposite to the first sides, the conductive layers include first side conductive layers corresponding to the first sides and second side conductive layers corresponding to the second sides; wherein the interlayer connectors are electrically connected and directly contact corresponding ones of the conductive layers, and the first direction, the second direction, and the third direction are crossed.Type: GrantFiled: November 12, 2019Date of Patent: November 16, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventor: Shih-Hung Chen