Abstract: A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes.

Abstract: A monolithic three dimensional NAND string includes a semiconductor channel located over a substrate, a plurality of control gates extending substantially parallel to the major surface of the substrate including a first control gate located in a first device level and a second control gate located in a second device level located over the substrate and below the first device level, a charge storage material including a silicide layer located in the first device level and in the second device level, a blocking dielectric located between the charge storage material and the plurality of control gates, and a tunnel dielectric located between the charge storage material and the semiconductor channel. The tunnel dielectric has a straight sidewall, portions of the blocking dielectric have a clam shape, and each of the plurality of control gates is located at least partially in an opening in the clam-shaped portion of the blocking dielectric.

Abstract: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately formed on a surface portion of the substrate, buried insulating films formed in portions of the substrate that lie under the source and drain regions and each having a dielectric constant smaller than that of the substrate, a tunnel insulating film formed on a channel region formed between the source and drain regions, a charge storage layer formed of a dielectric body on the tunnel insulating film, a block insulating film formed on the charge storage layer, and a control gate electrode formed on the block insulating film.

Abstract: A process for fabricating a transistor may include forming source and drain regions in a substrate, and forming a floating gate having electrically conductive nanoparticles able to accumulate electrical charge. The process may include deoxidizing part of the floating gate located on the source side, and oxidizing the space resulting from the prior deoxidation so as to form an insulating layer on the source side.

Abstract: An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.

Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a plurality of charge storage layers each including a lower portion and an upper portion provided on the lower portion and having a smaller width than the lower portion, and a plurality of sacrificial films provided between the upper portions of adjacent ones of the charge storage layers. The sacrificial films are projected higher than the upper portions and spaced by first gaps from sidewalls of the upper portions. The method includes forming a plurality of intermediate insulating films on the upper portions and in the first gaps. The method includes removing the sacrificial films and forming second gaps between adjacent ones of the intermediate insulating films. The method includes forming a control electrode on the intermediate insulating films and in the second gaps.

Abstract: A nonvolatile memory device includes a multi-finger type control gate formed over a substrate, a multi-finger type floating gate formed over the substrate and disposed close to the control gate with gaps defined therebetween, and spacers formed on sidewalls of the control gate and the floating gate, and filling the gaps.

Abstract: Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures may be grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures may include at least one of nanocrystals, nanowires, or nanotubes. According to various nanocrystal embodiments, the nanocrystals can be positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein.

Abstract: This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height.

Abstract: A floating gate forming process includes the following steps. A substrate containing active areas isolated from each other by isolation structures protruding from the substrate is provided. A first conductive material is formed to conformally cover the active areas and the isolation structure. An etch back process is performed on the first conductive material to respectively form floating gates separated from each other in the active areas.

Abstract: A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer.

Abstract: The present invention discloses a discrete three-dimensional memory (3D-M). It is partitioned into at least two discrete dice: a memory-array die and a peripheral-circuit die. The memory-array die comprises at least a 3D-M array, which is built in a 3-D space. The peripheral-circuit die comprises at least a peripheral-circuit component, which is built on a 2-D plane. At least one peripheral-circuit component of the 3D-M is formed in the peripheral-circuit die instead of in the memory-array die. The array efficiency of the memory-array die can be larger than 70%.

Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.

Abstract: A nonvolatile memory structure includes a substrate having thereon a first, a second, and a third OD regions arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second the third OD region. A first select transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the first select transistor. The floating gate transistor includes a floating gate completely overlapped with the second OD region and is partially overlapped with the first and second intervening isolation regions. A second select transistor is on the third OD region and serially coupled to the floating gate transistor.

Abstract: A semiconductor memory device which includes a memory cell including two or more sub memory cells is provided. The sub memory cells each including a word line, a bit line, a first capacitor, a second capacitor, and a transistor. In the semiconductor device, the sub memory cells are stacked in the memory cell; a first gate and a second gate are formed with a semiconductor film provided therebetween in the transistor; the first gate and the second gate are connected to the word line; one of a source and a drain of the transistor is connected to the bit line; the other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor; and the first gate and the second gate of the transistor in each sub memory cell overlap with each other and are connected to each other.

Abstract: A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.

Abstract: Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.

Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.

Abstract: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction.

Abstract: According to one embodiment, a semiconductor storage device includes a first insulating film formed on a substrate and functioning as a FN (Fowler-Nordheim) tunnel film, a first floating gate formed on the first insulating film, an inter-floating-gate insulating layer formed on the first floating gate and functioning as a FN tunnel film, a second floating gate formed on the inter-floating-gate insulating layer, a second insulating film formed on the second floating gate, and a control gate formed on the second insulating film. The inter-floating-gate insulating layer includes a third insulating film and a fourth insulating film having a charge trap property which are stacked.

Abstract: The disclosed technology generally relates to memory devices, and more particularly to memory devices having an intergate dielectric stack comprising multiple high k dielectric materials. In one aspect, a planar non-volatile memory device comprises a hybrid floating gate structure separated from an inter-gate dielectric structure by a first interfacial layer which is designed to be electrically transparent so as not to affect the program saturation of the device. The inter-gate structure comprises a stack of three layers having a high-k/low-k/high-k configuration and the interfacial layer has a higher k-value than its adjacent high-k layer in the inter-gate dielectric structure. A method of making such a non-volatile memory device is also described.

Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

Abstract: The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.

Abstract: Nonvolatile memory devices including memory cell arrays with first bit line regions and common source tapping regions which are alternately disposed on a substrate along a direction, a page buffer including second bit line regions aligned with the first bit line regions and page buffer tapping regions aligned with the common source tapping regions, and a plurality of bit lines spaced apart from one another and extending to the second bit line regions from the first bit line regions.

Abstract: A method for forming a surrounding stacked gate fin FET nonvolatile memory structure includes providing a silicon-on-insulator (SOI) substrate of a first conductivity type, patterning a fin active region on a region of the substrate, forming a tunnel oxide layer on the fin active region, and depositing a first gate electrode of a second conductivity type on the tunnel oxide layer and upper surface of the substrate. The method further includes forming a dielectric composite layer on the first gate electrode, depositing a second gate electrode on the dielectric composite layer, patterning the first and second gate electrodes to define a surrounding stacked gate area, forming a spacer layer on a sidewall of the stacked gate electrode, and forming elevated source/drain regions in the fin active region on both sides of the second gate electrode.

Abstract: A semiconductor device includes two floating gates, a control gate and a first dielectric layer. The floating gates are disposed on a semiconductor substrate. The control gate partially overlaps each of the floating gates, and a part of the control gate is disposed between the two floating gates. Furthermore, the first dielectric layer disposed between the two floating gates and the control gate has a fixed thickness.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a foundation layer; and a stacked body provided on the foundation layer, each of a plurality of electrode layers and each of a plurality of insulating layers being stacked alternately in the stacked body; a select gate electrode provided on the stacked body; and a semiconductor layer extending from an upper end of the select gate electrode to a lower end of the stacked body. The stacked body includes a plurality of staircase regions. The each of the plurality of electrode layers includes an exposed portion. The exposed portion is not covered with the plurality of electrode layers other than the each of the plurality of electrode layers and the plurality of insulating layers. And the exposed portion of each of the plurality of electrode layers is disposed in one of the plurality of staircase regions.

Abstract: The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its read/write-voltage generator (VR/VW-generator) is located on a separate peripheral-circuit die. The VR/VW-generator generates at least a read and/or write voltage to the 3D-array die. A single VR/VW-generator die can support multiple 3D-array dies.

Abstract: A process for fabricating a gate structure, the gate structure having a plurality of gates defined by a network of spaces. The word line (WL) spaces within a dense WL region having airgaps and those spaces outside of the dense WL being substantially free of airgaps. A gate structure having a silicide layer dispose across the plurality of gates is also provided.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a memory array on a first substrate; and a peripheral circuit on a second substrate, wherein the first substrate and the second substrate may be attached to each other so that the memory array and the peripheral circuit are electrically connected to each other.

Abstract: A memory device may include a plurality of cell pairs each including insulator regions interposed between opposing sides of at least one common word line gate and first and second vertical sides formed by a spacing within at least one semiconductor material; and at least one selector gate vertically aligned with the word line gate within the spacing configured to enable first and second source regions in the first and second vertical sides, respectively; wherein when the selector gate is enabled, the first and second source regions are connected to different source diffusion regions.

Abstract: A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.

Abstract: A non-volatile memory including a substrate of a first conductivity type with first and second spaced apart regions formed therein of a second conductivity type with a channel region therebetween. A polysilicon metal gate word line is positioned over a first portion of the channel region and spaced apart therefrom by a high K dielectric layer. The metal portion of the word line is immediately adjacent to the high K dielectric layer. A polysilicon floating gate is immediately adjacent to and spaced apart from the word line, and positioned over and insulated from another portion of the channel region. A polysilicon coupling gate is positioned over and insulated from the floating gate. A polysilicon erase gate is positioned on another side of and insulated from the floating gate, positioned over and insulated from the second region, and immediately adjacent to but spaced apart from another side of the coupling gate.

Abstract: NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

Abstract: A memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate. Methods for building such a memory device are also disclosed.

Abstract: Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P? region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P? region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P? region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

Abstract: Methods and apparatus for non-volatile memory cells. A memory cell includes a floating gate formed over a substrate with a tunneling dielectric over an upper surface of the floating gate and an erase gate over the tunneling dielectric. Sidewall dielectrics enclose the tunneling dielectric. Assist gates and coupling gates are formed on either side of the memory cell and are spaced from the floating gate of the memory cell by the sidewall dielectrics. Methods for forming memory cells include depositing a floating gate over a dielectric layer over a semiconductor substrate, depositing a tunneling dielectric over the floating gate, depositing an erase gate over the tunneling dielectric, patterning the erase gate, tunneling dielectric and floating gate to form memory cells having vertical sides, and depositing sidewall dielectrics on the vertical sides of the memory cells to seal the tunneling dielectrics. Additional steps are performed to complete the cells.

Abstract: The technology of the present invention relates to a non-volatile memory device and a fabrication method thereof. The non-volatile memory device includes channel layers protruding vertically from a substrate, a plurality of hole-supply layers and a plurality of gate electrodes, which are alternately stacked along the channel layers, and a memory film interposed between the channel layers and the gate electrodes and between the hole-supply layers and the gate electrodes. According to this technology, the hole-supply layers are formed between the memory cells such that sufficient holes are supplied to the memory cells during the erase operation of the memory cells, whereby the erase operation of the memory cells is smoothly performed without using the GIDL current, and the properties of the device are protected from being deteriorated due to program/erase cycling.

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

Abstract: An embodiment of a nonvolatile-memory device includes: a body accommodating at least a first semiconductor well and a second semiconductor well; an insulating structure; and at least one nonvolatile memory cell. The cell includes: at least one first control region in the first well; conduction regions in the second well; and a floating gate region, which extends over portions of the first well and of the second well, is capacitively coupled to the first control region and forms a floating-gate memory transistor with the conduction regions. The insulating structure includes: first insulating regions, which separate the floating gate region from the first control region and from the second well outside the conduction regions and have a first thickness; and second insulating regions, which separate the floating gate region from the first well outside the first control region and have a second thickness greater than the first thickness.

Abstract: The present invention relates to a semiconductor device including nanodots and a capacitor. A semiconductor device includes a channel layer, a tunnel insulating layer formed on the channel layer, a memory layer formed on the tunnel insulating layer and including first nanodots, a charge blocking layer formed on the memory layer, a gate electrode conductive layer formed on the charge blocking layer, and a buffer layer located, at least one of, inside the tunnel insulating layer, inside the charge blocking layer, at an interface between the tunnel insulating layer and the memory layer and at the interface between the charge blocking layer and the memory layer, wherein the buffer layer includes second nanodots.

Abstract: A NAND flash memory chip is formed by depositing two N-type polysilicon layers. The upper N-type polysilicon layer is then replaced with P-type polysilicon and barrier layer in the array area only, while maintaining the upper N-type polysilicon layer in the periphery. In this way, floating gates are substantially P-type while gates of peripheral transistors are N-type.

Abstract: A semiconductor memory device includes: a semiconductor substrate; a plurality of element isolation insulators disposed in parts of an upper layer portion of the semiconductor substrate and dividing the upper layer portion into a plurality of active areas extended in one direction; tunnel insulating films provided on the active areas: charge storage members provided on the tunnel insulating films; and control gate electrodes provided on the charge storage members. A width of a middle portion of one of the active areas in the up-to-down direction being smaller than a width of a portion of the active areas upper of the middle portion and a width of a portion of the active areas below the middle portion.

Abstract: The present invention provides a manufacturing method of a non-volatile memory including forming a gate dielectric layer on a substrate; forming a floating gate on the gate dielectric layer; forming a first charge blocking layer on the floating gate; forming a nitride layer on the first charge blocking layer; forming a second charge blocking layer on the nitride layer; forming a control gate on the second charge blocking layer; and performing a treatment to the nitride layer to get a higher dielectric constant.

Abstract: A nonvolatile semiconductor memory of an aspect of the present invention including a plurality of first active areas which are provided in the memory cell array side-by-side in a first direction and which have a dimension smaller than a fabrication limit dimension obtained by lithography, a second active area provided between the first active areas adjacent in the first direction, a memory cell unit which is provided in each of the plurality of first active areas and which has memory cells and select transistors, and a linear contact which is connected to one end of the memory cell unit and which extends in the first direction, wherein an area in which the linear contact is provided is one semiconductor area to which the plurality of first active areas are connected by the plurality of second active areas, and the bottom surface of the linear contact is planar.

Abstract: A non-volatile semiconductor memory device is proposed that has an unprecedented novel structure in which carriers can be injected into a floating gate by applying various voltages of the same polarity.

Abstract: A cell array portion of a single-layer gate EEPROM device includes a plurality of unit cells formed over a substrate to share a first well region in the substrate. Each of the plurality of unit cells includes a floating gate having a first part disposed over the first well region and a second part extending from the first part to have a strip shape, a selection gate spaced apart from the floating gate and disposed to be parallel with the second part of the floating gate, and an active region disposed in the substrate to intersect the floating gate and the selection gate.

Abstract: According to one embodiment, a nonvolatile memory includes the following structure. A first gate insulating film, a first floating gate, a second gate insulating film and a gate electrode are stacked on a semiconductor region between source and drain electrodes. A second floating gate is formed on a first side surface of the first floating gate. A first insulating film is formed between the first and second floating gates and has an air gap. A third floating gate is formed on a second side surface of the first floating gate on the opposite side of the first side surface. A second insulating film is formed between the first and third floating gates.

Abstract: A semiconductor device of the present invention is a semiconductor device selectively including a nonvolatile memory cell on a semiconductor substrate, and includes a trench formed in the semiconductor substrate, an element separation portion buried into the trench such that the element separation portion has a projecting part projecting from the semiconductor substrate, the element separation portion defining an active region in first a region for the nonvolatile memory cell of the semiconductor substrate, and a floating gate disposed in the active region such that the floating gate selectively has an overlapping part overlapping the element separation portion, and the floating gate has a shape recessed with respect to the overlapping part.