Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a plurality of first fin structures over a substrate. The first fin structure includes a first semiconductor material layer, a second semiconductor material layer disposed over the first semiconductor material layer, being at least partially surrounded by a semiconductor oxide feature. The device also includes a third semiconductor material layer disposed over the second semiconductor material layer and a second fin structures over the substrate and adjacent to one of the first fin structures. The second fin structure includes the first semiconductor material layer and the third semiconductor material layer disposed over the dielectric layer.

Abstract: Selective removal of specified layers of thin film structures and devices, such as solar cells, electrochromics, and thin film batteries, by laser direct patterning is achieved by including heat and light blocking layers in the device/structure stack immediately adjacent to the specified layers which are to be removed by laser ablation. The light blocking layer is a layer of metal that absorbs or reflects a portion of the laser energy penetrating through the dielectric/semiconductor layers and the heat blocking layer is a conductive layer with thermal diffusivity low enough to reduce heat flow into underlying metal layer(s), such that the temperature of the underlying metal layer(s) does not reach the melting temperature, Tm, or in some embodiments does not reach (Tm)/3, of the underlying metal layer(s) during laser direct patterning.

Abstract: Selective removal of specified layers of thin film structures and devices, such as solar cells, electrochromics, and thin film batteries, by laser direct patterning is achieved by including heat and light blocking layers in the device/structure stack immediately adjacent to the specified layers which are to be removed by laser ablation. The light blocking layer is a layer of metal that absorbs or reflects a portion of the laser energy penetrating through the dielectric/semiconductor layers and the heat blocking layer is a conductive layer with thermal diffusivity low enough to reduce heat flow into underlying metal layer(s), such that the temperature of the underlying metal layer(s) does not reach the melting temperature, Tm, or in some embodiments does not reach (Tm)/3, of the underlying metal layer(s) during laser direct patterning.

Abstract: Selective removal of specified layers of thin film structures and devices, such as solar cells, electrochromics, and thin film batteries, by laser direct patterning is achieved by including heat and light blocking layers in the device/structure stack immediately adjacent to the specified layers which are to be removed by laser ablation. The light blocking layer is a layer of metal that absorbs or reflects a portion of the laser energy penetrating through the dielectric/semiconductor layers and the heat blocking layer is a conductive layer with thermal diffusivity low enough to reduce heat flow into underlying metal layer(s), such that the temperature of the underlying metal layer(s) does not reach the melting temperature, Tm, or in some embodiments does not reach (Tm)/3, of the underlying metal layer(s) during laser direct patterning.

Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.

Abstract: Provided are a metamaterial structure and a manufacturing method thereof. The metamaterial structure includes a dielectric layer, nanowires penetrating the dielectric layer and arranged in a spacing having negative refraction with respect to an electromagnetic wave incident on the dielectric layer, and coating layers formed between the nanowires and the dielectric layer.

Abstract: A semiconductor chip includes a first mark for identifying a position of the chip within an exposure field. The semiconductor chip includes a first matrix in a first layer of the chip and a second mark within the first matrix identifying a position of the exposure field on a wafer.

Abstract: Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials.

Abstract: Systems and methods are provided for annealing a semiconductor device structure using microwave radiation. For example, a semiconductor device structure is provided. An interfacial layer is formed on the semiconductor device structure. A high-k dielectric layer is formed on the interfacial layer. Microwave radiation is applied to anneal the semiconductor device structure for fabricating semiconductor devices.

Abstract: A process for avoiding formation of an Si—SiO2—H2 environment during a dissolution treatment of a semiconductor-on-insulator structure that includes a carrier substrate, an oxide layer, a thin layer of a semiconductor material and a peripheral ring in which the oxide layer is exposed. This process includes encapsulating at least the exposed oxide layer of the peripheral ring with semiconductor material by performing a creep thermal treatment; and performing an oxide dissolution treatment to reduce part of the thickness of the oxide layer. In this process, the semiconductor material that encapsulates the oxide layer has a thickness before the oxide dissolution that is at least twice that of the oxide that is to be dissolved, thus avoiding formation of an Si—SiO2—H2 environment on the peripheral ring where the oxide layer would otherwise be exposed.

Abstract: A single dual-sided image sensor simultaneously captures discrete images from two different perspectives using both a front-side and a back-side of the image sensor. The two different perspectives are extracted from a composite image for processing. The two cameras, as configured in a device, face in a same direction and are spatially offset.

Abstract: Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer.

Abstract: A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.

Abstract: A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.

Abstract: There is provided a semiconductor device including a semiconductor layer, a protective layer including a transparent material, and a transparent resin layer that seals a gap between the semiconductor layer and the protective layer. A chip prevention member with a higher Young's modulus than the transparent resin layer is formed to come into contact with the semiconductor layer in a dicing portion of a layer structure before fragmentation, and dicing is performed in the dicing portion for the fragmentation.

Abstract: A semiconductor apparatus includes fin field-effect transistor (FinFETs) having controlled fin heights. The apparatus includes a high fin density area and a low fin density area. Each fin density area includes fins and dielectric material between the fins. The dielectric material includes different dopant concentrations for different fin density areas and is the same material as deposited.

Abstract: An epitaxial growth method includes the steps of: providing a substrate; forming a sacrifice layer on the substrate; patterning the sacrifice layer to form a plurality of bumps spaced apart from each other on the substrate; epitaxially forming a first epitaxial layer on the substrate to cover a portion of each of the bumps; removing the bumps to form a plurality of cavities; and epitaxially forming a second epitaxial layer on the first epitaxial layer such that the cavities are enclosed by the first epitaxial layer and the second epitaxial layer. An epitaxial structure grown by the method is disclosed as well.

Abstract: A magnetic field-guided method of metal-assisted chemical etching comprises immersing a structure that comprises a two-dimensional magnetic pattern layer on a surface thereof in an etchant solution. The magnetic pattern layer sinks into the structure as portions of the structure directly under the magnetic pattern layer are etched. A programmable magnetic field H(t) is applied to the structure during etching to guide the sinking of the magnetic pattern layer, thereby controlling the etching of the structure in three dimensions.

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract: A method of forming a nonvolatile memory cell includes forming a first electrode and a second electrode of the memory cell. Sacrificial material is provided between the first second electrodes. The sacrificial material is exchanged with programmable material. The sacrificial material may additionally be exchanged with select device material.

Abstract: A method for fabricating the device includes patterning a first structure and a second structure on a semiconductor device. A first angled ion implantation is applied to the second structure such that the first structure is protected and a second angled ion implantation is applied to the first structure such that the second structure is protected, wherein exposed portions of the first and second structures have an altered rate of oxidation. Oxidation is performed to form thicker or thinner oxide portions on the exposed portions of the first and second structures relative to unexposed portions of the first and second structures. Oxide portions are removed to an underlying layer of the first and second structures. The first and second structures are removed. Spacers are formed about a periphery of remaining oxide portions. The remaining oxide portions are removed. A layer below the spacers is patterned to form integrated circuit features.

Abstract: Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.

Abstract: A method of forming a carbon-containing thin film and a method of manufacturing a semiconductor device using the method of forming the carbon-containing thin film are described. The method of forming a carbon-containing thin film includes the steps of introducing a substrate into a chamber, injecting hydrocarbon gas and at least nitrogen gas simultaneously into the chamber, and depositing a carbon-containing thin film including carbon and nitrogen on the substrate, thereby forming a carbon-containing thin film having high selectivity and uniform thickness.

Abstract: A method for forming bond pads on a semiconductor die includes forming a dielectric stack including a bottom and top dielectric layer having a contact hole therethrough over a bond pad. An outer edge of the bottom dielectric layer within the contact hole extends beyond an outer edge of the top dielectric layer to define a bond pad edge. A second metal layer on a first metal layer is deposited. A first photoresist layer is formed exclusively within the contact hole. The second metal layer is wet etched to recess the second metal layer from sidewalls of the bottom dielectric layer in the contact hole. A second photoresist layer is formed exclusively within the contact hole. The first metal layer is wet etched to recess the first metal layer from the top dielectric layer. The first metal layer extends over the bond pad edge onto the bottom dielectric layer.

Abstract: Semiconductor devices are provided with dual passivation layers. A semiconductor layer is formed on a substrate and covered by a first passivation layer (PL-1). PL-1 and part of the semiconductor layer are etched to form a device mesa. A second passivation layer (PL-2) is formed over PL-1 and exposed edges of the mesa. Vias are etched through PL-1 and PL-2 to the semiconductor layer where source, drain and gate are to be formed. Conductors are applied in the vias for ohmic contacts for the source-drain and a Schottky contact for the gate. Interconnections over the edges of the mesa couple other circuit elements. PL-1 avoids adverse surface states near the gate and PL-2 insulates edges of the mesa from overlying interconnections to avoid leakage currents. An opaque alignment mark is desirably formed at the same time as the device to facilitate alignment when using transparent semiconductors.

Abstract: A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxy is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxy on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume.

Abstract: An article includes a substrate; and a coating disposed on the substrate that includes a microporous layer; a gradient in a density of a volume of the microporous layer, and a plurality of dendritic veins that are anisotropically disposed in the coating. A process for forming a coating includes disposing an activating catalyst on a substrate; introducing an activatable etchant; introducing an etchant oxidizer, performing an oxidation-reduction reaction between the substrate, the activatable etchant, and the etchant oxidizer in a presence of the activating catalyst, the oxidation-reduction reaction occurring in a liquid medium including the activatable etchant; and the etchant oxidizer, forming an etchant product comprising atoms from the substrate; removing a portion of the etchant product from the substrate; and forming a dendritic vein in the substrate to form the coating, the dendritic vein being anisotropically disposed in the coating.

Abstract: Methods for fabricating silicon nanowire chemical sensing devices, devices thus obtained, and methods for utilizing devices for sensing and measuring chemical concentration of selected species in a fluid are described. Devices may comprise a metal-oxide-semiconductor field-effect transistor (MOSFET) structure.

Abstract: A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first denuded zone being formed with a depth ranging from approximately 20 ?m to approximately 80 ?m from the top surface, and a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen uniformly distributed within a variation of 10% over the bulk area.

Abstract: In some embodiments, an integrated circuit includes a central array region having a first layout feature density. A background region surrounds the central array region and has a second layout feature density, which is different from the first density. A peripheral array region surrounds the central array region and separates the central array region from the background region. The peripheral array region has a third layout feature density between the first and second layout feature densities.

Abstract: Methods for forming a layer of semiconductor material and a semiconductor-on-insulator structure are provided. A substrate including one or more devices or features formed therein is provided. A seed layer is bonded to the substrate, where the seed layer includes a crystalline semiconductor structure. A first portion of the seed layer that is adjacent to an interface between the seed layer and the substrate is amorphized. A second portion of the seed layer that is not adjacent to the interface is not amorphized and maintains the crystalline semiconductor structure. Dopant implantation is performed to form an N-type conductivity region or a P-type conductivity region in the first portion of the seed layer. A solid-phase epitaxial growth process is performed to crystallize the first portion of the seed layer. The SPE growth process uses the crystalline semiconductor structure of the second portion of the seed layer as a crystal template.

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

Abstract: A method of forming a semiconductor structure includes forming a first fin in a p-FET device region of a semiconductor substrate and a second fin in an n-FET device region of the semiconductor substrate substantially parallel to the first fin. The first fin and the second fin each comprise a strained semiconductor material. Next, the second fin is amorphized to form a relaxed fin by implanting ions into the second fin while protecting the first fin.

Abstract: An etch mask is formed on a substrate. The substrate is positioned in an enclosure configured to shield an interior of the enclosure from electromagnetic fields exterior to the enclosure; and the substrate is etched in the enclosure, including removing a portion of the substrate to form a structure having at least a portion that is isolated and/or suspended over the substrate.

Abstract: A method of forming nanostructures may include forming a block copolymer composition within a trench in a material on a substrate, wherein the block copolymer composition may comprise a block copolymer material and an activatable catalyst having a higher affinity for a first block of the block copolymer material compared to a second block of the block copolymer material; self-assembling the block copolymer composition into first domains comprising the first block and the activatable catalyst, and second domains comprising the second block; generating catalyst from the activatable catalyst in at least one portion of the first domains to produce a structure comprising catalyst-containing domains and the second domains, the catalyst-containing domains comprising the first block and the catalyst; and reacting a metal oxide precursor with the catalyst in the catalyst-containing domains to produce a metal oxide-containing structure comprising the first block and metal oxide.

Abstract: A semiconductor device includes a backing plate, a semiconductor wafer, and integrated devices. The semiconductor wafer includes a plurality of semiconductor die having edges oriented along a reference line, a front surface facing the backing plate, and a backside surface. The backside surface is formed opposite the front surface and includes linear grind marks oriented along the reference line and diagonal with respect to the edges of the plurality of semiconductor die. The linear grind marks are formed by a linear motion of an abrasive surface, such as by a cylinder or wheel having an abrasive surface, and in one embodiment are oriented at 45 degrees with respect to the reference line. The linear grind marks increase a strength of the plurality of semiconductor die to resist cracking. Integrated devices are formed on the front surface of the semiconductor wafer.

Abstract: One embodiment describes a method of manufacturing a semiconductor device. Here, impurities are implanted into a semiconductor body via a first side of the semiconductor body. Thereafter, a drift zone layer on the first side of the semiconductor body is formed. The following is an ablation of the semiconductor body from a second side of the semiconductor body and up to pn junction defined by impurities.

Abstract: Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing material capped with silicon oxynitride. A mask is formed over the second masking features, and the silicon oxynitride caps are removed from the first masking features. Spacers are formed along sidewalls of the first masking features. The mask and the carbon-containing material of the first masking features are removed. Patterns of the spacers and second masking features are transferred into one or more materials of the base to pattern said one or more materials. Some embodiments include patterned bases.

Abstract: Embodiments relate to structures, systems and methods for more efficiently and effectively etching sacrificial and other layers in substrates and other structures. In embodiments, a substrate in which a sacrificial layer is to be removed to, e.g., form a cavity comprises an etch dispersion system comprising a trench, channel or other structure in which etch gas or another suitable gas, fluid or substance can flow to penetrate the substrate and remove the sacrificial layer. The trench, channel or other structure can be implemented along with openings or other apertures formed in the substrate, such as proximate one or more edges of the substrate, to even more quickly disperse etch gas or some other substance within the substrate.

Abstract: Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.

Abstract: A composite wafer 10 includes a supporting substrate 12 and a semiconductor substrate 14 which are bonded to each other by direct bonding. The supporting substrate 12 is a translucent alumina substrate with an alumina purity of 99% or more. The linear transmittance of the supporting substrate 12 at the visible light range is 40% or less. Furthermore, the total light transmittance from the front at a wavelength of 200 to 250 nm of the supporting substrate 12 is 60% or more. The average crystal grain size of the supporting substrate 12 is 10 to 35 ?m. The semiconductor substrate 14 is a single crystal silicon substrate. Such a composite wafer 10 has insulation performance and thermal conduction comparable to those of a SOS wafer, can be manufactured at low cost, and can be easily made to have a large diameter.

Abstract: A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area.

Abstract: A semiconductor arrangement includes a first semiconductor device including a first type region having a first conductivity type and a second type region having a second conductivity type. The semiconductor arrangement includes a second semiconductor device adjacent the first semiconductor device. The second semiconductor device includes a third type region having a third conductivity type and a fourth type region having a fourth conductivity type. The semiconductor arrangement includes a first insulator layer including a first insulator portion around at least some of the first semiconductor device and a second insulator portion around at least some of the second semiconductor device. The first insulator portion has a first insulator height, and the second insulator portion has a second insulator height. The first insulator height is different than the second insulator height. A method of forming a semiconductor arrangement is provided.

Abstract: A device includes a semiconductor chip. An outline of a frontside of the semiconductor chip includes at least one of a polygonal line including two line segments joined together at an inner angle of greater than 90° and an arc-shaped line.

Abstract: A semiconductor device includes a semiconductor layer over a substrate. The semiconductor layer changes direction at least twice and has at least two different widths in the same plane. The length of a current path through the semiconductor layer is greater than a shortest path through the semiconductor layer in the same plane.

Abstract: A chip package is described. This chip package includes a substrate having a side at an angle relative to the top and bottom surfaces of the substrate that is between that of a direction parallel to the top and bottom surfaces and that of a direction perpendicular to the top and bottom surfaces (i.e., between 0° and 90°). This side may be configured to couple to a stack of semiconductor dies in which the semiconductor dies are offset from each other in a direction parallel to the top and bottom surfaces so that one side of the stack defines a stepped terrace. For example, the side may include electrical pads. These electrical pads may be coupled to electrical pads on the top surface by through-substrate vias (TSVs) in the substrate. Moreover, the electrical pads on the top surface may be configured to couple to an integrated circuit.

Abstract: A semiconductor structure comprises a substrate comprising a first crystalline semiconductor material, a dielectric layer, above the substrate, defining an opening, a second crystalline semiconductor material at least partially filling the opening, and a crystalline interlayer between the substrate and the second crystalline semiconductor material. The first crystalline semiconductor material and the second crystalline semiconductor material are lattice mismatched, and the crystalline interlayer comprises an oxygen compound. A method for fabricating semiconductor structure comprises the steps of providing a substrate including a first crystalline semiconductor material, patterning an opening in a dielectric layer above the substrate, the opening having a bottom, forming a crystalline interlayer on the substrate at least partially covering the bottom, and growing a second crystalline semiconductor material on the crystalline interlayer thereby at least partially filling the opening.

Abstract: A method of forming a semiconductor device includes forming an insulator layer over a substrate; opening a trench in the insulator layer so as to expose one or more semiconductor structures formed on the substrate; forming a protective layer on sidewalls of the trench; subjecting the substrate to a precleaning operation in preparation for epitaxial semiconductor formation, wherein the protective layer prevents expansion of the sidewalls of the trench as a result of the precleaning operation; and forming epitaxial semiconductor material within the trench and over the exposed one or more semiconductor structures.