Abstract: A semiconductor device has an insulation substrate formed with a conductive pattern; an independent terminal, which is an externally leading terminal, soldered to the conductive pattern of the insulation substrate; a case disposed over the insulation substrate such that a top surface of the independent terminal is exposed; an opening provided on a side surface of the case; a nut glove inserted from the opening so as to be below the independent terminal, and fix the independent terminal; and a first projection part formed on a side surface of the nut glove, and having tapers in a frontward direction and a rearward direction of insertion of the nut glove, respectively. The rearward taper of the first projection part is pressure contacting with a sidewall surface of the opening.

Abstract: The present stacked semiconductor packages include a bottom package and a top package. The bottom package includes a substrate, a solder mask layer, a plurality of conductive pillars and a die electrically connected to the substrate. The solder mask layer has a plurality of openings exposing a plurality of pads on the substrate. The conductive pillars are disposed on at least a portion of the pads, and protrude from the solder mask layer.

Abstract: Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.

Abstract: The present invention is directed to a semiconductor packaging solution wherein a high K thermal material such as a grease or gel is placed in a controlled thin bond line between the semiconductor die of the package and a heat sink in a direct manner using a thermal tape window frame as a low cost mechanical attachment mechanism. As the main thermal dissipation path is between the backside of the semiconductor die and the heat sink, a high K TIM material can be used to maximize thermal dissipation in a manner that does not require expensive mechanical attachment methods.

Abstract: Disclosed herein is a semiconductor package, including: a substrate having a first surface and a second surface; at least one semiconductor device formed on the first surface of the substrate; first lead frames respectively formed at both sides of the first surface of the substrate; and second lead frames respectively formed at both sides of the second surface of the substrate, wherein the first lead frame and the second lead frame are spaced apart from each other by an isolation distance base.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a post of multiple plating layers having a base end with an inward protrusion, a connect riser, and a top end opposite the base end; positioning an integrated circuit device having a perimeter end facing the connect riser and the inward protrusion; attaching a bond wire directly on the inward protrusion and the integrated circuit device; and applying an encapsulation over the integrated circuit device, the bond wire, the inward protrusion, and around the post, the encapsulation exposing a portion of the base end and the top end of the post.

Abstract: An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

Abstract: Provided is a ball grid array substrate, a semiconductor chip package, and a method of manufacturing the same. The ball grid array substrate includes an insulating layer having a first surface providing a mounting region for a semiconductor chip, a second surface opposing the first surface, and an opening connecting the second surface with the mounting region of the semiconductor chip, and a circuit pattern buried in the second surface. Since the ball grid array substrate is manufactured by a method of stacking two insulating layers, existing devices can be used, and the ball grid array substrate can be manufactured as an ultra thin plate. In addition, since the circuit pattern is buried in the insulating layer, a high-density circuit pattern can be formed.

Abstract: A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects.

Abstract: A chip design (1) comprising an external supply connection (VBAT), an internal supply connection (VDD), an integrated circuit (2) that is coupled to the internal supply connection (VDD) for voltage supply, and a fuse (3) that electrically connects the internal supply connection (VBAT) and is arranged within the chip design (1).

Abstract: A semiconductor package has a first substrate having a plurality of electrically conductive patterns formed thereon. A first semiconductor die is coupled to the plurality of conductive patterns. A second semiconductor die is coupled to the first semiconductor die by a die attach material. A third semiconductor die is coupled to the second semiconductor die by a die attach material. A second substrate having a plurality of electrically conductive patterns formed thereon is coupled to the third semiconductor die. A plurality of contacts is coupled to a bottom surface of the first substrate. A connector jack is coupled to the second substrate. A plurality of leads is coupled to the second semiconductor die by conductive wires.

Abstract: An electronic device includes a first semi-conductor die, a second semi-conductor die and an electrically conductive element. The electrically conductive element includes a first electrically conductive part interposed at least partially between the first semi-conductor die and the second semi-conductor die, wherein said first part is electrically coupled to the first semi-conductor die. The electrically conductive element further includes a second electrically conductive part electrically coupled to the first part, wherein said second part extends from at least part of the first part. The first part is an electrically conductive strap between the dice, and the second part is clip extending from at least part of the strap.

Abstract: An electronic device package comprising: a block of insulating material; an electronic device housed within the insulating material and having a set of contact pads thereon; and a set of electrically conductive contact members at least partially housed within the insulating material, each contact member extending between a respective external contact point at which it is exposed at the surface of the block and an internal contact point from which it is electrically coupled to a respective contact pad on the electronic device, each internal contact point being outside the footprint of the electronic device, the set of contact members including: at least one contact member of a first type whose external contact point is located at least partially within the footprint of the electronic device; and at least one contact member of a second type that is wholly outside the footprint of the device.

Abstract: Aspects of the present invention are directed to circuits, circuit packages and related methods. In accordance with various example embodiments, respective electrodes are implemented to facilitate contact to a semiconductor device via different surfaces and/or sidewalls, as may be useful in connecting the device to an external package having a plurality of semiconductor devices in which same-surface connections to the devices are spatially restricted. The semiconductor device has opposing surfaces and sidewalls connecting the surfaces, and contacts to respective different regions in the device. Respective electrodes are coupled to the respective contacts and extend along/around the device to provide access to the contacts via different surfaces.

Abstract: According to an embodiment, a chip package is provided, which includes: a substrate having a first surface and a second surface; a device region formed in the substrate; a passivation layer formed overlying the first surface of the substrate; at least a polymer planarization layer formed overlying the passivation layer; a package substrate disposed overlying the first surface of the substrate; and a spacer layer disposed between the package substrate and the passivation layer, wherein the spacer layer and the package substrate surround a cavity overlying the substrate, wherein the polymer planar layer does not extends to an outer edge of the spacer layer.

Abstract: A power semiconductor device has the power semiconductor elements having back surfaces bonded to wiring patterns and surface electrodes, cylindrical communication parts having bottom surfaces bonded on the surface electrodes of the power semiconductor elements and/or on the wiring patterns, a transfer mold resin having concave parts which expose the upper surfaces of the communication parts and cover the insulating layer, the wiring patterns, and the power semiconductor elements. External terminals have one ends inserted in the upper surfaces of the communication parts and the other ends guided upward, and at least one external terminal has, between both end parts, a bent area which is bent in an L shape and is embedded in the concave part of the transfer mold resin.

Abstract: A semiconductor device package including a substrate, first and second solder joints, a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.

Abstract: The thermal interface material including a thermally conductive metal a thermally conductive metal having a first surface and an opposing second surface, a diffusion barrier plate coupled to the first surface of the thermally conductive metal and the second surface of the thermally conductive metal, and a thermal resistance reducing layer coupled to the diffusion barrier plate.

Abstract: In one implementation, a high power semiconductor package is configured as a buck converter including a control transistor and a sync transistor disposed on a leadframe, a flip chip driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. The source of the control transistor is electrically coupled to the drain of the sync transistor using the leadframe and one of the transistor conductive clips. In this manner, the leadframe and the conductive clips provide efficient current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost.

Abstract: A light emitting device package is disclosed. The light emitting device package includes a light emitting device disposed on a first lead frame, the light emitting device having an electrode pad on an upper surface thereof, a first wire to electrically interconnect a second lead frame spaced apart from the first lead frame and the electrode pad, and a first bonding ball disposed on the second lead frame, the first bonding ball spaced apart from a first contact point, which is in contact with the first wire and the second lead frame, wherein the first bonding ball is disposed between the first wire and the second lead frame to electrically interconnect the first wire and the second lead frame.

Abstract: Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a die having a first surface and a second surface opposite the first surface, a conductive pillar formed on the first surface of the die, and an encapsulant material encasing the die, including covering the first surface, the second surface, and at least a portion of a side surface of the conductive pillar. Methods for making the same also are described.

Abstract: Disclosed is a semiconductor structure including a semiconductor substrate including an electronic circuit which is provided in a predetermined region of the semiconductor substrate, a wiring provided on the semiconductor substrate in a region outside of the predetermined region, an external connection electrode provided on the wiring, a sealing resin which covers a side surface of the external connection electrode and a wall which intervenes between the electronic circuit and the sealing resin.

Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; pressing an encapsulation onto the package carrier and with the integrated circuit therein; mounting a conductive frame, having a vertical pillar integral with a horizontal cover, through the encapsulation, over the integrated circuit, and the vertical pillar on the package carrier and the horizontal cover on the encapsulation; and forming a contact from the horizontal cover.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral contact layer surrounding the peripheral lead with a non-horizontal side exposed from the peripheral contact layer; forming an inner lead and a paddle non-planar with the peripheral lead; mounting an integrated circuit to the paddle; and forming an encapsulation covering the integrated circuit and exposing the inner lead, the paddle, and the non-horizontal side.

Abstract: A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.

Abstract: An LED package includes a substrate with two opposite lateral bulging portions, an LED die, an electrode structure, and a reflective layer. The substrate includes a first substrate and a second substrate stacked together; the first substrate and the second substrate are transparent; and the substrate includes an emitting surface for emitting light of the LED package. The electrode structure is sandwiched between the first substrate and the second substrate. The LED die is mounted in the substrate and electrically connected to the electrode structure. The reflective layer is formed on an outer surface of the substrate except the emitting surface and the bulging portions. The disclosure also provides a method for manufacturing such an LED package.

Abstract: Provided is a manufacturing method of a substrate for a semiconductor element including the steps of: providing a first photosensitive resin layer on a first surface of a metal plate; providing a second photosensitive resin layer on a second surface different from the first surface of the metal plate; forming a first etching mask for forming a connection post on the first surface of the metal plate; forming a second etching mask for forming a wiring pattern on the second surface of the metal plate; forming the connection post by performing an etching from the first surface to a midway of the metal plate; filling in a premold resin to a portion of the first surface where the connection post does not exist; processing so that a height of the connection post of the first surface is lower than a height of the premold resin surrounding the connection post; and forming the wiring pattern by performing an etching on the second surface.

Abstract: A semiconductor die includes interface logic for performing a function on an external device, and a surrogate circuit in communication with the interface logic. The interface logic facilitates testing of the interface logic by attempting to perform the function on the surrogate circuit. The interface logic may be a memory interface, and the surrogate circuit may be a memory circuit that is a smaller and simpler replica of an external memory die. The surrogate circuit allows the interface logic to be tested before the semiconductor die is physically coupled to the external device, for exampled in a three dimensional (3D) integrated circuit (IC).

Abstract: An ESD protection device is manufactured such that its ESD characteristics are easily adjusted and stabilized. The ESD protection device includes an insulating substrate, a cavity provided in the insulating substrate, at least one pair of discharge electrodes each including an exposed portion that is exposed in the cavity, and external electrodes provided on a surface of the insulating substrate and connected to the discharge electrodes. Supporting electrodes obtained by dispersing conductive powder in an insulating material defining the insulating substrate are provided along a bottom surface and a top surface that define the cavity between the exposed portions of the at least one pair of discharge electrodes.

Abstract: The light emitting device according to the present invention includes a resin molded body having a recess, a first electrically conductive member and a second electrically conductive member each having terminal portions respectively exposed from a first outer side surface and second outer side surface which are opposite outer side surfaces among the outer side surfaces of the resin molded body, and a light emitting element mounted on the first electrically conductive member exposed at a bottom surface of the recess. The recess has a first bottom surface on which the light emitting element is mounted and a second bottom surface arranged at a higher position of the outer periphery of the first bottom surface.

Abstract: Parylene-coated, ultra ruggedized ball grid array electronic components include a substrate with electronic components attached to one surface, and solder balls attached to a second substrate surface through openings formed in the parylene coating.

Abstract: A multimode system with at least two end points may include a multimode signaling path that, in some embodiments, is a multimode cable or a multimode board and is pluggably connectable to packages at each end point. Each end point may include a processor die package coupled to a socket. The socket may also receive a connector that couples the cable to the package. Power supply signals and input/output signals may be decoupled at each end point.

Abstract: In some aspects of the invention, an insulating substrate fixed onto a metal base plate can include an insulating plate and metal foils. A semiconductor element can be disposed on each of the metal foils. External connection terminals can be fixed to a set of ends of terminal holders, respectively. The other ends of the terminal holders can be bonded to the metal foils, respectively. External connection terminals which are main terminals through which main current flows are disposed on a lid. By preparing a plurality of lids having different layouts of the external connection terminals, in which the external connection terminals are connected to the terminal holders in the resin case, respectively, and exchanging the lids, the positions of the external connection terminals can be easily changed.

Abstract: A wiring process between the provided power semiconductor module and the external circuit is simple. In the power semiconductor module, a power semiconductor element and a cylindrical conductor are joined to one surface of a lead frame. An opening of the cylindrical conductor is exposed at a surface of transfer molding resin. Sealing with the transfer molding resin is performed such that terminal portions of the lead frame protrude from peripheral side portions of the transfer molding resin. The cylindrical conductor is conductive with a control circuit. The terminal portions of the lead frame are each conductive with a main circuit.

Abstract: A semiconductor housing package may be provided. The semiconductor housing package may include a mold layer, a housing chip, a redistribution structure, and a housing node. The mold layer may surround and partially expose the housing chip. The redistribution structure may be electrically connected to the housing chip and may be disposed on the mold layer. The housing node may be in contact with the redistribution structures. The semiconductor housing package may be disposed on a semiconductor base package and may constitute a semiconductor package structure along with the semiconductor base package. The semiconductor package structure may be disposed on a processor-based system.

Abstract: An apparatus provides good bonding between a package structure and a substrate and extended solder bonding life, even under heat stress. Of a lead frame to be used for a package structure having a configuration in which a semiconductor chip, an island of the lead frame, and external connection terminals are sealed with a resin from one surface, and the island and the external connection terminals are exposed on the other surface, the external connection terminals include a first external connection terminal disposed at a central part of each of sides of an outer rim of a semiconductor chip mounting region in which the semiconductor chip is to be mounted and a second external connection terminal outside the first external connection terminal at each of the sides of the outer rim of the semiconductor chip mounting region, wherein the first external connection terminal area exceeds the second external connection terminal's.

Abstract: A method for creating an improved signal light is disclosed. For example, the improved signal light includes a housing, one or more first type of light emitting diodes (LEDs) emitting a light energy having a first dominant wavelength deployed in the housing, one or more second type of LEDs emitting a light energy having a second dominant wavelength deployed in the housing, a filter and a mixer. The filter may filter the light energy of the one or more second type of LEDs such that only a third dominant wavelength passes from the one or more second type of LEDs. The mixer may mix the light energy having the first dominant wavelength and the filtered light energy having the third dominant wavelength to form a light energy having a desired fourth dominant wavelength.

Abstract: A first wiring (1) has a bending portion (2), a first wiring region (1a) extending from the bending portion (2) in the X direction, and a second wiring region (1b) extending from the bending portion (2) in the Y direction. A via (3) is formed under the wiring (1). The via (3) is formed so as not to overlap with a region of the bending portion (2) in the first wiring region (1a). The length of the via (3) in the X direction (x) is longer than the length thereof in the Y direction (y) and both ends of the via (3) in the Y direction overlap with both ends of the first wiring region (1a) in the Y direction.

Abstract: An ESD protection device is manufactured such that its ESD characteristics are easily adjusted and stabilized. The ESD protection device includes an insulating substrate, a cavity provided in the insulating substrate, at least one pair of discharge electrodes each including a portion exposed in the cavity, the exposed portions being arranged to face each other, and external electrodes provided on a surface of the insulating substrate and connected to the at least one pair of discharge electrodes. A particulate supporting electrode material having conductivity is dispersed between the exposed portions of the at least one pair of discharge electrodes in the cavity.

Abstract: A metal base circuit board, having an insulating layer with a linear expansion coefficient of 60 ppm per degree C. or higher and 120 ppm per degree C. or lower, a metal foil provided on one side of the insulating layer, comprising a metal material with a linear expansion coefficient of 10 ppm per degree C. or higher and 35 ppm per degree C. or lower, a circuit portion and a non-circuit potion having a linear expansion coefficient of 10 ppm per degree C. or higher and 35 ppm per degree C.

Abstract: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.

Abstract: An integrated circuit structure can include a first die including a first surface and a second surface and a second die including a first surface and a second surface. The first surface of the first die can be coupled to the second surface of the second die. The integrated circuit structure also can include a heat sink coupled to the first surface of the first die and the first surface of the second die.

Abstract: Provided is a semiconductor device in which a connection between connection terminals and land of the semiconductor device can be checked with the semiconductor device kept in a sound condition, the connection not being allowed to be checked with a semiconductor chip. The semiconductor device of the present invention includes: a package substrate; a semiconductor chip mounted on the package substrate; a first land formed in a first principal surface of the package substrate; a second land formed in a second principal surface of the package substrate; first connection terminals connected to the second land and having the connection thereto not allowed to be checked with the semiconductor chip; a connection interconnection for connecting the first land and the second land; a second connection terminal formed in the second principal surface of the package substrate; and a branch interconnection for connecting the connection interconnection and the second connection terminal.

Abstract: A wafer level semiconductor package is provided. A warpage control barrier line formed in every package of a single wafer prevents wafer from warping. The changed shape of the interface between a semiconductor chip and a molding layer at the edge of the package disperses stress applied to the outside of the package, and suppress the generation and propagation of crack. The size of the package is reduced to that of the semiconductor, and the thickness of the package is minimized.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first terminal; connecting an integrated circuit to the first terminal; forming a second terminal connected over the first terminal and the integrated circuit by a vertical conductive post integral with the first terminal or the second terminal; and encapsulating the integrated circuit and the vertical conductive post leaving portions of the first terminal and the second terminal exposed.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

Abstract: A wafer for electronic component packages is used for manufacturing a plurality of electronic component packages, each of the plurality of electronic component packages including: a base incorporating a plurality of external connecting terminals; and at least one electronic component chip bonded to the base and electrically connected to the plurality of external connecting terminals. The wafer has a plurality of sets of external connecting terminals corresponding to the plurality of electronic component packages, a retainer for retaining the plurality of sets of external connecting terminals, and a coupling portion for coupling the plurality of sets of external connecting terminals to one another. The wafer includes a plurality of pre-base portions that will each be subjected to bonding of the at least one electronic component chip thereto and will be subjected to separation from one another later so that each of them will thereby become the base.

Abstract: A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.

Abstract: A system or microelectronic assembly can include one or more microelectronic packages each having a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.

Abstract: A semiconductor module includes a module housing, at least one substrate, a number N of at least two controllable power semiconductor chips arranged inside the module housing and one after another in a lateral direction, a single main load terminal arranged outside the module housing and electrically connected to the first main electrodes, and an auxiliary terminal arranged outside the module housing and electrically connected to the first main electrodes via an auxiliary terminal connecting conductor.