Abstract: A method of manufacturing a display device, the method including forming a first layer on a rigid glass substrate, the first layer having a hydrophobic surface; forming a second layer to be bonded to a rigid thin glass substrate on the first layer to prepare a carrier substrate; bonding the rigid thin glass substrate onto the second layer; forming and encapsulating a display portion on an upper surface of the rigid thin glass substrate; and irradiating a laser beam to delaminate the first layer and detaching the rigid thin glass substrate from the rigid glass substrate.

Abstract: The present disclosure provides a method and system for characterizing a pattern loading effect. A method may include performing a reflectivity measurement on a semiconductor wafer and determining an anneal process technique based on the reflectivity measurement. The determining the anneal process technique may include determining a spatial distance for a reflectivity change using a reflectivity map generated using the reflectivity measurement. This spatial distance is compared with the thermal diffusion length associated with each of the plurality of anneal process techniques. In an embodiment, a thermal profile map and/or a device performance map may be provided.

Abstract: The present invention discloses a method of manufacturing semiconductor devices. The method includes a step of performing a chemical mechanical planarization processing on a poly-silicon layer before fabricating a poly-silicon gate such that the poly-silicon gates obtained in subsequent fabrication process are kept at the same height, which thus avoids the silicon nitride residues issue that occurs in the prior art. Therefore, the present invention is capable of enhancing product yield of semiconductor devices and improving device performances.

Abstract: A light emitting device includes a conductive substrate, a plurality of light emitting cells disposed on the conductive substrate, wherein each of the plurality of light emitting device cells includes a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, a protective layer disposed to cover a side of the first semiconductor layer and a side of the active layer, and a first electrode for connecting the second semiconductor layers of more than one of the light emitting cells to each other, wherein the protective layer includes protruding portions extending to an inside of each of the light emitting cells from the side of the first semiconductor layer and the side of the active layer.

Abstract: A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.

Abstract: Methods of fabricating a semiconductor device including a metal gate transistor and a resistor are provided. A method includes providing a substrate including a transistor device region and an isolation region, forming a dummy gate over the transistor device region and a resistor over the isolation region, and implanting the resistor with a dopant. The method further includes wet etching the dummy gate to remove the dummy gate, and then forming a metal gate over the transistor device region to replace the dummy gate.

Abstract: A method includes a first bonding step of bonding a first main surface of a first solar cell and one side portion of a first wiring member to each other in such a way that the first main surface of the first solar cell and the one side portion are heated and pressed against each other by heated first and second tools in a state where the first main surface of the first solar cell and the one side portion face each other with the resin adhesive interposed therebetween. The first bonding step is performed with the first tool disposed in such a way that, in an extending direction of the first wiring member, both end portions of the first tool are located outside both ends of a portion of the first wiring member, the portion facing the first solar cell with the resin adhesive interposed therebetween.

Abstract: A method of forming a dielectric film having Si—C bonds and/or Si—N bonds on a semiconductor substrate by cyclic deposition, includes: (i) conducting one or more cycles of cyclic deposition in a reaction space wherein a semiconductor substrate is placed, using a Si-containing precursor and a reactant gas; and (ii) before or after step (i), applying a pulse of RF power to the reaction space while supplying a rare gas and a treatment gas without supplying a Si-containing precursor, whereby a dielectric film having Si—C bonds and/or Si—N bonds is formed on the semiconductor substrate.

Abstract: A semiconductor wafer has a plurality of semiconductor die separated by a saw street. The wafer is mounted to dicing tape. The wafer is singulated through the saw street to expose side surfaces of the semiconductor die. An ESD protection layer is formed over the semiconductor die and around the exposed side surfaces of the semiconductor die. The ESD protection layer can be a metal layer, encapsulant film, conductive polymer, conductive ink, or insulating layer covered by a metal layer. The ESD protection layer is singulated between the semiconductor die. The semiconductor die covered by the ESD protection layer are mounted to a temporary carrier. An encapsulant is deposited over the ESD protection layer covering the semiconductor die. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The ESD protection layer is electrically connected to the interconnect structure to provide an ESD path.

Abstract: A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.

Abstract: In a package wherein a lead part coupled to a semiconductor element by wire bonding, an element retention member to retain the semiconductor element on the top face side and radiate heat on the bottom face side, and an insulative partition part to partition the lead part from the element retention member with an insulative resin appear, a creeping route ranging from the top face to retain the semiconductor element to a package bottom face on a boundary plane between the element retention member and an insulative partition part includes a bent route having a plurality of turns. Consequently, it is possible to inhibit an encapsulation resin to seal a region retaining the semiconductor element from exuding toward the bottom face side of the package.

Abstract: The present invention discloses a structure and a manufacturing method for a high-resolution camera module, wherein the method includes the following steps: providing an image sensor wafer comprising multiple image sensor chips; performing inspection and defining if each image sensor chip is a good chip; disposing an optical cover on the image sensor chip defined as the good chip, wherein the optical cover faces a sensing area and does not cover conductive contacts; cutting the image sensor wafer to obtain the discrete image sensor chip covered with the optical cover; and disposing a first surface of the divided image sensor chip on a bottom surface of a ceramic substrate. The present invention can seal the high resolution camera module during early stage of the manufacturing process to improve the yield rate of the camera module, and downsize the camera module effectively.

Abstract: Embodiments of the invention provide for fabricating a filter, for electromagnetic radiation, in at least three ways, including (1) fabricating integrated thin film filters directly on a detector; (2) fabricating a free standing thin film filter that may be used with a detector; and (3) treating an existing filter to improve the filter's properties.

Abstract: A semiconductor device includes a silicon substrate having a protrusion, a gate insulating film formed over an upper surface of the protrusion of the silicon substrate, a gate electrode formed over the gate insulating film, a source/drain region formed in the silicon substrate on the side of the gate electrode, a first side wall formed over the side surface of the protrusion of the silicon substrate, the first side wall containing an insulating material, a second side wall formed over the first side wall, the second side wall having a bottom portion formed below the upper surface of the protrusion of the silicon substrate, the second side wall containing a material having a Young's modulus greater than that of the silicon substrate, and a stress film formed over the gate electrode and the second side wall.

Abstract: The present invention is directed to a method for producing a bonded wafer, the method in which heat treatment for flattening the surface of a thin film is performed on a bonded wafer made by the ion implantation delamination method in an atmosphere containing hydrogen or hydrogen chloride, wherein the surface of a susceptor on which the bonded wafer is to be placed, the susceptor used at the time of flattening heat treatment, is coated with a silicon film in advance. As a result, a method for producing a bonded wafer is provided, the method by which a bonded wafer having a thin film with good film thickness uniformity can be obtained even when heat treatment for flattening the surface of a thin film of a bonded wafer after delamination is performed in the ion implantation delamination method.

Abstract: An embodiment is a method for semiconductor packaging. The method comprises attaching a chip to a carrier substrate through a first side of a jig, the chip being attached by bumps; applying balls to bond pads on the carrier substrate through a second side of the jig; and simultaneously reflowing the bumps and the balls. According to a further embodiment, a packaging jig comprises a cover, a base, and a connector. The cover has a first window through the cover. The base has a second window through the base. The first window exposes a first surface of a volume intermediate the cover and the base, and the second window exposes a second surface of the volume. The first surface is opposite the volume from the second surface. The connector aligns and couples the cover to the base.

Abstract: A laser processing method which can accurately cut an object to be processed along a line to cut is provided. A modified region 7 formed by multiphoton absorption forms a cutting start region 8 within an object to be processed 1 along a line to cut 5. Thereafter, the object 1 is irradiated with laser light L2 absorbable by the object 1 along the line to cut 5, so as to generate fractures 24 from the cutting start region 8 acting as a start point, whereby the object 1 can accurately be cut along the line to cut 5. Expanding an expandable film 19 having the object 1 secured thereto separates individual chips 25 from each other, which can further improve the reliability in cutting the object 1 along the line to cut 5.

Abstract: Provided herein are novel pre-metal dielectric (PMD) integration schemes. According to various embodiments, the methods involve depositing flowable dielectric material to fill trenches or other gaps between gate structures in a front end of line (FEOL) fabrication process. The flowable dielectric material may be partially densified to form dual density filled gaps having a low density region capped by a high density region. In certain embodiments, the methods include further treating at least a portion of the gap fill material after subsequent process operations such as chemical mechanical planarization (CMP) or contact etching.

Abstract: An assembly and method of making same are provided. The assembly can be formed by stacking a first semiconductor element atop a second semiconductor element and forming an electrically conductive element extending through openings of the semiconductor elements. The openings may be staged. The conductive element can conform to contours of the interior surfaces of the openings and can electrically connect conductive pads of the semiconductor elements. A dielectric region can be provided at least substantially filling the openings of the semiconductor elements, and the electrically conductive element can extend through an opening formed in the dielectric region.

Abstract: A semiconductor package includes a circuit substrate, a semiconductor chip on the circuit substrate, an inner solder ball between the circuit substrate and the semiconductor chip, and dummy solder filling a dummy opening in at least one of an substrate insulation layer of the circuit substrate and a chip insulation layer. The dummy solder does not electrically connect the semiconductor chip with the substrate. The circuit substrate may include a base substrate, a substrate connection terminal on the base substrate, and the substrate insulation layer covering the base substrate. The semiconductor chip may include a chip connection terminal and the chip insulation layer exposing the chip connection terminal. The inner solder ball may be interposed between the substrate connection terminal and the chip connection terminal to electrically connect the circuit substrate to the semiconductor chip.

Abstract: Manufacturing a semiconductor structure including: forming a seed material on an insulator layer; forming a graphene field effect transistor (FET) on the seed material; and forming an air gap under the graphene FET by removing the seed material.

Abstract: An electronic package implemented in an electronic device may include a damaged connection that restricts electrical communication between components in the electronic package. For example, the damaged connection may restrict communication between a silicon unit, such as a processor die for example, and a printed circuit board. The damaged connection may be repaired without damaging other components in the electronic package by using a repair apparatus that includes a heating element and a cooling element. The heating element may be activated to transfer heat to the electronic package for reforming the damaged connection between components to enable effective electrical communication. The cooling element may be activated for cooling components in the electronic package to prevent damage due to the transfer of the heat from the heating element. The heating element and/or the cooling element may be activated in a predetermined pattern to facilitate the repair of the damaged connection.

Abstract: A semiconductor device structure includes a substrate having a transistor thereon; a multi-layer contact etching stop layer (CESL) structure covering the transistor, the multi-layer CESL structure comprising a first CESL and a second CESL; and a dielectric layer on the second CESL. The first CESL is made of a material different from that of the second CESL, and the second CESL is made of a material different from that of the dielectric layer.

Abstract: An image sensor including a plurality of pixels each including a charge collection region including an N-type region bounded by P-type regions and having an overlying P-type layer; and an insulated gate electrode positioned over the P-type layer and arranged to receive a gate voltage for conveying charges stored in the charge collection region through the P-type layer.

Abstract: Disclosed herein is a display device, including: a substrate; a circuit part configured to include a drive element; a planarization insulating layer; an electrically-conductive layer including a plurality of first electrodes and an auxiliary interconnect; an aperture-defining insulating layer configured to insulate the plurality of first electrodes from each other and have an aperture through which part of the first electrode is exposed; a plurality of light emitting elements; and a separator configured to be formed by removing the planarization insulating layer at a position between a display area, in which the plurality of light emitting elements connected to the drive element are disposed, and a peripheral area which is surrounding the display area. A method of manufacturing a display device is also provided.

Abstract: In a POP type semiconductor device comprising a second semiconductor package as an upper package stacked on a first semiconductor package as a lower package, a plurality of main surface-side lands formed on a first wiring substrate of the first semiconductor package are disposed distributively on both sides of a chip mounting region as a boundary positioned at a central part of a main surface of the first wiring substrate, thus permitting the adoption of a through molding method. Consequently, a first sealing body formed on the main surface of the first wiring substrate in the first semiconductor package as a lower package extends from one second side of the first wiring substrate toward a central part of the other second side of the same substrate.

Abstract: Provided is a method for manufacturing a nitride semiconductor device, including the steps of: forming an AlNO buffer layer containing at least aluminum, nitrogen, and oxygen on a substrate; and forming a nitride semiconductor layer on the AlNO buffer layer, wherein, in the step of forming the AlNO buffer layer, the AlNO buffer layer is formed by a reactive sputtering method using aluminum as a target in an atmosphere to and from which nitrogen gas and oxygen gas are continuously introduced and exhausted, and the atmosphere is an atmosphere in which a ratio of a flow rate of the oxygen gas to a sum of a flow rate of the nitrogen gas and the flow rate of the oxygen gas is not more than 0.5%.

Abstract: A resin material layer including photosensitive resin material is formed on an interlayer on an underlayer. By partially exposing and developing the resin material layer using developer in which the resin material layer and the interlayer are soluble, an uncured portion of the resin material layer is removed to form an opening penetrating to the interlayer, and the developer infiltrates into the interlayer via the opening to remove at least surfaces of first and second portions of the interlayer. The first portion corresponds to the opening. The second portion surrounds the first portion. Each bank is formed by heating a remaining portion of the resin material layer to soften an overhanging portion above a space formed by the surface of the second portion being removed, so that the overhanging portion flows downward to fill the space, cover an exposed portion of the interlayer, and contact the underlayer or the interlayer.

Abstract: A process of forming a MEMS device with a device cavity underlapping an overlying dielectric layer stack having an etchable sublayer over an etch-resistant lower portion, including: etching through at least the etchable sublayer of the overlying dielectric layer stack in an access hole to expose a lateral face of the etchable sublayer, covering exposed surfaces of the etchable sublayer by protective material, and subsequently performing a cavity etch. A cavity etch mask may cover the exposed surfaces of the etchable sublayer. Alternatively, protective sidewalls may be formed by an etchback process to cover the exposed surfaces of the etchable sublayer. Alternatively, the exposed lateral face of the etchable sublayer may be recessed by an isotropic etch, than isolated by a reflow operation which causes edges of an access hole etch mask to drop and cover the exposed lateral face of the etchable sublayer.

Abstract: In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.

Abstract: The present invention provides a semiconductor device manufacturing method. This method comprises: etching a first dielectric layer to form a recess; depositing a second dielectric layer over said first dielectric layer and said recess, such that said recess is enclosed by said first dielectric layer and said second dielectric layer to form an air gap; and performing etching, such that a first trench is formed in said first dielectric layer and said second dielectric layer, adjacent to said air gap. The first trench can be filled with a conductive material to form wiring.

Abstract: Disclosed herein is a device that includes: an interlayer insulation film having a through hole; and a phase change storage element provided in the through hole. The phase change storage element includes: an outer electrode being a conductive film of cylindrical shape and being formed along an inner wall of the through hole; a buffer insulation film being an insulation film of cylindrical shape and being formed along an inner wall of the outer electrode, an upper end of the buffer insulation film being recessed in part to form a recess; a phase change film filling an interior of the recess; and an inner electrode being a conductive film formed along an inner wall of the buffer insulation film including a surface of the phase change film.

Abstract: Manufacturing a semiconductor structure including: forming a seed material on a sidewall of a mandrel; forming a graphene field effect transistor (FET) on the seed material; and removing the seed material.

Abstract: A liquid ejection head substrate including a silicon substrate having a liquid supply port as hollow and slots as through holes connecting the hollow and a liquid channel arranged opposite sides of the substrate. The method includes etching the substrate to form the hollow; forming a first resist on the hollow; etching the first resist on the bottom of the hollow under conditions of securing an equal etching rate to both the silicon substrate and the first resist; forming a second resist on the hollow; patterning the second resist into an etching mask; and etching the substrate using the etching mask to form the through holes.

Abstract: Representative implementations of devices and techniques provide heating for a semiconductor device. A heating element is arranged to be located proximate to the semiconductor device and to increase a temperature of at least a portion of the semiconductor device during operation of the semiconductor device.

Abstract: A structure (46) for holding an integrated circuit (IC) die (50) during packing includes a flexible structurally reinforced silicone adhesive film (22) and a mold frame (44). The mold frame (44) adheres to an adhesive side (38) of the film (22). A method (20) of packaging the IC die (50) includes placing the IC die (50) on the adhesive film (22) with its active surface (52) and bond pads (54) in contact with an adhesive side (38) of the film (22). A molding compound (58) is dispensed over the IC die, and the IC die (50) is encapsulated using compression molding to form a compression molded encapsulant layer (70). IC die (50) is subsequently released from the film (22) as a panel (72) of IC dies (50).

Abstract: A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by natural oxidation and containing an oxygen surfactant layer to form a more uniform MgO layer and lower breakdown distribution percent. A CoFeB/NCC/CoFeB composite free layer with a middle nanocurrent channel layer minimizes Jc0 while enabling thermal stability, write voltage, read voltage, and Hc values that satisfy 64 Mb design requirements. The NCC layer has RM grains in an insulator matrix where R is Co, Fe, or Ni, and M is a metal such as Si or Al. NCC thickness is maintained around the minimum RM grain size to avoid RM granules not having sufficient diameter to bridge the distance between upper and lower CoFeB layers. A second NCC layer and third CoFeB layer may be included in the free layer or a second NCC layer may be inserted below the Ru capping layer.

Abstract: An improved method for singulation of compound electronic devices is presented. Compound electronic devices are manufactured by combining two or more substrates into an assembly containing multiple devices. Presented are methods for singulation of compound electronic devices using laser processing. The methods presented provide fewer defects such as cracking or chipping of the substrates while minimizing the width of the kerf and maintaining system throughput.

Abstract: A composite material includes a carbon nanotube, and plural pentacene molecules bonded to the carbon nanotube. A method of forming the composite layer, includes depositing on a substrate a dispersion of soluble pentacene precursor and carbon nanotubes, heating the dispersion to remove solvent from the dispersion, heating the substrate to convert the pentacene precursor to pentacene and form the carbon nanotube-pentacene composite layer.

Abstract: A method for forming a fine pattern having a variable width by simultaneously using an optimal focused electron beam and a defocused electron beam in a light exposure process Includes, after forming a first film on a substrate, forming a first film pattern including a first level area and a second level area having different distances from the substrate by changing a profile of an upper surface of the first film. A photoresist film having a first area covering the first level area and a second area covering the second level area is formed. To simultaneously light-expose the first area and the second area with the same width, a light exposure condition, in which an optimal focused electron beam is eradiated on the first area and a defocused electron beam is eradiated on the second area, is applied.

Abstract: A light emitting device (LED) employs one or more conductive multilayer reflector (CMR) structures. Each CMR is located between the light emitting region and a metal electrical contact region, thereby acting as low-loss, high-reflectivity region that masks the lossy metal contact regions away from the trapped waveguide modes. Improved optical light extraction via an upper surface is thereby achieved and a vertical conduction path is provided for current spreading in the device. In an example vertical, flip-chip type device, a CMR is employed between the metal bottom contact and the p-GaN flip chip layer. A complete light emitting module comprises the LED and encapsulant layers with a phosphor. Also provided is a method of manufacture of the LED and the module.

Abstract: A method for fabricating a semiconductor device is described. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is formed over the metal silicide layer.

Abstract: A step of forming wiring using first solution ejection means for ejecting a conductive material, a step of forming a resist mask on the wiring using second solution ejection means, and a step of etching the wiring using an atmospheric-pressure plasma device having linear plasma generation means or an atmospheric-pressure plasma device having a plurality of linearly-arranged plasma-generation-means using the resist mask as a mask are included.

Abstract: Fabricating a printhead includes providing a silicon wafer including first and second surfaces and a nozzle membrane layer on the first surface of the silicon wafer. The silicon wafer is sized to a thickness ranging from 10 to 250 microns. A plurality of chambers is defined on the second surface of the silicon wafer by depositing and patterning a mask on the second surface of the silicon wafer. The plurality of chambers is formed in the silicon wafer by etching portions of the silicon wafer that are exposed by the mask. A second wafer, permanently bonded to the second surface of the silicon wafer, includes a material property that is compatible with a material property of the silicon wafer. A preformed fluid channel of the second wafer is in fluid communication with the plurality of chambers of the silicon wafer after permanent bonding of the wafers.

Abstract: The present invention provides a method for manufacturing an electrode of a dye-sensitized solar cell using an inkjet printing process, an electrode formed thereby, and a dye-sensitized solar cell having the electrode. According to the method, a metal electrode is formed by jetting an ink solution containing nano metal powder on a transparent substrate or a transparent substrate in which a barrier layer is deposited to improve coating performance of a transparent conductive layer. A transparent conductive layer is formed on the transparent substrate on which the metal electrode is formed. The transparent conductive layer protects the metal electrode from liquid electrolyte.

Abstract: Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. A transistor in the pixel sensor cell has a gate structure that includes a gate dielectric with a thick region and a thin region. A gate electrode of the gate structure is formed on the thick region of the gate dielectric and the thin region of the gate dielectric. The thick region of the gate dielectric and the thin region of the gate dielectric provide the transistor with an asymmetric threshold voltage.

Abstract: A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer.

Abstract: A semiconductor device is made by forming solder bumps over a copper carrier. Solder capture indentations are formed in the copper carrier to receive the solder bumps. A semiconductor die is mounted to the copper carrier using a die attach adhesive. The semiconductor die has contact pads formed over its active surface. An encapsulant is deposited over the copper carrier, solder bumps, and semiconductor die. A portion of the encapsulant is removed to expose the solder bumps and contact pads. A conductive layer is formed over the encapsulant to connect the solder bumps and contact pads. The conductive layer operates as a redistribution layer to route electrical signals from the solder bumps to the contact pads. The copper carrier is removed. An insulating layer is formed over the conductive layer and encapsulant. A plurality of semiconductor devices can be stacked and electrically connected through the solder bumps.

Abstract: In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured.

Abstract: The following processes are included: preparing a substrate; forming a first gate electrode above the substrate; forming a second gate electrode above the substrate and adjacent to the first gate electrode; forming a gate insulating film on the first gate electrode and the second gate electrode; forming, on the gate insulating film, a noncrystalline semiconductor film at least in a first region above the first gate electrode and a second region above the second gate electrode; irradiating the noncrystalline semiconductor film a laser beam having continuous convex light intensity distributions; and forming a first source electrode and a first drain electrode above the first region, and a second source electrode and a second drain electrode above the second region. In the irradiating, when irradiating the first region with an inner region of the laser beam, the second region is irradiated with an outer region of the laser beam.