Abstract: Using compression molding to form lenses over LED arrays on a metal core printed circuit board leaves a flash layer of silicone covering the contact pads that are later required to connect the arrays to power. A method for removing the flash layer involves blasting particles of sodium bicarbonate at the flash layer. A nozzle is positioned within thirty millimeters of the top surface of the flash layer. The stream of air that exits from the nozzle is directed towards the top surface at an angle between five and thirty degrees away from normal to the top surface. The particles of sodium bicarbonate are added to the stream of air and then collide into the top surface of the silicone flash layer until the flash layer laterally above the contact pads is removed. The edge of silicone around the cleaned contact pad thereafter contains a trace amount of sodium bicarbonate.

Abstract: Placement of an encapsulation material adhesion promoter onto a semiconductor device leadframe can be performed through the use of an offset printing apparatus such as a rotogravure printing apparatus or a tampoprint printing apparatus. This can provide accurate and low-cost placement of the adhesion promoter.

Abstract: The present disclosures relates to a method for producing ultrathin chip stacks and chip stacks. Generally, a plurality of first semiconductor chips is formed in a wafer. A second semiconductor chip is applied to each of the plurality of first semiconductor chips via a connection layer and a stabilization layer is applied to fill in the interspace between each of the second semiconductor chips. The wafer, semiconductor chip, and stabilization layer are thinned and the wafer is sawed to produce a plurality of singulated chip stacks.

Abstract: A method for processing a silicon substrate includes providing a combination of a first silicon substrate, a second silicon substrate, and an intermediate layer including a plurality of recessed portions, which is provided between the first silicon substrate and the second silicon substrate, forming a first through hole that goes through the first silicon substrate by executing etching of the first silicon substrate on a surface of the first silicon substrate opposite to a bonding surface with the intermediate layer by using a first mask, and exposing a portion of the intermediate layer corresponding to the plurality of recessed portions of the intermediate layer, forming a plurality of openings on the intermediate layer by removing a portion constituting a bottom of the plurality of recessed portions, and forming a second through hole that goes through the second silicon substrate by executing second etching of the second silicon substrate by using the intermediate layer on which the plurality of openings ar

Abstract: The present invention generally relates to methods for producing MEMS or NEMS devices and the devices themselves. A thin layer of a material having a lower recombination coefficient as compared to the cantilever structure may be deposited over the cantilever structure, the RF electrode and the pull-off electrode. The thin layer permits the etching gas introduced to the cavity to decrease the overall etchant recombination rate within the cavity and thus, increase the etching rate of the sacrificial material within the cavity. The etchant itself may be introduced through an opening in the encapsulating layer that is linearly aligned with the anchor portion of the cantilever structure so that the topmost layer of sacrificial material is etched first. Thereafter, sealing material may seal the cavity and extend into the cavity all the way to the anchor portion to provide additional strength to the anchor portion.

Abstract: According to a method for transferring a functional region, at least part of functional regions on separation layers arranged on a first substrate is transferred onto a second substrate, the separation layers being capable of being brought into a separable state by treatment. In a first bonding step, the first substrate is bonded to the second substrate with a dry film resist arranged between the second substrate and the at least part of the functional regions above the first substrate. In an exposure step, at least part of the dry film resist is exposed. In a patterning step, the exposed dry film resist is patterned.

Abstract: A method and apparatus for oxidizing materials used in semiconductor integrated circuits, for example, for oxidizing silicon to form a dielectric gate. An ozonator is capable of producing a stream of least 70% ozone. The ozone passes into an RTP chamber through a water-cooled injector projecting into the chamber. Other gases such as hydrogen to increase oxidation rate, diluent gas such as nitrogen or O2, enter the chamber through another inlet. The chamber is maintained at a low pressure below 20 Torr and the substrate is advantageously maintained at a temperature less than 800° C. Alternatively, the oxidation may be performed in an LPCVD chamber including a pedestal heater and a showerhead gas injector in opposition to the pedestal.

Abstract: The present invention is a method for producing a group III nitride semiconductor layer in which a single crystal group III nitride semiconductor layer (103) is formed on a substrate (101), the method including: a substrate processing step of forming, on the (0001) C-plane of the substrate (101), a plurality of convex parts (12) of surfaces (12c) not parallel to the C-plane, to thereby form, on the substrate, an upper surface (10) that is composed of the convex parts (12) and a flat surface (11) of the C-plane; and an epitaxial step of epitaxially growing the group III nitride semiconductor layer (103) on the upper surface (10), to thereby embed the convex parts (12) in the group III nitride semiconductor layer (103).

Abstract: A metallic silicide resistive thermal sensor has a body, a conductive wire and multiple electrodes. The body has multiple etching windows formed on the body and a cavity formed under the etching windows. The etching windows separate the body into a suspended part and multiple connection parts. The conductive wire is formed on the suspended part and the connection parts and is made of metallic silicide. The electrodes are formed on the body and are electrically connected to the conductive wire. The metallic silicide is compatible for common CMOS manufacturing processes. The cost for manufacturing the resistive thermal sensor decreases. The metallic silicon is stable at high temperature. Therefore, the performance of the resistive thermal sensor in accordance with the present invention is improved.

Abstract: A semiconductor device that prevents the leaning of storage node when forming a capacitor having high capacitance includes a plurality of cylinder-shaped storage nodes formed over a semiconductor substrate; and support patterns formed to fix the storage nodes in the form of an ‘L’ or a ‘+’ when viewed from the top. This semiconductor device having support patterns in the form of an ‘L’ or a ‘+’ reduces stress on the storage nodes when subsequently forming a dielectric layer and plate nodes that prevents the capacitors from leaking.

Abstract: Assuming that r (m) represents the radius of a GaN substrate, t1 (m) represents the thickness of the GaN substrate, h1 (m) represents a warp of the GaN substrate before formation of an epitaxialwafer, t2 (m) represents the thickness of an AlxGa(1-X)N layer, h2 (m) represents a warp of the epitaxialwafer, a1 represents the lattice constant of GaN and a2 represents the lattice constant of AlN, the value t1 found by the following expression is decided as the minimum thickness (t1) of the GaN substrate: (1.5×1011×t13+1.2×1011×t23)×{1/(1.5×1011×t1)+1/(1.2×1011×t2)}/{15.96×x×(1?a2/a1)}×(t1+t2)+(t1×t2)/{5.32×x×(1?a2/a1)}?(r2+h2)/2h=0 A GaN substrate having a thickness of at least this minimum thickness (t1) and less than 400 ?m is formed.

Abstract: A method of reducing parasitic capacitance of liquid crystal display device is disclosed where the liquid crystal display device comprises a first substrate, a second substrate and a liquid crystal layer. The first substrate comprises data lines and a first transparent electrode, and the second substrate is provided with a second transparent electrode. The method comprises the following steps: A. by means of photolithography and patterning, the second transparent electrode is separated into a primary second transparent electrode and a secondary second transparent electrode; B. offering the secondary second transparent electrode the same signal to the relevant data line. The invention further relates to a liquid crystal display device and the parasitic capacitance in the data lines of the liquid crystal display device can be diminished.

Abstract: Front-side integrated parts of integrated-circuit chips are produced at locations on a substrate wafer. The front-side parts have a front side. A support wafer having a bearing side is mounted with the bearing side on top of said front-side parts. The support wafer includes at least one weak surface layer. This weak surface layer is attached to the substrate wafer using a retaining adhesive. In one implementation, the weak surface layer is attached to a front surface of the wafer. In another implementation, the weak surface layer is attached to a peripheral edge of the wafer. After attaching the support wafer, back-side integrated parts of the integrated-circuit chips are produced on the substrate wafer. The weak surface layer is then destroyed so as to demount the support wafer from the substrate wafer.

Abstract: A color unit is disclosed in which is included in an imaging device. The color unit includes; a first p-type electrode layer disposed on a light receiving side of the color unit, and including a light-absorptive organic material which selectively absorbs a wavelength other than a desired wavelength in a visible light band of the electromagnetic spectrum, a second p-type electrode layer disposed under the first p-type electrode layer and including a light-absorptive organic material which absorbs a desired wavelength and an n-type electrode layer disposed under the second p-type electrode layer and including an organic material, wherein photoelectric conversion is performed through a p-n junction between the second p-type electrode layer and the n-type electrode layer and light of the desired wavelength is converted into electrical current.

Abstract: Memory devices based on tungsten-oxide memory regions are described, along with methods for manufacturing and methods for programming such devices. The tungsten-oxide memory region can be formed by oxidation of tungsten material using a non-critical mask, or even no mask at all in some embodiments. A memory device described herein includes a bottom electrode and a memory element on the bottom electrode. The memory element comprises at least one tungsten-oxygen compound and is programmable to at least two resistance states. A top electrode comprising a barrier material is on the memory element, the barrier material preventing movement of metal-ions from the top electrode into the memory element.

Abstract: Provided are transistor devices such as logic gates that are capable of associating a computational state and or performing logic operations with detectable electronic spin state and or magnetic state. Methods of operating transistor devices employing magnetic states are provided. Devices comprise input and output structures and magnetic films capable of being converted between magnetic states.

Abstract: An exemplary method for manufacturing LEDs includes steps: providing a substrate and an epitaxial layer formed on the substrate; etching the epitaxial layer along a transverse direction thereof to divide the epitaxial layer into separated LED chips, and a groove defined between each two adjacent LED chips; providing insulating poles and inserting the insulating poles in the grooves; printing a solder paste layer on a top surface of each LED chip away from the substrate; reflow soldering the LED chips to make the solder paste layers mounted on the LED chips become solder balls; releasing the substrate from the LED chips; etching the insulating poles until the insulating poles are totally removed and the LED chips are separated from each other; and providing metallic plates and respectively soldering the metallic plates on the solder balls of the LED chips.

Abstract: The present invention includes a liquid crystal display device with an oxide film having high adhesiveness to a semiconductor layer or a pixel electrode to thereby prevent oxidation of a wiring material or the like, and includes a source electrode and a drain electrode having high conductivity, and a manufacturing method therefor. In one embodiment of the present invention, a liquid crystal display device has a TFT electrode of a TFT substrate, wherein a source electrode or a drain electrode includes a layer of mainly copper and an oxide covering an outer part of the layer. Further, in the present invention, the semiconductor layer or the pixel electrode and said source electrode or the drain electrode are in ohmic contact in the TFT electrode.

Abstract: The present invention relates to a resistive random access memory using the rare earth scandate thin film as the storage medium, comprising a substrate, an insulation layer, a first electrode layer, a resistive memory layer, and a second electrode layer. In the present invention, it uses an amorphous rare earth scandate layer as the resistive memory layer of the resistive random access memory. Therefore, the resistive random access memory using the rare earth scandate thin film as the storage medium having advantages of low operation voltage and low power consumption can easily be manufactured without using any forming process or thermal annealing process. Moreover, through the characteristics of unipolar resistance switching behavior revealed by the amorphous rare earth scandate layer, the resistive random access memory using rare earth scandate thin film as the storage medium is able to perform a high resistance state and a low resistance state.

Abstract: Forming conformal platinum-zinc films for semiconductor devices is described. In one example, a conformal film is formed by heating a substrate in a reaction chamber, exposing a desired region of the substrate to a precursor that contains platinum, purging excess precursor from the chamber, exposing the desired region of the substrate to a co-reactant containing zinc to cause a reaction between the precursor and the co-reactant to form a platinum zinc film on the desired region, and purging the chamber of excess reaction by-products.

Abstract: One embodiment of the present invention provides a method for fabricating an InGaAlN light-emitting semiconductor structure. During the fabrication process, at least one single-crystal sacrificial layer is deposited on the surface of a base substrate to form a combined substrate, wherein the single-crystal sacrificial layer is lattice-matched with InGaAlN, and wherein the single crystal layer forms a sacrificial layer. Next, the InGaAlN light-emitting semiconductor structure is fabricated on the combined substrate. The InGaAlN structure fabricated on the combined substrate is then transferred to a support substrate, thereby facilitating a vertical electrode configuration. Transferring the InGaAlN structure involves etching the single-crystal sacrificial layer with a chemical etchant. Furthermore, the InGaAlN and the base substrate are resistant to the chemical etchant. The base substrate can be reused after the InGaAlN structure is transferred.

Abstract: An optoelectronic device article comprises a substrate containing at least one electrically conductive microvia, at least one emitter diode and at least one ESD diode, optionally formed in situ, disposed in or on the substrate, and an electrically conductive path between the foregoing elements. A reflector cavity may be defined in the substrate for receiving the emitter diode(s), with retention elements on the substrate used to retain a lens material. High flux density and high emitter diode spatial density may be attained. Thermal sensors, radiation sensors, and integral heat spreaders comprising one or more protruding fins may be integrated into the article.

Abstract: An optical device wafer processing method including a laser processed groove forming step of applying a laser beam for performing ablation to the front side or back side of a substrate of an optical device wafer along streets, thereby forming a laser processed groove as a break start point on the front side or back side of the substrate along each street, and a wafer dividing step of applying an external force to the optical device wafer after performing the laser processed groove forming step to thereby break the wafer along each laser processed groove, thereby dividing the wafer into individual optical devices. In performing the laser processed groove forming step, an etching gas atmosphere for etching a modified substance produced by applying the laser beam to the substrate is generated, whereby an etching gas in the etching gas atmosphere is converted into a plasma by the application of the laser beam to thereby etch away the modified substance.

Abstract: A shielded embedded electronic component substrate includes a core dielectric layer having a die opening. An electrically conductive die shield lines the die opening. An electronic component is mounted within the die opening and to the die shield, where the die shield shields the electronic component. By mounting the electronic component within the die opening, the shielded embedded electronic component substrate is made relatively thin. Further, heat generated by the electronic component is dissipated to the die shield and to the ambient environment. Accordingly, the shielded embedded electronic component substrate is well suited for use when the electronic component generates a significant amount of heat, e.g., in high power applications.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.

Abstract: Example methods and example embodiments include methods of fabricating semiconductor devices and semiconductor devices fabricated by the same. Example fabricating methods include forming a first nanowire, oxidizing the first nanowire to form a first nanostructure including a first insulator and a second nanowire, and oxidizing the second nanowire to form a second nanostructure including a second insulator and nanodots. Example semiconductor devices include nanostructures including nanodots and nanostructures providing storage nodes in memory devices.

Abstract: A convex part formation method of forming a convex part in parallel with a <110> direction of a backing on the backing having a {100} face as the top surface thereof, includes: (a) forming a mask layer in parallel with the <110> direction on the backing; (b) etch the backing so as to form a convex-part upper layer whose sectional shape on a cutting plane corresponding to a {110} face is an isosceles trapezoid, the base of which is longer than the upper side thereof, and the side surface of which has an inclination of ?U; and (c) further etching the backing so as to form a convex-part lower layer whose sectional shape on the cutting plane corresponding to the {110} face is an isosceles trapezoid, the base of which is longer than the upper side thereof, and the side surface of which has an inclination of ?D (where ?D??U).

Abstract: An alteration method of a titanium nitride film, comprising exposing a titanium nitride film formed on a semiconductor substrate to plasma obtained by exciting a process gas that includes noble gas or nitrogen and excludes oxygen, thereby increasing a specific resistance of the titanium nitride film.

Abstract: A micro electrical mechanical system includes a membrane structure and a backplate structure. The backplate structure includes a backplate material and at least one pre-tensioning element mechanically connected to the backplate material. The at least one pre-tensioning element causes a mechanical tension on the backplate material for a bending deflection of the backplate structure in a direction away from the membrane structure.

Abstract: A method of forming a phosphor coating layer on a light emitting diode (LED) chip using electrophoresis includes separating phosphor particles in a suspension according to a particle size, and coating the phosphor particles on a surface of the LED chip by sequentially depositing the separated phosphor particles on the surface of the LED chip according to the particle size. An apparatus to form a phosphor coating layer on an LED chip includes an electrophoresis bath to accommodate a suspension containing phosphor particles separated into layers according to a particle size, and electrodes disposed inside the electrophoresis bath. The electrodes may include a cathode electrode on which the LED chip may be arranged, and an anode electrode.

Abstract: The present sensor chip comprises a substrate. A plurality of electrode elements is arranged at a first level on the substrate with at least one gap between neighbouring electrode elements. A metal structure is arranged at a second level on the substrate, wherein the second level is different from the first level. The metal structure at least extends over an area of the second level that is defined by a projection of the at least one gap towards the second level.

Abstract: A method of manufacture of an integrated circuit package system includes: providing a penetrable layer; partially immersing leads in the penetrable layer; coupling an integrated circuit die to the leads; molding a package body on the integrated circuit die, the leads, and the penetrable layer; and exposing stand-off leads from the leads by removing the penetrable layer including establishing a stand-off height between a bottom of the package body and the bottom of the stand-off leads.

Abstract: A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer and a second electrically conductive material layer. The first electrically conductive material layer has a thickness. A resist material layer is deposited over the second electrically conductive material layer. The resist material layer is patterned to expose a portion of the second electrically conductive material layer. Some of the second electrically conductive material layer is removed to expose a portion of the first electrically conductive material layer. The second electrically conductive material layer is caused to overhang the first electrically conductive material layer by removing some of the first electrically conductive material layer.

Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.

Abstract: A method for manufacturing a phase change memory includes forming a phase change memory cell by forming a phase change layer between two switching layers. The phase change layer is separated from thermal heat sinks, such as the bitline or wordline, by the switching layers.

Abstract: In one embodiment, a method of forming a MEMS device includes providing a substrate, forming a sacrificial layer above the substrate layer, forming a silicon based working portion on the sacrificial layer, releasing the silicon based working portion from the sacrificial layer such that the working portion includes at least one exposed outer surface, forming a first layer of silicide forming metal on the at least one exposed outer surface of the silicon based working portion, and forming a first silicide layer with the first layer of silicide forming metal.

Abstract: A light emitting system is disclosed. The system comprises an active region having a stack of bilayer quantum well structures separated from each other by barrier layers. Each bilayer quantum well structure is formed of a first layer made of a first semiconductor alloy for electron confinement and a second layer made of a second semiconductor alloy for hole confinement, wherein a thickness and composition of each layer is such that a characteristic hole confinement energy of the bilayer quantum well structure is at least 200 meV.

Abstract: A system and method for preventing defaults during singulation is presented. An embodiment comprises a dummy metal structure located in the scribe region. The dummy metal structure comprises a series of alternating dummy lines that are connected through dummy vias. The dummy lines are offset from dummy lines in adjacent metal layers. Additionally, the dummy lines and dummy vias in the upper layers of the scribe line may be formed with larger dimensions than the dummy lines and dummy vias located in the lower layers.

Abstract: A semiconductor device has a carrier. A first semiconductor die is mounted to the carrier with an active surface of the first semiconductor die oriented toward the carrier. A dam structure is formed on the carrier and around the first semiconductor die by depositing dam material on the carrier with screen printing, electrolytic plating, electroless plating, or spray coating. An encapsulant is deposited over the carrier and around the first semiconductor die. The encapsulant has a coefficient of thermal expansion (CTE) that corresponds to a CTE of the dam material. The CTE of the dam material is equal to or less than the CTE of the encapsulant. The carrier is removed to expose the active surface of the first semiconductor die with the dam structure stiffening a periphery of the first semiconductor die. The semiconductor device is singulated through the dam structure.

Abstract: A liquid ejection head substrate including a silicon substrate having a liquid supply port as hollow and slots as through holes connecting the hollow and a liquid channel arranged opposite sides of the substrate. The method includes etching the substrate to form the hollow; forming a first resist on the hollow; etching the first resist on the bottom of the hollow under conditions of securing an equal etching rate to both the silicon substrate and the first resist; forming a second resist on the hollow; patterning the second resist into an etching mask; and etching the substrate using the etching mask to form the through holes.

Abstract: A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate.

Abstract: Microsensors that include an integrated thermal energy source and an integrated temperature sensor are capable of providing localized heating and temperature control of individual sensing regions within the microsensor. Localized temperature control allows analyte detection to be carried out at the same temperatures or substantially the same temperatures at which the sensor is calibrated. By carrying out the sensing near the calibration temperature, more accurate results can be obtained. In addition, the temperature of the sensing region can be controlled so that chemical reactions involving the analyte in the sensing region occur near their peak reaction rate. Carrying out the sensing near the peak reaction rate improves the sensitivity of the sensor which is important as sensor dimensions decrease and the magnitude of the generated signals decreases.

Abstract: A method of manufacturing an image sensor having a plurality of pixels, each pixel having a photoelectric converter including an accumulation region, and a transfer gate, the accumulation region extending under a corresponding transfer gate, the plurality of pixels including a plurality of pixel groups, each pixel group including N adjacent pixels, and the channels of the N adjacent pixels, in each pixel group, being configured to transfer the charges of the N adjacent pixels away from each other, the method comprising a step of forming a resist pattern having one opening corresponding to each pixel group, and a step of forming a charge accumulation region for each of the N adjacent pixels by implanting ions into a substrate through the one opening of the resist pattern along N ion implantation directions so as to implant the ions under the transfer gate of each of the N adjacent pixels.

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.

Abstract: Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided.

Abstract: A MEMS may integrate movable MEMS parts, such as mechanical elements, flexible membranes, and sensors, with the low-cost device package, leaving the electronics and signal-processing parts in the integrated circuitry of the semiconductor chip. The package may be a leadframe-based plastic molded body having an opening through the thickness of the body. The movable part may be anchored in the body and extend at least partially across the opening. The chip may be flip-assembled to the leads to span across the foil, and may be separated from the foil by a gap. The leadframe may be a prefabricated piece part, or may be fabricated in a process flow with metal deposition on a sacrificial carrier and patterning of the metal layer. The resulting leadframe may be flat or may have an offset structure useful for stacked package-on-package devices.

Abstract: A processing method of a semiconductor wafer is provided. The method comprising the steps of: removing at least part of oxide film from a surface of the semiconductor wafer; removing liquid from the surface; and providing at least partial oxide film on the surface by applying an oxidizing gas wherein a gas flow of the oxidizing gas and/or an ambient gas involved by the oxidizing gas is characterized by an unsaturated vapor pressure of the liquid such that the liquid on the surface vaporizes. The above-described steps are conducted in this order.

Abstract: An MEMS component including a monolithically integrated electronic component with a multi-plane conductor track layer stack which is arranged on a substrate and into which is integrated a cantilevered elastically movable metallic actuator which is arranged in the multi-plane conductor track layer stack at the level of a conductor track plane and is connected by via contacts to conductor track planes which are arranged thereabove or therebeneath and which apart from an opening in the region of the actuator are separated from the conductor track plane of the actuator by a respective intermediate plane insulator layer, wherein the actuator is formed from a metallically conductive layer or layer combination which is resistant to corrosive liquids or gases and which contains titanium nitride or consists of titanium nitride.

Abstract: Conductive layers having knots are adjacently formed with uniform distance therebetween. Droplets of the conductive layers are discharged to stagger centers of the droplets in a length direction of wirings so that the centers of the discharged droplets are not on the same line in a line width direction between the adjacent conductive layers. Since the centers of the droplets are staggered, parts of the conductive layers each having a widest line width (the widest width of knot) are not connected to each other, and the conductive layers can be formed adjacently with a shorter distance therebetween.

Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.