Abstract: The present invention provides a TFT-LCD array substrate having a gate-line metal layer, a data-line metal layer crossing the gate-line metal layer and a plurality of layers covering a periphery of the gate-line metal layer and the data-line metal layer; the gate-line metal layer has first gate lines and second gate lines parallel and alternately arranged, the date-line metal layer has first data lines and second data lines parallel and alternately arranged; the first gate line and the second gate line are electrically connected; the first data line and the second data line are electrically connected. The present invention further provides a manufacturing method of the TFT-LCD array substrate. Implementing the TFT-LCD array substrate and the manufacturing method can reduce the occurrence of line-broken in the active array of TFT-LCD, increase the aperture ratio of the product and enhance yield rate of the products.

Abstract: Semiconductor trench inductor and transformer structures are provided, which include thin film conductive layers and magnetic layers formed within trenches etched in semiconductor substrates. Semiconductor trench devices effectively provide vertical oriented inductor and transformer structures whereby conductive coils and magnetic layers are vertically oriented on edge within trenches, thereby providing a space-saving compact design, and which allows the conductive layers within the trench to be enclosed by magnetic material, thereby providing a density of magnetic material that increases the storable energy density.

Abstract: The present invention relates to a method for producing silicon waveguides on non-SOI substrate (non-silicon-on-insulator substrate), and particularly relates to a method for producing silicon waveguides on silicon substrate with a laser. This method includes the following steps: (1) forming a ridge structure with high aspect ratio on a non-SOI substrate; (2) melting and reshaping the ridge structure by laser illumination for forming a structure having broad upper part and narrow lower part; and (3) oxidizing the structure having broad upper part and narrow lower part to form a silicon waveguide.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits. In one embodiment, the material that encapsulates the mechanical structures is, for example, silicon (polycrystalline, amorphous or porous, whether doped or undoped), silicon carbide, silicon-germanium, germanium, or gallium-arsenide.

Abstract: A quantum bit computing architecture includes a plurality of single spin memory donor atoms embedded in a semiconductor layer, a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, wherein a first voltage applied across at least one pair of the aligned quantum dot and donor atom controls a donor-quantum dot coupling. A method of performing quantum computing in a scalable architecture quantum computing apparatus includes arranging a pattern of single spin memory donor atoms in a semiconductor layer, forming a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, applying a first voltage across at least one aligned pair of a quantum dot and donor atom to control a donor-quantum dot coupling, and applying a second voltage between one or more quantum dots to control a Heisenberg exchange J coupling between quantum dots and to cause transport of a single spin polarized electron between quantum dots.

Abstract: Capacitive micromachined ultrasonic transducers (CMUTs) in permanent contact mode are provided. Such a CMUT always has its plate in contact with the substrate, even for zero applied electrical bias. This contact is provided by the pressure difference between the environment, and the pressure of the evacuated region between the CMUT plate and substrate. Due to this permanent contact, the electric field in the gap for a given DC bias voltage will be larger, which provides improved coupling efficiency at lower DC bias voltages. Furthermore, in an environment with high and varying pressure, the plate will not shift between the conventional mode and the collapsed mode, but will only be pushed down with varying contact radius. In some embodiments, an electrode shaped as an annulus is employed, so that only the active vibrating part of the CMUT plate sees the applied DC and AC voltages.

Abstract: A sensor having a monolithically integrated structure for detecting thermal radiation includes: a carrier substrate, a cavity, and at least one sensor element for detecting thermal radiation. Incident thermal radiation strikes the sensor element via the carrier substrate. The sensor element is suspended in the cavity by a suspension.

Abstract: A device includes a micro-electro-mechanical system (MEMS) device, which includes a movable element and a fixed element. The movable element and the fixed element form two capacitor plates of a capacitor, with an air-gap between the movable element and the fixed element acting as a capacitor insulator of the capacitor. At least one of the movable element and the fixed element has a rugged surface.

Abstract: A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of the substrate to enhance carrier mobility and upgrade the device performance. The improved formation method is achieved by providing a treatment to redistribute at least a portion of the corner in the cavity.

Abstract: There are provided a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a substrate having a ground electrode formed on one surface thereof; at least one electronic component mounted on one surface of the substrate; an insulation layer including an exposed part exposing the ground electrode and a cover part covering the electronic component; and a shielding layer electrically connected to the ground electrode and covering the insulation layer.

Abstract: Methods and apparatus teach a substrate wafer having a plurality of plugs configured there within. The method also includes depositing and patterning a layer of a second metallic material over the substrate wafer, providing a layer of a dielectric material of a predetermined thickness over the patterned layer of the second metallic material, and conducting chemical mechanical polishing of the layer of the dielectric material to form a planarized top surface while exposing the patterned layer of the second metallic material. The method further includes cleaning the planarized top surface, depositing and patterning a resistor film over the planarized top surface, depositing one or more blanket films over the patterned resistor film, and patterning and etching the one or more blanket films. Further disclosed are planar heater structures and additional methods for fabricating the planar heater structures.

Abstract: A method for manufacturing a thermoelectrical device includes providing a substrate and also forming at least one deep trench into the substrate. The method further includes forming at least one thermocouple which comprises two conducting paths, wherein a first conducting path comprises a first conductive material and a second conducting path comprises a second conductive material, such that at least the first conducting path is embedded in the deep trench of the substrate.

Abstract: The present approach involves a radiation detector module with increased quantum efficiency and methods of fabricating the radiation detector module. The module includes a scintillator substrate and a photodetector fabricated on the scintillator substrate. The photodetector includes an anode, active organic elements, and a cathode. The module also includes a pixel element array disposed over the photodetector. During imaging, radiation attenuated by an object to be imaged may propagate through the pixel element array and through the layers of the photodetector to be absorbed by the scintillator which in response emits optical photons. The photodetector may absorb the photons and generate charge with improved quantum efficiency, as the photons may not be obscured by the cathode or other layers of the module. Further, the module may include reflective materials in the cathode and at the pixel element array to direct optical photons towards the active organic elements.

Abstract: An alteration method of a titanium nitride film, comprising exposing a titanium nitride film formed on a semiconductor substrate to plasma obtained by exciting a process gas that includes noble gas or nitrogen and excludes oxygen, thereby increasing a specific resistance of the titanium nitride film.

Abstract: A method of fabricating a MEMS composite transducer includes providing a substrate having a first surface and a second surface opposite the first surface. A transducing material is deposited over the first surface of the substrate. The transducing material is patterned by retaining transducing material in a first region and removing transducing material in a second region. A polymer layer is deposited over the first region and the second region. The polymer layer is patterned by retaining polymer in a third region and removing polymer in a fourth region. A first portion of the third region is coincident with a portion of the first region and a second portion of the third region is coincident with a portion of the second region. A cavity is etched from the second surface to the first surface of the substrate.

Abstract: A flexible wiring circuit board has a second terminal section bonded and electrically connected to a first terminal section of a wiring circuit board of a discharge die. A drive signal is inputted to the first terminal section through the second terminal section, and then sent to a driver IC. The driver IC drives a piezoelectric element in accordance with the drive signal through a printed wiring pattern. Thereby, ink is discharged from an ink discharge opening. A copper ion diffusion inhibiting film is formed on a surface of a copper wiring member of the second terminal section on contact with a process liquid containing at least one of 1, 2, 3 triazole and 1, 2, 4 triazole. This inhibits diffusion of copper ions and copper ion migration resulting therefrom. Thus, malfunction due to the copper ion migration is inhibited.

Abstract: A semiconductor device according to the present embodiment comprises a lower electrode provided above a semiconductor substrate and made of metal, an upper electrode provided above the lower electrode and made of metal, and a crystal layer provided between the lower electrode and the upper electrode. A thickness of each of the lower electrode and the upper electrode is smaller than a thickness of a skin layer deriving from a skin effect corresponding to a frequency of a microwave used to crystallize the crystal layer.

Abstract: A device is provided which includes a transparent substrate. An opaque layer is disposed on the transparent substrate. A conductive layer disposed on the opaque layer. The opaque layer and the conductive layer form a handling layer, which may be used to detect and/or align the transparent wafer during fabrication processes. In an embodiment, the conductive layer includes a highly-doped silicon layer. In an embodiment, the opaque layer includes a metal. In embodiment, the device may include a MEMs device.

Abstract: A TFT-LCD array substrate and a manufacturing method thereof. The array substrate comprises a gate line, a data line, and a pixel electrode, and the pixel electrode is disposed in a pixel region defined by the intersection between the gate line and the data line. In the pixel region, a partition groove for forming a pixel electrode pattern is provided at the periphery of the pixel electrode. This structure is helpful to form a pixel electrode pattern by a lift-off process, which significantly reduces the production cost and improves the production yield.

Abstract: An apparatus and associated method for a non-volatile memory cell with a phonon-blocking insulating layer. In accordance with various embodiments, a magnetic stack has a tunnel junction, ferromagnetic free layer, pinned layer, and an insulating layer that is constructed of an electrically and thermally insulative material that blocks phonons while allowing electrical transmission through at least one conductive feature.

Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B). Annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer. Cooling down of the STTMRAM element to a second temperature that is lower than the first temperature is performed and a third free sub-layer is directly deposited on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer.

Abstract: In an acoustic sensor, a conductive vibrating membrane and a fixed electrode plate are disposed above a silicon substrate with an air gap provided therebetween, and the substrate has an impurity added to a surface thereof. A microphone includes an acoustic transducer; and an acquiring section that acquires a change in pressure as detected by the acoustic transducer. A method for manufacturing an acoustic transducer including a semiconductor substrate, a vibrating membrane, which is conductive, and a fixed electrode plate and detecting a pressure according to a change in capacitance between the vibrating membrane and the fixed electrode plate, the method includes an impurity adding step of adding an impurity to a surface of the semiconductor substrate; and a forming step of forming the vibrating membrane and the fixed electrode plate above the semiconductor substrate to which the impurity has been added.

Abstract: Provided is a method of manufacturing an electromechanical transducer having a reduced variation in a breakdown strength caused by a variation in flatness of an insulating layer. In the method of manufacturing the electromechanical transducer, a first insulating layer is formed on a first substrate, a barrier wall is formed by removing a part of the first insulating layer, and a second insulating layer is formed on a region of the first substrate after the part of the first insulating layer has been removed. Next, a gap is formed by bonding a second substrate on the barrier wall, and a vibration film that is opposed to the second insulating layer via the gap is formed from the second substrate. In the forming of the barrier wall, a height on a gap side in a direction vertical to the first substrate becomes lower than a height of a center portion.

Abstract: A sensing element having an integrally formed metal-silicide layer with a silicon layer is described. In some instances, the thickness of the metal-silicide layer can be controlled during fabrication such that the sensing element has a desired resistivity and/or a near linear thermal coefficient of resistance (TCR).

Abstract: An integrated circuit package for an integrated circuit having one or more sensor elements in a sensor element area of the circuit. An encapsulation covers bond wires but leaves an opening over the sensor element area. A protection layer is provided over the integrated circuit over which the encapsulation extends, and it has a channel around the sensor element area to act as a trap for any encapsulation material which has crept into the opening area.

Abstract: A method for fabricating a carbon nanotube film floating on a bottom is provided. The fabrication method of a carbon nanotube film comprises: forming electrodes on a substrate; arranging a suspension comprising a plurality of carbon nanotubes on the electrodes; and arranging the carbon nanotubes on the electrodes by applying a voltage to the electrodes.

Abstract: An edge emitting solid state laser and method. The laser comprises at least one AlInGaN active layer on a bulk GaN substrate with a non-polar or semi-polar orientation. The edges of the laser comprise {1 1?2±6} facets. The laser has high gain, low threshold currents, capability for extended operation at high current densities, and can be manufactured with improved yield. The laser is useful for optical data storage, projection displays, and as a source for general illumination.

Abstract: A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element.

Abstract: An aspect of the present invention provides a mirror driving apparatus, including: a mirror section having a reflecting surface which reflects light; a pair of piezoelectric actuator sections arranged on either side of the mirror section; coupling sections which respectively connect one end of each of the piezoelectric actuator sections to an end portion of the mirror section which is distant from an axis of rotation of the mirror section in a direction along the reflecting surface and perpendicular to the axis of rotation; a fixing section which supports another end of each of the piezoelectric actuator sections; and a perpendicular movement suppressing structure which suppresses translational motion of the axis of rotation of the mirror section in a direction perpendicular to the reflecting surface, one end of the perpendicular movement suppressing structure being connected to the fixing section and another end thereof being connected to the mirror section.

Abstract: Partial perpendicular magnetic anisotropy (PPMA) type magnetic random access memory cells are constructed using processes and structural configurations that induce a directed static strain/stress on an MTJ to increase the perpendicular magnetic anisotropy. Consequently, reduced switching current of the MTJ results. The directed static strain/stress on the MTJ is induced in a controlled direction and/or with a controlled magnitude during fabrication. The MTJ is permanently subject to a predetermined directed stress and permanently includes the directed static strain/strain that provides reduced switching current.

Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure.

Abstract: To provide an optical modulator having a reduced size and reduced power consumption and capable of being easily connected to a waveguide and a method of manufacturing the optical modulator. The optical modulator has at least semiconductor layer (8) having a rib-shaped portion and doped so as to be of a first conduction type, dielectric layer (11) laid on first-conduction-type semiconductor layer (8), and semiconductor layer (9) laid on dielectric layer (11), having the width at the side opposite from dielectric layer (11) increased relative to the width of the rib-shaped portion, and doped so as to be of a second conduction type.

Abstract: A plurality of sequential electro-deposition, planarization and insulator deposition steps are performed over a patterned thick photoresist film to form a laminated ferromagnetic alloy core for micro-fabricated inductors and transformers. The use of a plurality of contiguous thin laminations within deep patterns on non-removable photoresist film provides sufficient volume of magnetic film in, for example, high frequency applications, and reduces eddy current loss at high frequency.

Abstract: A method of forming a microphone forms a backplate, and a flexible diaphragm on at least a portion of a wet etch removable sacrificial layer. The method adds a wet etch resistant material, where a portion of the wet etch resistant material is positioned between the diaphragm and the backplate to support the diaphragm. Some of the wet etch resistant material is not positioned between the diaphragm and backplate. The method then removes the sacrificial material before removing any of the wet etch resistant material added during the prior noted act of adding. The wet etch resistant material then is removed substantially in its entirety after removing at least part of the sacrificial material.

Abstract: An embodiment of an electronic device includes first and second semiconductor bodies. The first semiconductor body houses a first conductive strip having a first end portion and a second end portion, and houses a first conduction terminal electrically coupled to the first end portion and facing a surface of the first semiconductor body. The second semiconductor body houses a second conductive strip having a third end portion and a fourth end portion, and houses a second conduction terminal electrically coupled to the third end portion and facing a surface of the second semiconductor body. The first and second semiconductor bodies are arranged relative to one another so that the respective surfaces face one another, and the first conduction terminal and the second conduction terminal are coupled to one another by means of a conductive element so as to form a loop of an inductor.

Abstract: A micromachining process forms a plurality of layers on a wafer. This plurality of layers includes both a support layer and a given layer. The process also forms a mask, with a mask hole, at least in part on the support layer. In this configuration, the support layer is positioned between the mask hole and the given layer, and longitudinally spaces the mask hole from the given layer. The process also etches a feature into the given layer through the mask hole.

Abstract: A thermoelectric module and methods for making and applying same provide an integrated, layered structure comprising first and second, thermally conductive, surface volumes, each in thermal communication with a separate respective first and second electrically conductive patterned trace layers, and an array of n-type and p-type semiconducting elements embedded in amorphous silica dielectric and electrically connected between the first and second patterned trace layers forming a thermoelectric circuit.

Abstract: Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.

Abstract: Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.

Abstract: A MEMS device includes a substrate. The substrate has a plurality of through holes in the substrate within a diaphragm region and optionally an indent space from the second surface at the diaphragm region. A first dielectric structural layer is then disposed over the substrate from the first surface, wherein the first dielectric structural layer has a plurality of openings corresponding to the through holes, wherein each of the through holes remains exposed by the first dielectric structural layer. A second dielectric structural layer with a chamber is disposed over the first dielectric structural layer, wherein the chamber exposes the openings of the first dielectric structural layer and the through holes of the substrate to connect to the indent space. A MEMS diaphragm is embedded in the second dielectric structural layer above the chamber, wherein an air gap is formed between the substrate and the MEMS diaphragm.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a depression in an upper portion of a semiconductor substrate, placing a sacrificial material in the depression, forming a plurality of fins extending in one direction and arranged periodically by selectively removing the semiconductor substrate and the sacrificial material, forming a device isolation insulating film in a lower portion of space between the fins, removing the sacrificial material, forming a gate insulating film on an exposed surface of the fin, and forming a gate electrode. The gate electrode extends in a direction crossing the one direction so as to straddle the fin on the device isolation insulating film.

Abstract: Devices that include one or more functional semiconductor elements that are immersed in static electric fields (E-fields). In one embodiment, one or more electrets are placed proximate the one or more organic, inorganic, or hybrid semiconductor elements so that the static charge(s) of the electret(s) participate in creating the static E-field(s) that influences the semiconductor element(s). An externally applied electric field can be used, for example, to enhance charge-carrier mobility in the semiconductor element and/or to vary the width of the depletion region in the semiconductor material.

Abstract: The present invention relates to a semiconductor structure and a method for manufacturing the same.

Abstract: Methods of fabrication of electronic modules comprise, on the one hand, power electronic components fabricated on a substrate made of gallium nitride (GaN) and, on the other hand, micro-switches using electrostatic activation of the MEMS (Micro Electro Mechanical System) type. The electronic components and the micro-switches are fabricated on a single gallium nitride substrate and the fabrication method comprises at least the following steps: fabrication of the power components on the gallium nitride substrate; deposition of a first common passivation layer on said components and on the substrate; fabrication of the micro-switches on said substrate.

Abstract: An electro-optic device, comprising an insulating layer and a layer of light-carrying material adjacent the insulating layer. The layer of light-carrying material, such as silicon, comprises a first doped region of a first type and a second doped region of a second, different type abutting the first doped region to form a pn junction. The first doped region has a first thickness at the junction, and the second doped region has a second thickness at the junction, the first thickness being greater than the second thickness, defining a waveguide rib in the first doped region for propagating optical signals. Since the position of the junction coincides with the sidewall of the waveguide rib a self-aligned process can be used in order to simplify the fabrication process and increase yield.

Abstract: The MEMS sensor according to the present invention includes a diaphragm.

Abstract: The present invention is a method for producing a capacitor. The method includes applying a dielectric substance (ex.—silicon nitride) to a first gold seed layer, the first gold seed layer being formed on a wafer. A second gold seed layer is formed upon the dielectric substance and first gold seed layer. Gold is electroplated into a photoresist to form a first set of 3-D capacitor elements on the second gold seed layer. A first copper layer is electroplated onto the second gold seed layer. Gold is electroplated into a photoresist to form a second set of 3-D capacitor elements, the second set of 3-D elements being formed at least partially within the first copper layer and being connected to the first set of 3-D elements. A second copper layer is electroplated onto the first copper layer. Then, both copper layers are removed to provide (ex.—form) the capacitor.

Abstract: Electro-acoustic transducers and methods of manufacturing the electro-acoustic transducer are provided. An electro-acoustic transducer includes: a first wafer including a first substrate in which a plurality of electro-acoustic transducer cells are formed; and a second wafer disposed in a lower portion of the first wafer, and including a second substrate in which a plurality of through wafer vias are formed. A method of manufacturing an electro-acoustic transducer includes: forming a plurality of electro-acoustic transducer cells in a first substrate of a first wafer; forming a plurality of through wafer vias in a second substrate of a second wafer; and bonding the first and second wafers to each other.

Abstract: To reduce dent defects formed in interlayer CMP process on a capacitor array after forming an interlayer insulating film on the capacitor array thicker than the height of a capacitor, the interlayer insulating film on the capacitor array is subjected to a step height reduction etching to form an opening with etching depth Hd, while remaining a first region that is a distance Lr in a horizontal direction from a rising point of a projected portion of the interlayer insulating film periphery to the capacitor array onto a part of the capacitor array, wherein an aspect ratio (Hd/Lr) of the Hd to the Lr is equal to or less than 0.6.

Abstract: A semiconductor laser element includes a substrate of a first conduction type and a layered semiconductor structure formed on the substrate. The layered semiconductor structure includes a first semiconductor layer of the first conduction type formed on the substrate, an active layer formed on the first semiconductor layer, and a second semiconductor layer of a second conduction type formed on the active layer, the second conduction type being opposite to the first conduction type. The first semiconductor layer, the active layer, and the second semiconductor layer include a non-window region through which a light emitted from the active layer passes and a window region surrounding the non-window region. Band gap energy of the active layer is larger in the window region than in the non-window region. The second semiconductor layer includes a current confinement layer.