Abstract: A method of forming a semiconductor structure includes providing a substrate and providing a detach region which is carried by the substrate. A device structure which includes a stack of crystalline semiconductor layers is provided, wherein the detach region is positioned between the device structure and substrate. The stack is processed to form a vertically oriented semiconductor device.

Abstract: As a base substrate, a substrate having an insulating surface such as a glass substrate is used. Then, a single crystal semiconductor layer is formed over the base substrate with the use of a large-sized semiconductor substrate. Note that, it is preferable that the base substrate be provided with a plurality of single crystal semiconductor layers. After that, the single crystal semiconductor layers are cut to divide the single crystal semiconductor layers into a plurality of single crystal semiconductor regions by patterning. Next, the single crystal semiconductor regions are irradiated with laser light or heat treatment is performed on the single crystal semiconductor regions in order to improve the planarity of surfaces and reduce defects. Peripheral portions of the single crystal semiconductor regions are not used as semiconductor elements, and central portions of the single crystal semiconductor regions are used as the semiconductor elements.

Abstract: One embodiment of the present invention provides a system for facilitating proximity communication between semiconductor chips. The system includes a base chip and a bridge chip, each of which includes an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The active face of the bridge chip is bonded to the active face of the base chip. Then, an identified portion of the active face of the bridge chip is thinned via etching and is removed by planarizing the back face of the bridge chip, thereby creating an opening in the bridge chip that exposes a portion of the active face of the base chip.

Abstract: A supporting substrate is laminated on a wafer in such a manner that the supporting substrate locked in peripheral edges with a plurality of locking claws is disposed in proximity to and facing to an adhering surface of a double-sided adhesive sheet on the workpiece, the supporting substrate is pressed by a pressing member made of an approximately hemispherical elastic body from an approximate center of a non-adhering surface of this supporting substrate, the supporting substrate is laminated by elastically deforming this pressing member on the wafer while making the supporting substrate surface contact in a flat condition.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.

Abstract: The invention concerns a method for preparing a thin layer (28) or a chip to be transferred onto another substrate, this method including the realization, above the surface of said thin layer or said chip, of at least one layer, called adhesive layer (25), and of at least one layer, called first barrier layer (22), the adhesive layer being made of a material of which etching presents selectivity in relation to the material of the barrier layer.

Abstract: A device structure includes a III-nitride wurtzite semiconductor light emitting region disposed between a p-type region and an n-type region. A bonded interface is disposed between two surfaces, one of the surfaces being a surface of the device structure. The bonded interface facilitates an orientation of the wurtzite c-axis in the light emitting region that confines carriers in the light emitting region, potentially increasing efficiency at high current density.

Abstract: Semiconductor wafers having a thin layer of strained semiconductor material. These structures include a substrate; an oxide layer upon the substrate; a silicon carbide (SiC) layer upon the oxide layer, and a strained layer of a semiconductor material in a strained state upon the silicon carbide layer, or a matching layer upon the donor substrate that is made from a material that induces strain in subsequent epitaxially grown layers thereon; a strained layer of a semiconductor material of defined thickness in a strained state; and an insulating or semi-insulating layer upon the strained layer in a thickness that retains the strained state of the strained layer. The insulating or semi-insulating layers are made of silicon carbide or oxides and act to retain strain in the strained layer.

Abstract: A process for producing a semiconductor substrate comprising a carrier wafer and a layer of single-crystalline semiconductor material: a) producing a layer containing recesses at the surface of a donor wafer of single-crystalline semiconductor material, b) joining the surface of the donor wafer containing recesses to the carrier wafer, c) heat treating to close the recesses at the interface between the carrier wafer and the donor wafer to form a layer of cavities within the donor wafer, and d) splitting the donor wafer along the layer of cavities, resulting in a layer of semiconductor material on the carrier wafer. Semiconductor substrates prepared thusly may have a single-crystalline semiconductor layer having a thickness of 100 nm or less, a layer thickness uniformity of 5% or less, and an HF defect density of 0.02/cm2 or less.

Abstract: A method for manufacturing a semiconductor device provided with a circuit capable of high speed operation while the manufacturing cost is reduced.

Abstract: A semiconductor memory device includes a substrate and an interconnect region carried by the substrate. A donor layer is coupled to the interconnect region through a bonding interface. An electronic device is formed with the donor layer, wherein the electronic device is formed after the bonding interface is formed. A capacitor is connected to the electronic device so that the electronic device and capacitor operate as a dynamic random access memory device.

Abstract: A method and apparatus for correcting overlay errors in a lithography system. During lithographic exposure, features being exposed on the wafer need to overlay existing features on the wafer. Overlay is a critical performance parameter of lithography tools. The wafer is locally heated during exposure. Thermal expansion causes stress between the wafer and the wafer table, which will cause the wafer to slip if it exceeds the local frictional force. To increase the amount of expansion allowed before slipping occurs, the wafer chuck is uniformly expanded after the wafer has been loaded. This creates an initial stress between the wafer and the wafer table. As the wafer expands due to heating during exposure, the expansion first acts to relieve the initial stress before causing an opposite stress from thermal expansion. The wafer may be also be heated prior to attachment to the wafer chuck, creating the initial stress as the wafer cools.

Abstract: Semiconductor devices and methods for making such devices are provided. One such method may include forming an epitaxial layer of single crystal SiC on a single crystal Si growth substrate, forming an epitaxial diamond layer on the layer of SiC, forming a Si layer on the diamond layer, bonding a SiO2 surface of a Si carrier substrate to the Si layer, and removing the Si growth substrate to expose the SiC layer. In yet another aspect, a semiconductor layer may be deposited onto the SiC layer. The semiconductor layer may further be deposited epitaxially.

Abstract: The invention relates to a process for obtaining a thin layer made of a first material on a substrate made of a second material called the final substrate, including the following steps: bonding a thick layer of a first material on one of its main faces on the final substrate at an interface, implantation of gaseous species in the thick layer of first material to create a weakened zone delimiting said thin layer between the interface and the weakened zone, deposit a layer of third material called the self-supporting layer on the thick layer made of first material, fracture within the structure composed of the final substrate, the thick layer of first material and the layer of third material, at the weakened zone to supply the substrate supporting said thin layer.

Abstract: A method for fabricating semiconductor on insulator wafers by providing a semiconductor substrate or a substrate that includes an epitaxial semiconductor layer as a source substrate, attaching the source substrate to a handle substrate to form a source handle assembly and detaching the source substrate at a predetermined splitting area provided inside the source substrate and being essentially parallel to its main surface, to remove a layer from the source handle assembly to thereby create the semiconductor on insulator wafer. A diffusion barrier layer, in particular, an oxygen diffusion barrier layer can be provided on the source substrate. In addition the invention relates to the corresponding semiconductor on insulator wafers that are produced by the method.

Abstract: A multilayered substrate structure comprising one or more devices, e.g., optoelectronic, integrated circuit. The structure has a handle substrate, which is characterized by a predetermined thickness and a Young's modulus ranging from about 1 Mega Pascal to about 130 Giga Pascal. The structure also has a thickness of substantially crystalline material coupled to the handle substrate. Preferably, the thickness of substantially crystalline material ranges from about 100 microns to about 5 millimeters. The structure has a cleaved surface on the thickness of substantially crystalline material and a surface roughness characterizing the cleaved film of less than 200 Angstroms. At least one or more optoelectronic devices is provided on the thickness of material.

Abstract: Highly reliable single crystal semiconductor layers and semiconductor devices can be obtained through a fewer manufacturing steps. A method for manufacturing a semiconductor device is proposed.

Abstract: The present invention provides a method of manufacturing a bonded wafer. The method comprises an oxidation step in which an oxide film is formed on at least one surface of a base wafer, a bonding step in which the base wafer on which the oxide film has been formed is bonded to a top wafer to form a bonded wafer, and a thinning step in which the top wafer included in the bonded wafer is thinned. The oxidation step comprises heating the base wafer to a heating temperature ranging from 800 to 1300° C. at a rate of temperature increase ranging from 1 to 300° C./second in an oxidizing atmosphere, and the bonding step is carried out so as to position the oxide film formed in the oxidation step at an interface of the top wafer and the base wafer.

Abstract: A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided.

Abstract: A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.

Abstract: Methods for packaging microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One aspect of the invention is directed toward a method for packaging a microelectronic device that includes coupling an active side of a microelectronic die to a surface of a support member. The microelectronic die can have a backside opposite the active side, a peripheral side extending at least part way between the active side and the backside, and at least one through-wafer interconnect. The method can further include applying an encapsulant to cover a portion of the surface of the support member so that a portion of the encapsulant is laterally adjacent to the peripheral side, removing material from a backside of the microelectronic die to expose a portion of at least one through-wafer interconnect, and applying a redistribution structure to the backside of the microelectronic die.

Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.

Abstract: Ge/Si and other nonsilicon film heterostructures are formed by hydrogen-induced exfoliation of the Ge film which is wafer bonded to a cheaper substrate, such as Si. A thin, single-crystal layer of Ge is transferred to Si substrate. The bond at the interface of the Ge/Si heterostructures is covalent to ensure good thermal contact, mechanical strength, and to enable the formation of an ohmic contact between the Si substrate and Ge layers. To accomplish this type of bond, hydrophobic wafer bonding is used, because as the invention demonstrates the hydrogen-surface-terminating species that facilitate van der Waals bonding evolves at temperatures above 600° C. into covalent bonding in hydrophobically bound Ge/Si layer transferred systems.

Abstract: In some embodiments, a method of forming a photovoltaic cell includes (1) forming a cleave plane in a donor body so as to define a lamina to be bonded to a receiver element and exfoliated from the donor body; (2) prior to bonding, pre-heating the donor body without the receiver element to a temperature of greater than about 200° C. for a first time period that is less than a time period required for exfoliation of the lamina from the donor body; (3) cooling the donor body after pre-heating the donor body; (4) bonding the donor body to the receiver element; and (5) heating the bonded donor body and receiver element for a second time period so as to complete the exfoliation of the lamina from the donor body. Numerous other aspects are provided.

Abstract: A method for fabricating a thermal management substrate comprises acts of ion-implanting a substrate material to form a substrate layer, a ion-implanted layer, and an overlay layer; bonding a handle wafer to the overlay layer with a SiO2 bonding layer; splitting the ion-implanted wafer at the ion-implanted layer, resulting in a handle wafer SiO2 bonded with the overlay layer; depositing an insulating layer onto the overlay layer; and removing the handle wafer, whereby the resulting thermal management substrate comprises an overlay layer epitaxially fused with the insulating layer.

Abstract: A method for minimizing defects when transferring a useful layer from a donor wafer to a receptor wafer is described. The method includes providing a donor wafer having a surface below which a zone of weakness is present to define a useful layer to be transferred, molecularly bonding at a bonding interface the surface of the useful layer of the donor wafer to a surface of the receptor wafer to form a structure, heating the structure at a first temperature that is substantially higher than ambient temperature for a first time period sufficient to liberate water molecules from the bonding interface, with the heating being insufficient to cause detachment of the useful layer at the zone of weakness, and detaching the useful layer from the donor wafer.

Abstract: It is an object of the present invention to manufacture, with high yield, a semiconductor device in which an element that has a layer containing an organic compound is provided over a flexible substrate. A method for manufacturing a semiconductor device includes: forming a separation layer over a substrate; forming an element-formed layer over the separation layer by forming an inorganic compound layer, a first conductive layer, and a layer containing an organic compound and forming a second conductive layer which is in contact with the layer containing an organic compound and the inorganic compound layer; and separating the separation layer and the element-formed layer from each other after pasting a first flexible substrate over the second conductive layer.

Abstract: A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.

Abstract: A method (200) is described for an electronic assembly (30). An electronic die (24) with a sacrificial layer (28) on its back (27) and electrical contacts (26) on its front (25) is temporarily attached by its front (25) to a substrate (32). The back (27) is over-molded by a first material (34) extending over the substrate (32). The substrate (32) is removed leaving the die contacts (26) and the first material (33, 34) exposed. Interconnect layer(s) (44, 64) are provided over the first material (33, 34) and the die (24), electrically coupled to the contacts (26). Further components (66) can be coupled to the upper-most interconnects (64, 53). A second material (68) is over-molded over the components (66) and upper-most interconnects (64, 53). Thinning the first material (34) exposes the sacrificial layer (28) for removal.

Abstract: Embodiments of the invention contemplate the formation of a low cost solar cell using a novel electroplating apparatus and method to form a metal contact structure having metal lines formed using an electrochemical plating process. The apparatus and methods described herein remove the need to perform the often costly processing steps of performing a mask preparation and formation steps, such as screen printing, lithographic steps and inkjet printing steps, to form a contact structure. The resistance of interconnects formed in a solar cell device greatly affects the efficiency of the solar cell. It is thus desirable to form a solar cell device that has a low resistance connection that is reliable and cost effective. Therefore, one or more embodiments of the invention described herein are adapted to form a low cost and reliable interconnecting layer using an electrochemical plating process containing a common metal, such as copper.

Abstract: The invention specifically relates to methods of fabricating a composite substrate by providing a first insulating layer on a support substrate at a thickness of e1 and providing a second insulating layer on a source substrate at a thickness of e2, with each layer having an exposed face for bonding; providing plasma activation energy in an amount sufficient to activate a portion of the thickness of the face of the first insulating layer emp1 and a portion of the thickness of the face of the second insulating layer emp1; providing a final insulating layer by molecular bonding the activated face of the first insulating layer with the activated face of the second insulating layer; and removing a back portion of the source substrate while retaining an active layer comprising a remaining portion of the source substrate bonded to the support substrate with the final insulating layer interposed therein to form the composite substrate.

Abstract: The invention relates to the collective fabrication of superposed microstructures, such as an integrated circuit and a protective cover. Individual structures each comprising superposed first and second elements are fabricated collectively. The first elements (for example, integrated circuit chips) are prepared on a first plate and the second elements (for example, transparent covers) are prepared on a second plate. The plates are bonded to each other over the major portion of their facing surfaces, but with no bonding of the defined zones in which there is no adhesion. The individual structures are then diced via the top on the one hand and via the bottom on the other hand along different parallel dicing lines passing through the zones with no adhesion, so that, after dicing, the first elements retain surface portions (those lying between the parallel dicing lines) that are not covered by a second element. A connection pad may thus remain accessible at this point.

Abstract: In the present application, is disclosed a method of manufacturing a flexible semiconductor device having an excellent reliability and tolerance to the loading of external pressure. The method includes the steps of: forming a separation layer over a substrate having an insulating surface; forming an element layer including a semiconductor element comprising a non-single crystal semiconductor layer, over the separation layer; forming an organic resin layer over the element layer; providing a fibrous body formed of an organic compound or an inorganic compound on the organic resin layer; heating the organic resin layer; and separating the element layer from the separation layer. This method allows the formation of a flexible semiconductor device having a sealing layer in which the fibrous body is impregnated with the organic resin.

Abstract: A method for forming a light-transmitting region comprises providing a support feature. A sacrificial layer is formed over a portion of the support feature, wherein the sacrificial layer comprises an energy-induced swelling material. A light-blocking layer is conformably formed over the support feature to cover the sacrificial layer and the support feature. The support feature, the sacrificial layer, and the light-blocking layer are subjected to an energy source to swell the sacrificial layer until bursting to thereby delaminate a portion of the light-blocking layer from the support feature and leave a light-transmitting region exposed with a portion of the support feature in the light-blocking layer. A gas flow or scrub cleaning force is provided to clean up the light-transmitting region and a top surface of the light-blocking layer remains over the support feature.

Abstract: Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.

Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing a bonding sheet having one or more holes that penetrate from a first surface to an opposite second surface thereof, and a semiconductor wafer having a semiconductor element; affixing the bonding sheet to a predetermined surface of the semiconductor wafer; and evacuating gas present between the bonding sheet and the semiconductor wafer via the one or more holes.

Abstract: A method of forming buried cavities in a wafer of monocrystalline semiconductor material with at least one cavity formed in a substrate of monocrystalline semiconductor material by timed TMAH etching silicon; covering the cavity with a material inhibiting epitaxial growth; and growing a monocrystalline epitaxial layer above the substrate and the cavities. Thereby, the cavity is completely surrounded by monocrystalline material. Starting from this wafer, it is possible to form a thin membrane. The original wafer must have a plurality of elongate cavities or channels, parallel and adjacent to one another. Trenches are then excavated in the epitaxial layer as far as the channels, and the dividers between the channels are removed by timed TMAH etching.

Abstract: The invention concerns a sealing zone between two microstructure substrates. Said sealing zone comprises at least the following parts: on a first wafer level (20), a lower edging (22A) made of an adhesive material capable of causing the first substrate (20) to adhere to a sealing material, said sealing material being adapted to spontaneously diffuse jointly with the material of the second wafer level (30); on said lower edging (22A), a layer of said sealing material; and on said layer of sealing material, a protuberance (36) formed on said second wafer level (30) containing a certain amount of sealing material. The invention is applicable to microstructures comprising vacuum-operated components.

Abstract: A method of manufacturing a photodetecting device, by providing a first wafer that includes a photosensitive layer made of a semiconductor material and a second wafer that includes a circuit layer of electronic components, with one of the photosensitive layer or the circuit layer incorporating a field isolation layer; bonding the first and second wafers to form a structure comprising successively the circuit layer, the field isolation layer and the photosensitive layer; and forming electrically conductive vias to electrically connect the photosensitive layer to at least some of the electronic components of the circuit layer. Also, photodetecting devices prepared by these methods.

Abstract: A multi-layer device is provided for connecting to an electrical unit enclosed within the multi-layer device. A first wafer has a first outer terminal and a second outer terminal with etch pits. A first insulator has a first surface bonded to the first wafer and a first inner terminal located on an opposing second surface. A second wafer has a first surface bonded to the second surface of the first insulating layer and includes a pillar electrically connected to the first wafer. A second insulator has a first surface bonded to a second surface of the second wafer and a second inner terminal located on the first surface of the second insulator. The first outer terminal is electrically connected to the first inner terminal, and the second outer terminal is electrically connected to the second inner terminal. The first and second outer terminals are adapted for connecting to an electrical unit.

Abstract: It is an object to reduce a thickness of a semiconductor component (chip) on a substrate to a predetermined thickness regardless of a variation in thickness of a substrate in a semiconductor product. In a semiconductor product mounted on a base plate, a surface of a semiconductor component on a substrate is set to be located at a predetermined height h from a surface of a base plate. Thereafter, through machining the surface of the semiconductor component which is adjusted to be located at the predetermined height, it is possible to make the thickness of the semiconductor component on the substrate equal to a predetermined thickness.

Abstract: Provided is a method and apparatus for close alignment of two or more electrically conductive wafers which are positioned face-to-face in closely spaced opposition, the wafers having position marks on corresponding portions thereof, the wafers being aligned as to their mating components, as guided by optically comparing the alignment of the respective position marks; deflecting an interior portion of one of the wafers into contact with the other wafer, to partially bond the wafers to each other, then fully contacting and bonding the rest of the wafer pair and then optically checking the resulting wafer alignment to see if same is acceptable.

Abstract: Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.

Abstract: A semiconductor layer structure includes a donor substrate and a detach region carried by the donor substrate. A device structure is carried by the donor substrate and positioned proximate to the detach region. The device structure includes a stack of crystalline semiconductor layers. The stack of crystalline semiconductor layers includes a pn junction.

Abstract: A process for fabricating a silicon on insulator (SOI) substrate by forming a weakened zone within a semiconductor donor substrate to define a thick layer having a thickness of greater 150 nm and form a boundary between the thick layer and a remainder of the donor substrate, bonding the donor substrate to a semiconductor receiver substrate, with one of the substrates including an oxide layer that is present between the donor and receiver substrates after bonding; detaching a remainder of the donor substrate along the weakened zone to obtain a semifinished SOI substrate comprising the receiver substrate, the oxide layer and the thick layer; and finishing the semifinished SOI substrate by thinning the thick layer to obtain a silicon layer having a thickness is less than that of the thick layer but greater than 150 nm; long annealing the semifinished SOI substrate in a gaseous atmosphere comprising hydrogen and/or argon; and thinning the thin layer to obtain an ultrathin layer with a thickness of 150 nm or less

Abstract: Conventional heat bonding and anodic bonding require heating at high temperature and for a long time, leading to poor production efficiency and occurrence of a warp due to a difference in thermal expansion, resulting in a defective device. Such a problem is solved. An upper wafer 7 made of glass and a lower wafer 8 made of Si are surface-activated using an energy wave before performing anodic bonding, thereby performing bonding at low temperature and increasing a bonding strength. In addition, preliminary bonding due to surface activation is performed before main bonding due to anodic bonding is performed in a separate step or device, thereby increasing production efficiency, and enabling bonding of a three-layer structure without occurrence of a warp.

Abstract: The invention relates to improvements in a method for molecularly bonding first and second substrates together by placing them in surface to surface contact. The improvement includes, prior to placing the substrates in contact, cleaning the surface of one or both of the substrates in a manner to provide a cleaned surface that is slightly roughened compared to a conventionally polished surface, and heating at least one or both of the substrates prior to placing the substrates in contact while retaining the heating at least until the substrates are in surface to surface contact.

Abstract: The invention concerns a method of collective bonding of individual chips on a strained substrate (44), which comprises the following steps: functionalised layers (40) are arranged on a support (41), in an adjacent non-contiguous manner, with a space e between two neighboring layers (40), a calibrated drop of adhesive (43) is deposited on each of these functionalised layers, the strained substrate (44) is transferred onto these drops of adhesive, the parts of the assembly thereby formed are singularized to produce chips (45) bonded to the surface of strained substrate. The invention also concerns a method of placing under strain a semiconductor reading circuit by a substrate in a material of different coefficient of expansion.

Abstract: A method includes steps of providing first and second substrates, and forming a bonding interface between them using a conductive bonding region. A portion of the second substrate is removed to form a mesa structure. A vertically oriented semiconductor device is formed with the mesa structure. A portion of the conductive bonding region is removed to form a contact. The vertically oriented semiconductor device is carried by the contact.

Abstract: A partially completed multi-layered substrate, e.g., silicon on silicon. The substrate has a thickness of material from a first substrate. The thickness of material comprises a first face region. The substrate has a second substrate having a second face region. Preferably, the first face region of the thickness of material is joined to the second face region of the second substrate. The substrate has an interface region formed between the first face region of the thickness of material and the second face region of the second substrate. A plurality of particles are implanted within a portion of the thickness of the material and a portion of the interface region to electrically couple a portion of the thickness of material to a portion of the second substrate.