Abstract: An inhibited mud acid composition, said composition comprising: hydrofluoric acid in solution; an alkanolamine; and a mineral acid selected from a group consisting of: HCl; MEA-HCl and other modified acids, wherein said alkanolamine and hydrofluoric acid are present in a molar ratio of at least 1:1.

Abstract: There is provided a technique that includes selectively doping a metal film with a dopant by performing: supplying a dopant-containing gas containing the dopant to a substrate in which the metal film and a film other than the metal film are formed on a film in which the dopant is doped; and removing the dopant-containing gas from above the substrate.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to two sides of the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a contact hole in the ILD layer to expose the source/drain region; forming a barrier layer in the contact hole; performing an anneal process; and performing a plasma treatment process to inject nitrogen into the contact hole.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

Abstract: Techniques are disclosed for backside source/drain (S/D) replacement for semiconductor devices with metallization on both sides (MOBS). The techniques described herein provide methods to recover or otherwise facilitate low contact resistance, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some cases, the techniques include forming sacrificial S/D material and a seed layer during frontside processing of a device layer including one or more transistor devices. The device layer can then be inverted and bonded to a host wafer. A backside reveal of the device layer can then be performed via grinding, etching, and/or CMP processes. The sacrificial S/D material can then be removed through backside S/D contact trenches using the seed layer as an etch stop, followed by the formation of relatively highly doped final S/D material grown from the seed layer, to provide enhanced ohmic contact properties. Other embodiments may be described and/or disclosed.

Abstract: Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a low-level bit line positioned above the substrate, a high-level bit line bottom contact positioned above the substrate and adjacent to the low-level bit line, and first air gaps positioned adjacent to the low-level bit line.

Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.

Abstract: Structures including field-effect transistors and methods of forming a structure including field-effect transistors. A first field-effect transistor includes a first source/drain terminal and a second source/drain terminal, and a second field-effect transistor includes a third source/drain terminal and a fourth source/drain terminal. The first source/drain terminal and the second source/drain terminal each include a fully-silicided section located at and above a top surface of a semiconductor layer. The third source/drain terminal and the fourth source/drain terminal each include a partially-silicided section located over the top surface of the semiconductor layer.

Abstract: A method of forming source/drain contacts with reduced capacitance and resistance, including, forming a source/drain and a channel region on an active region of a substrate, forming a dielectric fill on the source/drain, forming a trench in the dielectric fill, forming a source/drain contact in the trench, forming an inner contact mask section on a portion of an exposed top surface of the source/drain contact, removing a portion of the source/drain contact to form a channel between a sidewall of the dielectric fill and a remaining portion of the source/drain contact, where a surface area of the remaining portion of the source/drain contact is greater than the surface area of the exposed top surface of the source/drain contact, and forming a source/drain electrode fill on the remaining portion of the source/drain contact.

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

Abstract: A semiconductor device includes a substrate, a gate disposed over the substrate, a source/drain disposed in the substrate at two sides of the gate, and an insulating layer disposed over sidewalls of the gate and at least a portion of a surface of the source/drain. In some embodiments, the insulating layer includes a first side facing the gate or the source, and includes a second side opposite to the first side. The insulating layer includes dopants, and a concentration of the dopants is reduced from the second side to the first side of the insulating layer.

Abstract: A fin-type field effect transistor including a substrate, insulators, a gate stack, a first spacer, a second spacer, and a third spacer is described. The substrate has fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and over the insulators. The first spacer is located over the sidewall of the gate stack. The second spacer is located over the first spacer. The first spacer and the second spacer includes carbon. The third spacer is located between the first spacer and the second spacer.

Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.

Abstract: A three-dimensional memory device includes a source-level material layer stack located over a substrate that includes, from bottom to top, a lower source-level semiconductor layer, a semiconductor oxide tunneling layer, a source contact layer including a doped semiconductor material, and an upper source-level semiconductor layer, an alternating stack of electrically conductive layers and insulating layers located over the source-level material layer stack, and memory stack structures that extend through the alternating stack and into an upper portion of the lower source-level semiconductor layer, in which each memory stack structure includes a vertical semiconductor channel and a memory film laterally surrounding the vertical semiconductor channel, and each of the vertical semiconductor channels vertically extends through, and is electrically connected to, the source contact layer.

Abstract: A method includes providing a semiconductor structure comprising a varactor region and a field effect transistor region. The varactor region includes a body region in a semiconductor material that is doped to have a first conductivity type. A gate-first process is performed by forming a gate stack over the semiconductor structure. The gate stack includes a layer of gate insulation material and a layer of work function adjustment metal positioned over the layer of gate insulation material. The gate stack is patterned to define a first gate structure over the varactor region and a second gate structure over the field effect transistor region. A source region and a drain region are formed in the field effect transistor region adjacent the second gate structure. The source region and the drain region are doped to have a second conductivity type opposite to the first conductivity type.

Abstract: Methods for manufacturing semiconductor structures are provided. The method for manufacturing a semiconductor structure includes forming a source/drain structure over a substrate and forming a metal layer over the source/drain structure. The method for manufacturing a semiconductor structure further includes reacting a portion of the metal layer with the source/drain structure to form a metallic layer by using an etching solvent. In addition, the etching solvent includes (a) a first component and (b) a second component. The first component includes an acid, and the second component includes propylene carbonate (PC), ethylene carbonate (EC), diethyl carbonate (DEC), or a combination thereof.

Abstract: A display device includes a sealing film covering a display region where an image is displayed, a touch sensor layer configured to detect a touched position of the display region, the touch sensor layer including a first electrode layer that is arranged on the sealing film, a first insulating layer that is formed on the first electrode layer using a material including nitrogen, and a second electrode layer that is arranged over the first insulating layer, an overcoat covering the touch sensor layer, and a polarizing plate being arranged on the overcoat. The touch sensor layer further includes a second insulating layer configured to inhibit a reaction between nitrogen included in the first insulating layer and water included in the overcoat, the second insulating layer being formed between the first insulating layer and the overcoat using a material not including nitrogen.

Abstract: In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.

Abstract: In a method of manufacturing a semiconductor device, a first layer containing a Si1-xGex layer doped with phosphorous is formed over an n-type semiconductor layer, a metal layer containing a metal material is formed over the first layer, and a thermal process is performed to form an alloy layer including Si, Ge and the metal material.

Abstract: A semiconductor device includes a substrate, a conductive wiring which comprises cobalt or copper and is electrically connected to the substrate, an insulating material which electrically isolates the conductive wiring from neighboring wiring, and a first barrier layer which comprises a first cobalt alloy and is disposed between the conductive wiring and the insulating material.

Abstract: Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.

Abstract: A method of fabricating a cobalt silicide layer includes providing a substrate disposed in a chamber. A deposition process is performed to form a cobalt layer covering the substrate. The deposition process is performed when the temperature of the substrate is between 50° C. and 100° C., and the temperature of the chamber is between 300° C. and 350° C. After the deposition process, an annealing process is performed to transform the cobalt layer into a cobalt silicide layer. The annealing process is performed when the substrate is between 300° C. and 350° C., and the duration of the annealing process is between 50 seconds and 60 seconds.

Abstract: A compound film of tungsten and germanium useful for semiconductor devices, a semiconductor device using the compound film and a method and an apparatus for manufacturing the compound film. Various embodiments include a compound film of tungsten and germanium, which has a germanium/tungsten composition ratio of 0.2 or more and less than 6 and includes an optical energy gap. The compound film of tungsten and germanium is produced on a substrate by causing a material gas of tungsten and a material gas of germanium to undergo a chemical reaction in at least one of a region in a gas phase and a region on the substrate. Various embodiments include a semiconductor device including a stack structure in which a semiconductor substrate, a compound film of tungsten and germanium having a germanium/tungsten composition ratio of 1 or more and 3.2 or less, and a metal electrode are laminated in this order.

Abstract: The present invention relates to a semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, an insulating stacked structure and a first conductive layer. The gate structure is disposed on the substrate, and the insulating stacked structure covers the gate structure and the substrate to define a first opening therein to expose a portion of the gate structure and a portion of the substrate. The first conductive layer covers surfaces of the first opening to directly contact the portion of the substrate and the portion of the gate structure, with the first conductive layer including two outer extension wings on a top surface of the insulating stacked structure.

Abstract: Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.

Abstract: An anode active material for a lithium secondary battery, the anode active material including a metal silicide core, a silicon shell disposed on the core, and a metal nitride disposed on a surface of the silicon shell opposite the core.

Abstract: A method for fabricating a CMOS integrated circuit structure and the CMOS integrated circuit structure. The method includes creating one or more n-type wells, creating one or more p-type wells, creating one or more pFET source-drains embedded in each of the one or more n-type wells, creating one or more nFET source-drains embedded in each of the one or more p-type wells, creating a pFET contact overlaying each of the one or more pFET source-drains, and creating an nFET contact overlaying each of the one or more nFET source-drains. A material of each of the one or more pFET source-drains includes silicon doped with a p-type material; a material of each of the one or more nFET source-drains includes silicon doped with an n-type material; a material of each pFET contact includes nickel silicide; and a material of each nFET contact comprises titanium silicide.

Abstract: A method for manufacturing a memory device comprises forming an initial silicide layer, including depositing and annealing a precursor metal over a layer of silicon material on a top surface of a stack of conductive strips in amounts effective to result in a majority of the initial silicide layer being a mono-silicon silicide of the precursor metal. The method comprises depositing and annealing additional silicon material over the initial silicide layer in amounts effective to result in formation of di-silicon silicide of the precursor metal to form a landing pad on the top surface of the stack of conductive strips, the formation of the di-silicon silicide of the precursor metal consuming mono-silicon silicide of the initial silicide layer so a majority of a silicide of the landing pad is di-silicon silicide.

Abstract: A device includes a metal-silicide region formed in a semiconductor material in a contact opening. A concentration of a material, including chlorine, fluorine, or a combination thereof is in the metal-silicide region near an uppermost surface of the metal-silicide region. The presence of chlorine or fluorine results from a physical bombarding of the chlorine or fluorine in the contact opening. As a result of the physical bombard, the opening becomes wider at the bottom of the opening and the sidewalls of the opening are thinned. A capping layer is over the metal-silicide region and over sidewalls of a contact plug opening. A contact plug is formed over the capping layer, filling the contact plug opening. Before the contact plug is formed, a silicidation occurs to form the metal-silicide and the metal-silicide is wider than the bottom of the opening.

Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.

Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.

Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.

Abstract: A temperature transmitter assembly includes a thermocouple and a temperature transmitter. The thermocouple has a first conductor and a second conductor connected to each other at a junction. The temperature transmitter has diagnostics that determines a resistance of the thermocouple and based on the determined resistance, provides an indication of whether the first conductor and the second conductor are shorted together before the junction.

Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.

Abstract: A technique capable of controlling in-plane uniformity of a film formed on a substrate includes a step of forming a film on a substrate by performing a predetermined number of cycles in which a step of supplying a metal-containing gas to the substrate and a step of supplying a reducing gas containing an element that becomes a solid by itself to the substrate are performed in a time-division manner. The reducing gas has a property of changing a deposition rate of the film from an increasing rate to a decreasing rate in accordance with the exposure amount of the reducing gas with respect to the substrate. In the step of supplying the reducing gas, the exposure amount of the reducing gas with respect to the substrate is adjusted in accordance with the property of the reducing gas.

Abstract: Provided is a wiring structure for display device which does not generate hillocks even when exposed to high temperatures at levels around 450 to 600° C., has excellent high-temperature heat resistance, keeps electrical resistance (wiring resistance) of the entire wiring structure low, and further has excellent resistance to hydrofluoric acid. This wiring structure for a display device comprises a structure in which are laminated, in order from the substrate side, a first layer of an Al alloy that contains at least one chemical element selected from the group (group X) consisting of Ta, Nb, Re, Zr, W, Mo, V, Hf, Ti, Cr, and Pt and contains at least one rare earth element, and a second layer of an Al alloy nitride, or a nitride of at least one chemical element selected from the group Y consisted of Ti, Mo, Al, Ta, Nb, Re, Zr, W, V, Hf, and Cr.

Abstract: A nanowire field effect transistor (FET) device and method for forming a nanowire FET device are provided. A nanowire FET including a source region and a drain region is formed. The nanowire FET further includes a nanowire that connects the source region and the drain region. A source silicide is formed on the source region, and a drain silicide is formed on the drain region. The source silicide is comprised of a first material that is different from a second material comprising the drain silicide.

Abstract: Methods for forming a metal silicide film with low resistivity at low temperature are described. A metal silicide film is formed on a substrate surface and annealed at high pressure and low temperature.

Abstract: A MOS gate structure including a p base region, a p epitaxial layer, an n++ source region, a p+ contact region, an n inversion region, a gate insulating film, and a gate electrode and a front surface electrode are provided on the front surface of an epitaxial substrate obtained by depositing an n? epitaxial layer on the front surface of a SiC substrate. A first metal film is provided on the front surface electrode so as to cover 10% or more, preferably, 60% to 90%, of an entire upper surface of the front surface electrode. The SiC-MOSFET is manufactured by forming a rear surface electrode, forming the first metal film on the surface of the front surface electrode, and annealing in a N2 atmosphere. According to this structure, it is possible to suppress a reduction in gate threshold voltage in a semiconductor device using a SiC semiconductor.

Abstract: The present disclosure generally relates to methods of selectively forming titanium silicides on substrates. The methods are generally utilized in conjunction with contact structure integration schemes. In one embodiment, a titanium silicide material is selectively formed on a substrate as an interfacial layer on a source/drain region. The titanium silicide layer may be formed at a temperature within range of about 400 degrees Celsius to about 500 degrees Celsius.

Abstract: A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

Abstract: Methods for selectively depositing a metal silicide layer are provided herein.

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof, a contact electrically connected to the source/drain region, the contact including a lower portion provided in the recess region, and a metal silicide layer provided at a lower region of the recess region and between the source/drain region and the contact.

Abstract: A method for depositing a metal film onto a substrate is disclosed. In particular, the method comprises pulsing a metal halide precursor onto the substrate and pulsing a decaborane precursor onto the substrate. A reaction between the metal halide precursor and the decaborane precursor forms a metal film, specifically a metal boride.

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a first passivation layer on the first III-V compound layer, a source region and a drain region. The source region penetrates the first passivation layer to electrically contact the first III-V compound layer. The drain region penetrates the first passivation layer to electrically contact the first III-V compound layer. A sidewall of the first passivation layer contacting with the source region comprises a stair shape.

Abstract: A nanowire comprises a source region, a drain region and a channel region. The source region is modified to reduce the lifetime of minority carriers within the source region. In an embodiment the modification may be performed by implanting either amorphizing dopants or lifetime reducing dopants. Alternatively, the source may be epitaxially grown with a different materials or process conditions to reduce the lifetime of minority carriers within the source region.

Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.