Abstract: A method for forming a metal silicide. The method comprises: providing a substrate having a fin, a gate formed on the fin, and spacers formed on opposite sides of the gate; depositing a Ti metal layer; siliconizing the Ti metal layer; and removing unreacted Ti metal layer. As the Ti atoms have relatively stable characteristics, diffusion happens mostly to Si atoms while the Ti atoms rarely diffuse during the thermal annealing. As a result, current leakage can be prevented in a depletion region and thus leakage current of the substrate can be reduced.

Abstract: A method of arranging at least one carbon nanotube on a semiconductor substrate includes depositing the at least one carbon nanotube on a dielectric layer of the semiconductor device. The method further includes arranging the at least one carbon nanotube on the dielectric layer in response to applying a voltage potential to an electrically conductive electrode of the semiconductor device, and applying a ground potential to an electrically conductive semiconductor layer of the semiconductor device.

Abstract: A method for depositing a metal boride film onto a substrate is disclosed. In particular, the method comprises pulsing a metal halide precursor onto the substrate and pulsing a boron compound precursor onto the substrate. A reaction between the metal halide precursor and the boron compound precursor forms a metal boride film. Specifically, the method discloses forming a tantalum boride (TaB2) or a niobium boride (NbB2) film.

Abstract: A fin-type field effect transistor including a substrate, insulators, a gate stack, a seal spacer, a first offset spacer, and a second offset spacer is described. The substrate has fins thereon. The insulators are located over the substrate and between the fins. The gate stack is located over the fins and over the insulators. The seal spacer is located over the sidewall of the gate stack. The first offset spacer is located over the seal spacer. The second offset spacer is located over the first offset spacer.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes forming a source/drain structure in a substrate and forming a metal layer over the source/drain structure. The method for manufacturing a semiconductor structure further includes performing an annealing process such that a portion of the metal layer reacts with the source/drain structure to form a metallic layer on the source/drain structure. The method for manufacturing a semiconductor structure further includes performing an etching process to remove an unreacted portion of the metal layer on the metallic layer and forming a contact over the metallic layer. In addition, the etching process includes using an etching solvent, and the etching solvent includes (a) a first component, including H2SO4, HCl, HF, H3PO4, or NH4OH and (b) a second component, including propylene carbonate, ethylene carbonate, diethyl carbonate, acetonitrile, or a combination thereof.

Abstract: Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device can include at least two sources; at least two memory arrays respectively formed over and coupled to the at least two sources; and a source conductor electrically respectively coupled to the at least two sources using source contacts adjacent one or more edges of the source. Each of the at least two memory arrays can include memory cells, control gates, and data lines. There is no data line between an edge of a source and the source contacts adjacent the edge.

Abstract: A vertical fuse element, including, a conductive silicide base on a surface of a substrate, and a conductive silicide pillar extending in a direction perpendicular to the surface of the substrate, where the conductive silicide pillar is on the conductive silicide base, and wherein the conductive silicide pillar includes an upper portion having a width, W5, a base having a width, W6, and a neck region having a width, W7, where W7<W5, and W7?W6.

Abstract: In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD.

Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

Abstract: Methods of fabricating a semiconductor device include forming a gate pattern on a substrate, forming spacers to cover both sidewalls of the gate pattern, forming an interlayer insulating layer to cover the gate pattern and the spacers, and forming contact holes to penetrate the interlayer insulating layer and expose sidewalls of the spacers. The forming of the spacers includes forming a spacer layer to cover the gate pattern and injecting silicon ions into the spacer layer. The spacer layer is a nitride-based low-k insulating layer, whose dielectric constant is lower than that of silicon oxide.

Abstract: A method of forming a semiconductor device includes forming a fin on a substrate and forming a source/drain region on the fin. The method further includes forming a doped metal silicide layer on the source/drain region and forming a super-saturated doped interface between the doped metal silicide and the source/drain region. An example benefit includes reduction of contact resistance between metal silicide layers and source/drain regions.

Abstract: Processes are provided for selectively depositing a metal silicide material on a first H-terminated surface of a substrate relative to a second, different surface of the same substrate. In some aspects, methods of forming a metal silicide contact layer for use in integrated circuit fabrication are provided.

Abstract: An anode active material for a lithium secondary battery, the anode active material including a metal silicide core, a silicon shell disposed on the core, and a metal nitride disposed on a surface of the silicon shell opposite the core.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a front surface and a back surface; forming a transition metal layer on a surface of the semiconductor substrate; and exposing the semiconductor substrate having the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves, to cause the transition metal layer to generate heat. During exposure of the semiconductor substrate, a portion of the semiconductor substrate contacting the transition metal layer is heated by a transfer of heat from the transition metal layer and, at an interface of the transition metal layer and the semiconductor substrate, an ohmic contact is formed by reaction of the transition metal layer and the semiconductor substrate, such as to form a transition metal silicide when the semiconductor substrate is silicon carbide. The ohmic contact provides a lower contact resistivity and device properties can be prevented from degrading.

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure with a source and a channel over the substrate; forming a spacer over the vertical structure; etching a portion of the spacer to expose the source; forming a first metal layer over the vertical structure; and thermal annealing the first metal layer to form a bottom silicide penetrating the source; and substantially removing the spacer.

Abstract: An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel dielectric layer includes at least one trench to the at least one contact surface of the electrical device. A conformal titanium liner is present on the sidewalls of the trench and is in direct contact with the at least one contact surface. The conformal titanium liner may be composed of 100 wt. % titanium, and may have a thickness ranging from 10 ? to 100 ?.

Abstract: A semiconductor structure includes a semiconductor substrate, at least one dielectric layer, a dielectric spacer liner (DSL) layer, and at least one conductor. The dielectric layer is present on the semiconductor substrate. The dielectric layer has at least one contact hole exposing at least a portion of the semiconductor substrate. The semiconductor substrate has at least one recess communicating with the contact hole. The recess has a bottom surface and at least one sidewall. The DSL layer is present on at least the sidewall of the recess. The conductor is present at least partially in the contact hole and is electrically connected to the semiconductor substrate.

Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

Abstract: A method includes performing a first sputtering to form a first metal film on a surface of a semiconductor region. The first sputtering is performed using a first ion energy. The method further includes performing a second sputtering to form a second metal film over and contacting the first metal film, wherein the first and the second metal films includes a same metal. The second sputtering is performed using a second ion energy lower than the first ion energy. An annealing is performed to react the first and the second metal films with the semiconductor region to form a metal silicide.

Abstract: A transistor, an integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the transistor includes a source electrode, at least one semiconductor channel, a gate electrode, a drain electrode, and a drain pad. The source electrode is disposed in a substrate. The semiconductor channel extends substantially perpendicular to the source electrode. The gate electrode surrounds the semiconductor channel. The drain electrode is disposed on top of the semiconductor channel. The drain pad is disposed on the drain electrode, wherein the drain pad comprises a single implanted silicide layer or a multiple conductive layers with the implanted silicide layer.

Abstract: A semiconductor device includes a gate arranged on a substrate; a source/drain formed on the substrate adjacent to the gate; a source/drain contact extending from the source/drain and through an interlayer dielectric (ILD) over the source/drain, a portion of the source/drain positioned adjacent to the source/drain contact; and a silicide positioned along a sidewall of the source/drain contact between the portion of the source/drain and the source/drain contact, and along an endwall of the source/drain contact between the source/drain contact and the substrate.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a third type region including a third conductivity type that is opposite the first conductivity type, the third type region covering the first type region. The semiconductor device includes a fourth type region including a fourth conductivity type that is opposite the second conductivity type, the fourth type region covering the second type region. The semiconductor device includes a channel region extending between the third type region and the fourth type region.

Abstract: A contact process for a semiconductor device is described. A substrate having a doped region and a dielectric layer over the doped region is provided. A contact hole is formed through the dielectric layer and exposing the doped region. An insulating liner layer is formed a in the contact hole. A portion of the insulating liner layer at a bottom of the contact hole is etch-removed and over-etching is performed. A conductive epitaxial layer is formed from the doped region in the contact hole, and then the contact hole is filled with a conductive material.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a gate stack on a semiconductor substrate. In some embodiments, the semiconductor device further includes a semiconductor element, such as for example, a resistor, on the semiconductor substrate. The semiconductor device includes a metal silicide layer on at least one of the gate stack, the source region, and the drain region. The semiconductor device also includes a blocking region in a portion of the semiconductor element. In some embodiments, the blocking region includes first dopants and second dopants with an atomic radius smaller than that of the first dopants.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. The disclosed method comprises forming a wedge-shaped recess with an initial bottom surface in the substrate; transforming the wedge-shaped recess into an enlarged recess with a height greater than the height of the wedge-shaped recess; and epitaxially growing a strained material in the enlarged recess.

Abstract: An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. The electronic device and the method of fabricating the same according to embodiments of the disclosed technology may have improved variable resistance characteristics.

Abstract: A semiconductor device includes a plasma-enhanced chemical vapor deposition (PECVD) protective layer configured to prevent failure of the semiconductor device throughout a temperature humidity with bias (THB) test exceeding about 1000 hours and/or a highly accelerated stress test (HAST) exceeding about 96 hours. Including a PECVD protective layer capable of protecting the semiconductor device throughout a THB test exceeding about 1000 hours and/or a HAST exceeding about 96 hours results in an extremely robust device, while providing the protective layer via PECVD results in convenience and cost savings.

Abstract: A self-limiting selective epitaxy process can be employed on a plurality of semiconductor fins such that the sizes of raised active semiconductor regions formed by the selective epitaxy process are limited to dimensions determined by the sizes of the semiconductor fins. Specifically, the self-limiting selective epitaxy process limits growth of the semiconductor material along directions that are perpendicular to crystallographic facets formed during the selective epitaxy process. Once the crystallographic facets become adjoined to one another or to a dielectric surface, growth of the semiconductor material terminates, thereby preventing merger among epitaxially deposited semiconductor materials.

Abstract: A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

Abstract: A semiconductor device including a nonvolatile memory cell and a field effect transistor together is improved in performance. In a method of manufacturing a semiconductor device, a hydrogen-containing insulating film is formed before heat treatment of a semiconductor wafer, the hydrogen-containing insulating film covering a gate electrode and agate insulating film in a region that will have a memory cell therein, and exposing a region that will have therein a MISFET configuring a peripheral circuit. Consequently, hydrogen in the hydrogen-containing insulating film is diffused into an interface between the gate insulating film and the semiconductor substrate, and thereby a defect at the interface is selectively repaired.

Abstract: A semiconductor fin fabrication method includes: providing a substrate; selectively epitaxially growing a first mask layer in a predetermined zone on the substrate; selectively epitaxially growing a first epitaxial layer on the substrate by using the first mask layer as a mask; and removing the first mask layer and a part, under the first mask layer, of the substrate by using the first epitaxial layer as a mask and by using an anisotropic etching method, so as to form a fin under the first epitaxial layer. According to the foregoing solutions, a manner in which a selective epitaxial growth technology and an anisotropic etching technology are combined is used It can be ensured that a semiconductor fin and a surface of a gate oxidized layer are perpendicular to each other, roughness of a surface of the semiconductor fin is reduced, and a fin with a smooth side surface is formed.

Abstract: A method of forming a metal silicide layer can include implanting dopants to a first depth below a surface of a semiconductor substrate including an active area. A metal-silicon composite layer can be formed on the semiconductor substrate and the metal-silicon composite layer can be silicided to form the metal silicide layer on the active area.

Abstract: The present invention provides a method for forming a semiconductor device, including the following steps: first, a substrate is provided, at least one gate is formed on the substrate, a contact etching stop layer (CESL) and a first dielectric layer are formed on the substrate in sequence, afterwards, a first etching process is performed to remove the first dielectric layer, and to expose a top surface and at least one sidewall of the etching stop layer, next, a second etching process is performed to partially remove the contact etching stop layer, and to form at least one epitaxial recess in the substrate. Afterwards, an epitaxial process is performed, to form an epitaxial layer in the epitaxial recess, and a contact structure is then formed on the epitaxial layer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

Abstract: In described examples, a MEMS device is formed by forming a sacrificial layer over a substrate and forming a first metal layer over the sacrificial layer. Subsequently, the first metal layer is exposed to an oxidizing ambient which oxidizes a surface layer of the first metal layer where exposed to the oxidizing ambient, to form a native oxide layer of the first metal layer. A second metal layer is subsequently formed over the native oxide layer of the first metal layer. The sacrificial layer is subsequently removed, forming a released metal structure.

Abstract: There is provided a method of manufacturing a semiconductor device. The method of manufacturing comprises a film formation process of forming a molybdenum layer that is mainly made of molybdenum (Mo), on at least one of a semiconductor layer, an insulating film and an electrode in the semiconductor device; a heat treatment process of heating the molybdenum layer at temperature of not lower than 200° C.; and a dry etching process of processing the semiconductor device that includes the formed molybdenum layer by dry etching, subsequent to the heat treatment process.

Abstract: Methods for depositing cobalt in features of a substrate include providing a substrate to a process chamber, the substrate having a first surface, a feature formed in the first surface comprising an opening defined by one or more sidewalls, a bottom surface, and upper corners, and the substrate having a first layer formed atop the first surface and the opening, wherein a thickness of the first layer is greater proximate the upper corners of the opening than at the sidewalls and bottom of the opening; exposing the substrate to a plasma formed from a silicon-containing gas to deposit a silicon layer predominantly onto a portion of the first layer atop the first surface of the substrate; and depositing a cobalt layer atop the substrate to fill the opening, wherein the silicon layer inhibits deposition of cobalt on the portion of the first layer atop the first surface of the substrate.

Abstract: A method of fabricating a fin field effect transistor (FinFET) includes forming a first fin and a second fin extending upward from a substrate major surface to a first height, forming an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, selectively forming a bulbous epitaxial layer covering a portion of each fin, annealing the substrate to convert at least a portion of the bulbous epitaxial layer to silicide and depositing a metal layer at least in the cavity. The first fin and the second fin are adjacent. A portion of the first fin and a portion of the second fin extend beyond the top surface of the insulation layer. The bulbous epitaxial layer defines an hourglass shaped cavity between adjacent fins.

Abstract: Methods for depositing or forming a metal silicide layer are disclosed. A metal halide layer is deposited, cleaned by a halogen and subjected to a siliciding agent to form the metal silicide.

Abstract: According to various embodiments, a method for processing a carrier may include: co-depositing at least one metal from a first source and carbon from a second source over a surface of the carrier to form a first layer; forming a second layer over the first layer, the second layer including a diffusion barrier material, wherein the solubility of carbon in the diffusion barrier material is less than in the at least one metal; and forming a graphene layer at the surface of the carrier from the first layer by a temperature treatment.

Abstract: An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer.

Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed over a portion of the fin structure. The gate structure traverses the fin structure and separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween. The source and drain region of the fin structure include a strained source and drain feature. The strained source feature and the strained drain feature each include: a first portion having a first width and a first depth; and a second portion disposed below the first portion, the second portion having a second width and a second depth. The first width is greater than the second width, and the first depth is less than the second depth.

Abstract: One aspect of the disclosure relates to a contact within a dielectric layer to a source/drain terminal of a field-effect-transistor (FET). The contact may include: a titanium-tantalum-silicide at a surface of the source/drain terminal; a barrier layer over the titanium-tantalum-silicide; and a metal over the barrier layer and extending to a top surface of the dielectric layer.

Abstract: A barrier metal is formed from a surface of an interlayer insulating film 2 to a trench that is formed in a semiconductor portion exposed in a contact hole. After RTA treatment and a plasma nitriding process, a plug is embedded at an inner side of the barrier metal inside the trench and the contact hole. The RTA treatment is performed at a temperature range of about 500 degrees C. to 650 degrees C. The plasma nitriding process is performed at a temperature lower than that of the RTA treatment. The barrier metal is formed by a first metal film of titanium and a second metal film of titanium nitride sequentially stacked. The plug is formed from tungsten. A surface electrode formed of aluminum is formed from a surface of the second metal film on the interlayer insulating film to a surface of the plug.

Abstract: A method of forming a contact structure is provided. A silicon-containing substrate is provided with a composite dielectric layer formed thereon. An opening penetrates through the composite dielectric layer and exposes a portion of the source/drain region. A titanium nitride layer is formed in the opening, and the titanium nitride layer is in contact with the exposed portion of the source/drain region. The titanium nitride layer is annealed, so that the bottom portion of the titanium nitride layer is partially transformed into a titanium silicide layer. A conductive layer is formed to fill up the opening.

Abstract: A semiconductor device and method of forming the same are described. A semiconductor device includes an active area adjacent a gate structure. The gate structure includes a gate electrode over a gate dielectric, the gate dielectric having a bottom surface in a first plane. A second etch interacts with a first composition and an initial dopant to remove a bottom portion of a first sidewall spacer adjacent the gate structure, such that a bottom surface of the first sidewall spacer lies in a second plane different than the first plane. The removal of the bottom portion of the first sidewall spacer reduces a first distance between a source or drain and a bottom surface of the gate electrode, thus reducing proximity loading of the semiconductor device and improving functionality of the semiconductor device.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including an n-type field effect transistor (N-FET) region, a p-type FET (P-FET) region, and an insulating material disposed over the N-FET region and the P-FET region. The method includes patterning the insulating material to expose a portion of the N-FET region and a portion of the P-FET region, and forming an oxide layer over the exposed portion of the N-FET region and the exposed portion of the P-FET region. The oxide layer over the P-FET region is altered, and a metal layer is formed over a portion of the N-FET region and the P-FET region. The workpiece is annealed to form a metal-insulator-semiconductor (MIS) tunnel diode over the N-FET region and a silicide or germinide material over the P-FET region.

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In some embodiments, a first precursor forms a layer on the first surface and is subsequently reacted or converted to form a metallic layer. The deposition temperature may be selected such that a selectivity of above about 50% or even about 90% is achieved.

Abstract: A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, a metal gate stack, and an insulating layer formed over the semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate. The metal gate stack is between the source region and the drain region. The insulating layer surrounds the metal gate stack. The method includes forming contact openings passing through the insulating layer to expose the source region and the drain region, respectively. The method includes performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region exposed by the contact openings. The method includes after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings. The dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively.