Abstract: In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.

Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.

Abstract: An integrated circuit structure and a method of forming the same are provided. The method includes providing a surface; performing an ionized oxygen treatment to the surface; forming an initial layer comprising silicon oxide using first process gases comprising a first oxygen-containing gas and tetraethoxysilane (TEOS); and forming a silicate glass over the initial layer. The method may further include forming a buffer layer using second process gases comprising a second oxygen-containing gas and TEOS, wherein the first and the second process gases have different oxygen-to-TEOS ratio.

Abstract: A metal line having a MoxSiy/Mo diffusion barrier of a semiconductor device and corresponding methods of fabricating the same are presented. The metal line includes an insulation layer, a diffusion barrier, and a metal layer. The insulation layer is formed on a semiconductor substrate and has a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a stack structure composed of a MoxSiy layer and a Mo layer. The metal layer is formed on the diffusion barrier which fills in the metal line forming region of the insulation layer.

Abstract: A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second heating temperature in an oxidizing atmosphere under a second pressure in a second process chamber to selectively oxidize at least a surface of the metal film on the element isolating insulation film and form a metal oxide film; conducting third heating processing at a third heating temperature which is higher than the first heating temperature and the second heating temperature in an atmosphere in a third process chamber to increase a concentration of silicon in the silicide film; and selectively removing the metal oxide film and an unreacted part of the metal film on the element isolating insulation film.

Abstract: A method including: making a structure on a substrate, said structure comprising at least a portion of a semiconductor material forming a channel of a field effect transistor, a gate located on the channel; forming at least one dielectric portion completely covering said structure and zones of the substrate corresponding to locations of a source and a drain of the field effect transistor; making two holes in the dielectric portion on each side of said structure, such that the locations of the source and the drain form bottom walls of the two holes and sides of the channel are exposed; depositing a first metallic layer on at least the bottom walls of the two holes, at least covering said sides of the channel; and depositing a second metallic layer on the first metallic layer-to form the source and the drain of the field effect transistor.

Abstract: A method is provided for forming a metal semiconductor alloy that includes providing a deposition apparatus that includes a platinum source and a nickel source, wherein the platinum source is separate from the nickel source; positioning a substrate having a semiconductor surface in the deposition apparatus; forming a metal alloy on the semiconductor surface, wherein forming the metal alloy comprises a deposition stage in which the platinum source deposits platinum to the semiconductor surface at an initial rate at an initial period that is greater than a final rate at a final period of the deposition stage, and the nickel source deposits nickel to the semiconductor surface; and annealing the metal alloy to react the nickel and platinum with the semiconductor substrate to provide a nickel platinum semiconductor alloy.

Abstract: Provided is a method for manufacturing a dual gate in a semiconductor device. The method includes forming a gate insulating layer and a gate conductive layer on a semiconductor substrate, forming a diffusion barrier layer on the gate conductive layer, forming a barrier metal layer on the diffusion barrier layer, depositing a first gate metal layer on the barrier metal layer, forming a metal nitride barrier layer on a surface of the first gate metal layer by supplying nitrogen (N2) plasma on the first gate metal layer, forming a second gate metal layer on the metal nitride barrier layer, and forming a hard mask layer on the second gate metal layer.

Abstract: A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer has a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier includes a stack structure including an MoxSiyNz layer and an Mo layer. A metal layer is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.

Abstract: A semiconductor device manufacturing method has forming a metal film containing platinum by depositing a metal on a source/drain diffusion layer primarily made of silicon formed on a semiconductor substrate and on a device isolation insulating film; forming a silicide film by silicidation of an upper part of the source/drain diffusion layer by causing a reaction between silicon in the source/drain diffusion layer and the metal on the source/drain diffusion layer by a first heating processing; forming a metal oxide film by a oxidation processing to oxidize selectively at least a surface of the metal film on the device isolation insulating film; increasing the concentration of silicon in the silicide film by a second heating processing; and selectively removing the metal oxide film and an unreacted part of the metal film on the device isolation insulating film.

Abstract: Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.

Abstract: Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.

Abstract: A formation method of a metallic compound layer includes preparing, in a chamber, a substrate having a surface on which a semiconductor material of silicon, germanium, or silicon germanium is exposed, and forming a metallic compound layer, includes: supplying a raw material gas containing a metal for forming a metallic compound with the semiconductor material to the chamber; heating the substrate to a temperature at which the raw material gas is pyrolyzed; and forming a metallic compound layer by reaction of the metal with the semiconductor material so that no layer of the metal is deposited on the substrate. A manufacturing method of a semiconductor device employs this formation method of a metallic compound layer.

Abstract: A method for forming a semiconductor device decouples NMOS and PMOS silicide processing and thereby allows independent optimization of at least one characteristic of both NMOS and PMOS devices, and eliminates constraints of using the same silicide process for both NMOS and PMOS, which limits the degree to which the process can be optimized for either technology.

Abstract: Techniques for manufacturing a CMOS image sensor are provided. A semiconductor substrate is provided, and at least one isolation region can be formed between a periphery region of the substrate and a photo-sensing region of the substrate. A first well in the periphery region and a second well in the photo-sensing region of the substrate are formed. A third well associated with a photodiode is also formed. A gate oxide layer, polysilicon layer, and first metal layer are respectively deposited. The polysilicon layer and first metal layer are etched to form an least one gate in the photo-sensing region and at least one gate in the periphery region. At least two doped regions in the first well are formed, as well as a doped region in the second well. A silicide block layer is deposited over the photo-sensing region of the substrate. A second metal layer is deposited at least over the periphery region after deposition of the silicide block. The substrate is exposed to a thermal environment to form silicide.

Abstract: Embodiments of the invention generally provide methods for forming cobalt silicide. In one embodiment, a method for forming a cobalt silicide material includes exposing a substrate having a silicon-containing material to either a wet etch solution or a pre-clean plasma during a first step and then to a hydrogen plasma during a second step of a pre-clean process. The method further includes depositing a cobalt metal layer on the silicon-containing material by a CVD process, heating the substrate to form a first cobalt silicide layer comprising CoSi at the interface of the cobalt metal layer and the silicon-containing material during a first annealing process, removing any unreacted cobalt metal from the substrate during an etch process, and heating the substrate to form a second cobalt silicide layer comprising CoSi2 during a second annealing process.

Abstract: A semiconductor structure in which the contact resistance in the contact opening is reduced as well as a method of forming the same are provided. This is achieved in the present invention by replacing conventional contact metallurgy, such as tungsten, or a metal silicide, such as Ni silicide or Cu silicide, with a metal germanide-containing contact material. The term “metal germanide-containing” is used in the present application to denote a pure metal germanide (i.e., MGe alloy) or a metal germanide that includes Si (i.e., MSiGe alloy).

Abstract: Silicon containing substrates are coated with nickel. The nickel is coated with a protective layer and the combination is heated to a sufficient temperature to form nickel silicide. The nickel silicide formation may be performed in oxygen containing environments.

Abstract: A method for fabricating an image sensor. The method may include forming a gate, a photo diode, and a floating diffusion region on a pixel region of a semiconductor substrate; forming an oxide film on the pixel region and on an edge region of the semiconductor substrate; forming a sacrificial oxide layer by etching the oxide film using a first photoresist pattern as a mask; forming a metal layer on the first photoresist pattern, the gate, and the floating diffusion region; forming a salicide layer on the gate and the floating diffusion region; etching a remaining non-salicided portion of the metal layer, the first photoresist pattern, and the sacrificial oxide layer; forming an interlayer insulating film on the semiconductor substrate and planarizing the interlayer insulating film; and forming contact holes and forming an edge open part by etching the interlayer insulating film using a second photoresist pattern as a mask.

Abstract: A method for forming silicide in a semiconductor device includes simultaneously performing a cleaning process and an etching process to remove a silicide metal layer if an excessive delay in time lapses after forming the silicide metal layer. This may prevent the occurrence of liquid marks due to an oxidation reaction at an interface of the semiconductor substrate in contact with the silicide metal layer, thereby preventing silicide defects due to the excessive delay.

Abstract: One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the p-type polysilicon has a first depth as measured from a top surface of the p-type polysilicon. An n-type dopant is implanted into the p-type polysilicon to form a counter-doped layer at the top-surface of the p-type polysilicon, where the counter-doped layer has a second depth that is less than the first depth. A catalyst metal is provided that associates with the counter-doped layer to form a catalytic surface. A metal is deposited over the catalytic surface. A thermal process is performed that reacts the metal with the p-type polysilicon in the presence of the catalytic surface to form a metal silicide. Other methods and devices are also disclosed.

Abstract: First, in a first step, a gate electrode is formed over a silicon substrate, with a gate insulation film therebetween. Next, in a second step, etching with the gate electrode as a mask is conducted so as to dig down a surface layer of the silicon substrate. Subsequently, in a third step, a first layer including an SiGe layer is epitaxially grown on the dug-down surface of the silicon substrate. Next, in a fourth step, a second layer including an SiGe layer lower than the first layer in Ge concentration or including an Si layer is formed on the first layer. Thereafter, in a fifth step, at least the surface side of the second layer is silicided, to form a silicide layer.

Abstract: A fabrication method of a semiconductor device includes: forming a gate insulating film and a gate electrode on an N type well; forming first source/drain regions by implanting a first element in regions of the N type well on both sides of the gate electrode, the first element being larger than silicon and exhibiting P type conductivity; forming second source/drain regions by implanting a second element in the regions of the N type well on the both sides of the gate electrode, the second element being smaller than silicon and exhibiting P type conductivity; and forming a metal silicide layer on the source/drain regions.

Abstract: A microelectronic device includes a metal gate with a metal gate upper surface. The metal gate is disposed in an interlayer dielectric first layer. The interlayer dielectric first layer also has an upper surface that is coplanar with the metal gate upper surface. A dielectric etch stop layer is disposed on the metal gate upper surface but not on the interlayer dielectric first layer upper surface.

Abstract: The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by physical vapor deposition, germanium atoms (120) and transition metal atoms (130) to form a metal-germanium alloy layer (140) on a semiconductor substrate (150). The metal-germanium alloy layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (400).

Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening by a metal deposition process employing a target which includes metal and silicon. The metal-silicide layer may then be annealed.

Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.

Abstract: A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second heating temperature in an oxidizing atmosphere under a second pressure in a second process chamber to selectively oxidize at least a surface of the metal film on the element isolating insulation film and form a metal oxide film; conducting third heating processing at a third heating temperature which is higher than the first heating temperature and the second heating temperature in an atmosphere in a third process chamber to increase a concentration of silicon in the silicide film; and selectively removing the metal oxide film and an unreacted part of the metal film on the element isolating insulation film.

Abstract: An integrated circuit structure and a method of forming the same are provided. The method includes providing a surface; performing an ionized oxygen treatment to the surface; forming an initial layer comprising silicon oxide using first process gases comprising a first oxygen-containing gas and tetraethoxysilane (TEOS); and forming a silicate glass over the initial layer. The method may further include forming a buffer layer using second process gases comprising a second oxygen-containing gas and TEOS, wherein the first and the second process gases have different oxygen-to-TEOS ratio.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.

Abstract: A method of forming an integrated circuit includes providing a semiconductor substrate and forming a gate over the semiconductor substrate. A gate sidewall spacer is formed around the gate and a resist is deposited on the gate sidewall spacer with the gate sidewall spacer and the gate exposed. A portion of the gate within the gate sidewall spacer is removed and a gate silicide is formed within the curved gate sidewall spacer. A dielectric layer is formed over the gate silicide and a contact is formed to the gate silicide.

Abstract: Embodiments of the invention provide an improved process for depositing tungsten-containing materials. The process utilizes soak processes and vapor deposition processes to provide tungsten films having significantly improved surface uniformity while increasing the production level throughput. In one embodiment, a method is provided which includes depositing a tungsten silicide layer on the substrate by exposing the substrate to a continuous flow of a silicon precursor while also exposing the substrate to intermittent pulses of a tungsten precursor. The method further provides that the substrate is exposed to the silicon and tungsten precursors which have a silicon/tungsten precursor flow rate ratio of greater than 1, for example, about 2, about 3, or greater. Subsequently, the method provides depositing a tungsten nitride layer on the tungsten suicide layer, depositing a tungsten nucleation layer on the tungsten nitride layer, and depositing a tungsten bulk layer on the tungsten nucleation layer.

Abstract: A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance.

Abstract: A method for forming a nickel silicide layer on a MOS device with a low carbon content comprises providing a substrate within an ALD reactor and performing an ALD process cycle to form a nickel layer on the substrate, wherein the ALD process cycle comprises pulsing a nickel precursor into the reactor, purging the reactor after the nickel precursor, pulsing a mixture of hydrogen and silane into the reactor, and purging the reactor after the hydrogen and silane pulse. The ALD process cycle can be repeated until the nickel layer reaches a desired thickness. The silane used in the ALD process functions as a getterer for the advantageous carbon, resulting in a nickel layer that has a low carbon content. The nickel layer may then be annealed to form a nickel silicide layer with a low carbon content.

Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

Abstract: A method for manufacturing a DRAM device on a silicon substrate includes: forming cell transistors in a memory cell area and other transistors in a peripheral circuit area; forming polysilicon plugs connected to diffused regions of the cell transistors and metallic plugs connected to diffused regions of the other transistors; heat treating at a temperature of 980 to 1,020 degrees C.; heat treating at a temperature of 700 to 850 degrees C.; implanting fluorine or boron fluoride into the diffused regions of the other transistors; and heat treating at a temperature of 500 to 850 degrees C.

Abstract: Techniques for manufacturing a CMOS image sensor are provided. A semiconductor substrate is provided, and at least one isolation region can be formed between a periphery region of the substrate and a photo-sensing region of the substrate. A first well in the periphery region and a second well in the photo-sensing region of the substrate are formed. A third well associated with a photodiode is also formed. A gate oxide layer, polysilicon layer, and first metal layer are respectively deposited. The polysilicon layer and first metal layer are etched to form an least one gate in the photo-sensing region and at least one gate in the periphery region. At least two doped regions in the first well are formed, as well as a doped region in the second well. A silicide block layer is deposited over the photo-sensing region of the substrate. A second metal layer is deposited at least over the periphery region after deposition of the silicide block. The substrate is exposed to a thermal environment to form silicide.

Abstract: A method of self-aligned silicidation involves interruption of the silicidation process prior to complete reaction of the blanket material (e.g., metal) in regions directly overlying patterned and exposed other material (e.g., silicon). Diffusion of excess blanket material from over other regions (e.g., overlying insulators) is thus prevented. Control and uniformity are insured by use of conductive rapid thermal annealing in hot wall reactors, with massive heated plates closely spaced from the substrate surfaces. Interruption is particularly facilitated by forced cooling, preferably also by conductive thermal exchange with closely spaced, massive plates.

Abstract: Nickel silicide is formed on the basis of a gaseous precursor, such as nickel tetra carbonyl, wherein the equilibrium of the decomposition of this gas may be controlled to obtain a highly selective nickel silicide formation rate. Moreover, any etch step for removing excess nickel may be avoided, since only minute amounts of nickel may form on exposed surfaces, which may then be effectively removed by correspondingly shifting the equilibrium. Consequently, reduced process complexity, enhanced controllability and enhanced tool lifetime may be obtained.

Abstract: A semiconductor device is fabricated by forming a gate electrode structure, comprising a gate oxide layer pattern, a polysilicon layer pattern, and sidewall spacers on a silicon substrate, forming source/drain regions on both sides of the gate electrode structure in the silicon substrate, depositing a physical vapor deposition (PVD) cobalt layer on the gate electrode structure using PVD, depositing a chemical vapor deposition (CVD) cobalt layer on the PVD cobalt layer using CVD, annealing the silicon substrate to react the PVD and CVD cobalt layers with polysilicon on an upper surface of the gate electrode structure, stripping at least a portion of the PVD cobalt layer and the CVD cobalt layer that has not reacted, and annealing the silicon substrate after stripping the at least the portion of the PVD cobalt layer and the CVD cobalt layer.

Abstract: A method for fabricating a semiconductor device is provided. A nickel layer is deposited on a semiconductor substrate and plasma-processed. Rapid thermal processing is performed on the plasma-processed nickel layer to form a nickel silicide layer. The portion of the nickel layer that has not reacted with silicon is then removed.

Abstract: Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance.

Abstract: A method of forming a wiring for a semiconductor memory device includes obtaining a semiconductor substrate, depositing at least one conductive layer on the semiconductor substrate under controlled conditions, such as substrate temperature and atmosphere temperature, to provide a conductive layer exhibiting a reduced surface roughness as compared to a comparable conductive layer deposited under uncontrolled conditions, and patterning the conductive layer to form a wiring.

Abstract: A metal line of a semiconductor device having a diffusion barrier including CrxBy and a method for forming the same is described. The metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer is formed having a metal line forming region. A diffusion barrier including a CrxBy layer is subsequently formed on the surface of the metal line forming region and the insulation layer. A metal line is finally formed to fill the metal line forming region of the insulation layer on the diffusion barrier including a CrxBy layer.

Abstract: Radical in a plasma generation chamber is supplied to a process chamber through an introducing aperture, and HF gas is supplied as a process gas from the vicinity of the radical introducing aperture. A native oxide film of the substrate surface of a IV group semiconductor doped an impurity is removed, with a good surface roughness equal to the wet cleaning. The substrate after the surface treatment is deposited with a metal material and metal silicide formation by thermal treatment is performed, and during these processes, the substrate is not exposed to the atmosphere, and a good contact resistance equal to or better than the wet process is obtained.

Abstract: Embodiments as described herein provide a method for depositing barrier layers and tungsten materials on substrates. In one embodiment, a method for depositing materials is provided which includes forming a barrier layer on a substrate, wherein the barrier layer contains a cobalt silicide layer and a metallic cobalt layer, exposing the barrier layer to a soak gas containing a reducing gas during a soak process, and forming a tungsten material over the barrier layer. In one example, the barrier layer may be formed by depositing a cobalt-containing material on a dielectric surface of the substrate and annealing the substrate to form the cobalt silicide layer from a lower portion of the cobalt-containing material and the metallic cobalt layer from an upper portion of the cobalt-containing material.

Abstract: The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate oxide layer, a conducting layer, and a first insulating layer. Sidewall spacers are formed adjacent to the sides of the gate stack structure and a third insulating layer is formed over the gate stack and substrate. The third insulating layer and first insulating layer are removed to expose the conducting layer and, at least one unetched metal-containing layer is formed over and in contact with the conducting layer. The gate stack structure then undergoes a siliciding process with different variations to finally form a silicide gate.

Abstract: The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 ?m.

Abstract: Methods of forming metal silicide layers include a convection-based annealing step to convert a metal layer into a metal silicide layer. These methods may include forming a silicon layer on a substrate and forming a metal layer (e.g., nickel layer) in direct contact with the silicon layer. A step is then performed to convert at least a portion of the metal layer into a metal silicide layer. This conversion step is includes exposing the metal layer to an inert heat transferring gas (e.g., argon, nitrogen) in a convection or conduction apparatus.

Abstract: A semiconductor substrate, a semiconductor chip and a semiconductor component with areas composed of a stressed monocrystalline material, and a method for production of a semiconductor component is disclosed. In one embodiment, the semiconductor chip includes relatively thick stressed layers achieving reduced switching times. For this purpose, the semiconductor substrate has one or more areas with extrinsic, permanent curvature, with the crystal structure K being compressed and/or widened and/or distorted in these areas.