Abstract: A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices.

Abstract: A method of forming a mask pattern includes a first pattern forming step of etching an anti-reflection coating film by using as a mask a first line portion made up of a photo resist film formed on the anti-reflection film to form a pattern including a second line portion made up of the photo resist film and the anti-reflection film; an irradiation step of irradiating the photo resist film with electrons; a silicon oxide film forming step to cover the second line portion isotropically; and an etch back step of etching back the silicon oxide film such that the silicon oxide film is removed from the top of the second line portion as sidewalls of the second line portion. The method further includes a second pattern forming step of ashing the second line portion to form a mask pattern including a third line portion made up of the silicon oxide film and remains.

Abstract: Elemental fluorine is used as etching agent for the manufacture of electronic devices, especially semiconductor devices, micro-electromechanical devices, thin film transistors, flat panel displays and solar panels, and as chamber cleaning agent mainly for plasma-enhanced chemical vapor deposition (PECVD) apparatus. For this purpose, fluorine often is produced on-site. The invention provides a process for the manufacture of electronic devices wherein fluorine is produced on site and is purified from HF by a low temperature treatment. A pressure of between 1.5 and 20 Bars absolute is especially advantageous.

Abstract: It is an object of the present invention to provide a manufacturing method of a semiconductor device where a semiconductor element is prevented from being damaged and throughput speed thereof is improved, even in a case of thinning or removing a supporting substrate after forming the semiconductor element over the supporting substrate.

Abstract: A process of forming a slit in a substrate is provided. A mask layer is formed on a substrate, wherein the mask layer does not include carbon. An etching process is performed to be substrate by using the mask layer as a mask, so as to form a slit in the substrate. The etching gas includes Cl2, CF4 and CHF3, a molar ratio of CF4 to CHF3 is about 0.5-0.8, and a molar ratio of F to Cl is about 0.4-0.8, for example. Further, the step of performing the etching process simultaneously removes the mask layer.

Abstract: A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.

Abstract: A process for manufacturing buried hetero-structure laser diodes includes the steps of forming a stacked semiconductor layer on a substrate; forming a mask layer on the stacked semiconductor layer; forming a semiconductor mesa by etching the stacked semiconductor layer through the mask layer; forming an overhang of the mask layer by selectively etching the stacked semiconductor layer of the semiconductor mesa; selectively growing a buried layer on a side surface of the semiconductor mesa while leaving the mask layer on the semiconductor mesa; forming a lateral portion of the buried layer, the lateral portion having a side surface adjacent to the side surface of the semiconductor mesa; after forming the lateral portion of the buried layer, removing the mask layer on the semiconductor mesa; and forming an electrode on a top surface of the semiconductor mesa and on the side surface of the lateral portion of the buried layer.

Abstract: A manufacturing method of a semiconductor substrate includes: forming a trench in a semiconductor board by a dry etching method; etching a surface portion of an inner wall of the trench by a chemical etching method so that a first damage layer is removed, wherein the surface portion has a thickness equal to or larger than 50 nanometers; and performing a heat treatment at temperature equal to or higher than 1050° C. in non-oxidizing and non-azotizing gas so that crystallinity of a second damage layer is recovered, wherein the second damage layer is disposed under the first damage layer.

Abstract: A fin Field Effect Transistor (finFET), an array of finFETs, and methods of production thereof. The finFETs are provided on an insulating region, which may optionally contain dopants. Further, the finFETs are optionally capped with a pad. The finFETs provided in an array are of uniform height.

Abstract: A high purity, non-toxic, environmentally friendly method for anisotropically etching single crystal silicon and etching polysilicon, suitable for microelectronics, optoelectronics and microelectromechanical (MEMS) device fabrication, using high purity aqueous ammonium hydroxide (NH4OH) solution generated at the point of use, is presented. The apparatus of the present invention supports generation of high purity aqueous NH4OH solution from ammonia NH3 gas dissolved into distilled/deionized water and maintained in equilibrium with an overpressure of NH3, within a hermetically enclosed chamber at the optimal temperature between 70-90° C., preventing evaporation of NH3 gas from aqueous NH4OH solution for achieving a high anisotropic etching rate. Other liquid anisotropic etching methods for silicon may use tetramethylammonium hydroxide (TMAH).

Abstract: A method for manufacturing an image sensor includes forming circuitry including a metal line over a semiconductor substrate, forming a photodiode over the metal line, and forming a contact plug in the photodiode such that the contact plug is connected to the metal line. The forming of the contact plug includes performing a first etch process to etch a portion of the photodiode, and performing a second etch process to expose a portion of the metal line by using a byproduct generated in etching, to form a via hole for the contact plug in the photodiode.

Abstract: A method for patterning an epitaxial substrate with nano-patterns, includes: forming a plurality of zinc oxide nano-particles on an epitaxial substrate; dry-etching the epitaxial substrate exposed from the zinc oxide nano-particles to form nano-patterns corresponding to the zinc oxide nano-particles; and removing the zinc oxide nano-particles on the epitaxial substrate. A method for forming a light-emitting diode having a patterned epitaxial substrate with the nano-patterns is also disclosed.

Abstract: Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate.

Abstract: A method of removing non-noble metal oxides from material (e.g., semiconductor material) used to make a microelectronic device includes providing the material comprising traces of the conducting non-noble metal oxides; applying a chemical mixture (or chemical solution) to the material; removing the traces of the non-noble metal oxides from the material; and removing the chemical mixture from the material. The non-noble metal oxides comprise MoOx, wherein x is a positive number between 0 and 3. The chemical solution comprises any one of HNO3-based chemicals, H2SO4-based chemicals, HCl-based chemicals, or NH4OH-based chemicals.

Abstract: In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.

Abstract: During the patterning of via openings in sophisticated metallization systems of semiconductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to exposed sidewall portions of the conductive cap layer, thereby establishing a protective material. Consequently, in a subsequent wet chemical etch process, the probability for undue material removal of the conductive cap layer may be greatly reduced.

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.

Abstract: In a manufacturing method of a semiconductor structure, a substrate having a front surface and a back surface is provided. The front surface has a device layer thereon and conductive plugs electrically connected to the device layer. A thinning process is performed on the back surface of the substrate, such that the back surface of the substrate and surfaces of the conductive plugs have a distance therebetween. Holes are formed in the substrate from the back surface to the conductive plugs, so as to form a porous film. An oxidization process is performed, such that the porous film correspondingly is reacted to form an oxide material layer. A polishing process is performed on the oxide material layer to expose the surfaces of the conductive plugs.

Abstract: A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.

Abstract: The present invention provides a method for removing polymer after etching a gate stack structure of high-K gate dielectric/metal gate. The method mainly comprises the following steps: 1): forming a gate stack structure of interface Si2/high-K gate dielectric/metal gate/poly-silicon/hard mask in sequence on a silicon substrate with device isolations formed thereon; 2): forming a resist pattern by the lithography; 3): etching the gate stack structure; and 4): immersing the resultant structure of the step 3) in an etching solution to remove the polymer, wherein the etching solution consists of HF, HCl and water, the ratio of HF by volume is 0.2˜1% and the ratio of HCl by volume is 5˜15%.

Abstract: A method includes forming a cavity in a substrate, depositing a layer of conductive material in the cavity and over exposed portions of the substrate, removing portions of the conductive material to expose portions of the substrate using a planarizing process, and removing residual portions of the conductive material disposed on the substrate using a reactive ion etch (RIE) process.

Abstract: Methods and structure are provided for creating and utilizing hard masks to facilitate creation of a grating effect to control an anisotropic etching process for the creation of an opening, and subsequent formation of a interconnect structure (e.g., a via) in a multilayered semiconductor device. A first hard mask can be patterned to control etching in a first dimension, and a second hard mask can be patterned to control etching in a second dimension, wherein the second hard mask is patterned orthogonally opposed to the first hard mask. A resist can be patterned by inverting the pattern of a metal line patterning. Interconnects can be formed with critical dimension(s) and also self-aligned.

Abstract: A semiconductor process is disclosed. The semiconductor process includes the steps of: providing a substrate having a specific area defined thereon; and performing an etch process by using an etchant comprising H2O2 to etch the specific area for forming a recess.

Abstract: Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate.

Abstract: A non-polished glass wafer, a thinning system, and a method for using the non-polished glass wafer to thin a semiconductor wafer are described herein. In one embodiment, the glass wafer has a body (e.g., circular body) including a non-polished first surface and a non-polished second surface substantially parallel to each other. In addition, the circular body has a wafer quality index which is equal to a total thickness variation in micrometers plus one-tenth of a warp in micrometers that is less than 6.0.

Abstract: Pre-texturing composition for texturing silicon wafers having one or more surfactants. Methods of texturing silicon wafers having the step of wetting said wafer with a pre-texturing composition having one or more surfactants followed by a texturing step.

Abstract: A method for single side texturing of a crystalline semiconductor substrate (10) comprises: providing a substrate (10), for example a semiconductor substrate, comprising a first surface (12) and a second surface (14) opposite to one another with respect to the substrate (10); providing a masking layer (21) with a random pattern on the first surface (12) of the substrate (10); and etching the substrate (10) in a polishing solution, thereby texturing the first surface (12) of the substrate (10) and polishing the second surface (14) in a single wet etching step.

Abstract: A method for etching a metal gate stack is provided. The method includes forming a gate stack on a substrate, where the gate stack includes a metal gate. A wet etch process is performed on the gate stack. The wet etch process includes submersing the substrate with the gate stack in an aqueous solution composed of a wet etchant and an oxidizer, removing the substrate from the solution and rinsing the solution from the etched gate stack.

Abstract: A method for etching a metal gate stack is provided. The method includes forming a gate stack on a substrate, where the gate stack includes a metal gate. A wet etch process is performed on the gate stack. The wet etch process includes submersing the substrate with the gate stack in an aqueous solution composed of a wet etchant and an oxidizer, removing the substrate from the solution and rinsing the solution from the etched gate stack.

Abstract: A method for decapsulating an integrated circuit package without the need of using a mask during the decapsulation process is disclosed. First, a package is provided. The package includes at least a circuit element and a molding compound enclosing the circuit. Second, a caustic solution is simultaneously provided. The caustic solution is capable of etching the molding compound and intermittently contacts a pre-selected area of the molding compound to etch the molding compound. As a consequence, the caustic solution removes the molding compound in the pre-selected area so the circuit element in the package is substantially exposed.

Abstract: A liquid composition used to carry out crystal anisotropic etching of a silicon substrate provided with an etching mask formed of a silicon oxide film with the silicon oxide film used as a mask includes cesium hydroxide, an alkaline organic compound, and water.

Abstract: A manufacturing method for a semiconductor structure includes providing a substrate having at least a gate structure formed thereon, performing a first wet etching process to etch the substrate at two sides of the gate structure, performing a second wet etching process to etch the substrate to form a recess respectively at two sides of the gate structure, and performing a selective epitaxial growth method to form an epitaxial layer having a diamond shape with a flat bottom respectively in the recess.

Abstract: A method for decapsulating an integrated circuit package in the absence of a mask is disclosed. First, a package is provided. The package includes at least a circuit element and a molding compound enclosing the circuit. Second, a caustic solution is simultaneously provided and drained. The caustic solution is capable of etching the molding compound while in continuous contact with the molding compound to etch the molding compound. As a consequence, the molding compound is removed so that the circuit element in the package is substantially exposed.

Abstract: A method for producing a light-emitting device including a growth substrate made of Group III nitride semiconductor, and a Group III nitride semiconductor layer stacked on the top surface of the growth substrate, includes forming, between the growth substrate and the semiconductor layer, a stopper layer exhibiting resistance to a wet etchant, and wet-etching the bottom surface of the growth substrate until the stopper layer is exposed.

Abstract: A method for removing a plurality of dielectric materials from a supporting substrate by providing a substrate with a plurality of materials, contacting the substrate at a first temperature with a solution to more quickly remove a first dielectric material than a second dielectric materials at the first temperature, and then contacting the substrate at a second temperature with a solution to more quickly remove the second dielectric material than the first dielectric material at the second temperature. Thus, the dielectric materials exhibit different etch rates when etched at the first and second temperatures. The solutions to which the first and second dielectric materials are exposed may contain phosphoric acid. The first dielectric material may be silicon nitride and the second dielectric material may be silicon oxide. Under these conditions, the first temperature may be about 175° C., and the second temperature may be about 155° C.

Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises performing at least one etching process to reduce a thickness of a P-active region of a semiconducting substrate to thereby define a recessed P-active region, performing a process in a process chamber to selectively form an as-deposited layer of a semiconductor material on the recessed P-active region, wherein the step of performing the at least one etching process is performed outside of the process chamber, and performing an etching process in the process chamber to reduce a thickness of the as-deposited layer of semiconductor material.

Abstract: The present invention provides a method of patterning an electronic or photonic material on a substrate comprising: forming a film (polymer A) of said electronic or photonic material on said substrate; and using a fluoropolymer (e.g. cytop) to protect regions of said electronic or photonic material during a patterning process.

Abstract: A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer.

Abstract: A method of fabricating an integrated circuit device includes forming first and second patterns extending in first and second directions, respectively, on a target layer. The first patterns comprise a metal oxide and/or metal silicate material having an etch selectivity with respect to that of the target layer. The second patterns comprise a material having an etch selectivity with respect to those of the first patterns and the target layer. The target layer is selectively etched using the first patterns and the second patterns as an etch mask to define holes respectively extending through the target layer to expose a layer therebelow. At least one of the first and second patterns is formed using respective mask patterns formed by a photolithographic process, and the at least one of the first and second patterns have a finer pitch than that of the respective mask patterns.

Abstract: MEMS accelerometers have a substrate, and a proof mass portion thereof which is separated from the substrate surrounding it by a gap. An electrically-conductive anchor is coupled to the proof mass, and a plurality of electrically-conductive suspension anus that are separated from the proof mass extend from the anchor and are coupled to the substrate surrounding the proof mass. A plurality of sense and actuation electrodes are separated from the proof mass by gaps and are coupled to processing electronics. The fabrication methods use deep reactive ion etch bulk micromachining and surface micromachining to form the proof mass, suspension arms and electrodes. The anchor, suspension arms and electrodes are made in the same process steps from the same electrically conductive material, which is different from the substrate material.

Abstract: Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching material on a microfeature workpiece includes providing a microfeature workpiece including a doped oxide layer and a nitride layer adjacent to the doped oxide layer. The method include selectively etching the doped oxide layer with an etchant comprising DI:HF and an acid to provide a pH of the etchant such that the etchant includes (a) a selectivity of phosphosilicate glass (PSG) to nitride of greater than 250:1, and (b) an etch rate through PSG of greater than 9,000 ?/minute.

Abstract: Improved methods and apparatus for cleaning substrates and enhancing diffusion limited reaction at substrate surfaces use piezoelectric transducers operating in the gigasonic domain. The resonator assemblies include plural transducer stacks each including a thin film piezoelectric element coupled to a resonator plate that faces the substrate. At the disclosed frequencies and powers used, Eckart or Rayleigh streaming can be induced in a liquid treatment medium without substantial generation of cavitation.

Abstract: In a method for processing monocrystalline silicon wafers, which are transported while lying flat along a horizontal transport path, etching solution for texturing the surface is applied from above by means of nozzles or the like. The etching solution is applied from above several times in succession onto the upper side of the silicon substrates, remains there and reacts with the silicon substrate.

Abstract: A device made of single-crystal silicon having a first side, a second side which is situated opposite to the first side, and a third side which extends from the first side to the second side, the first side and the second side each extending in a 100 plane of the single-crystal silicon, the third side extending in a first area in a 111 plane of the single-crystal silicon. The third side extends in a second area in a 110 plane of the single-crystal silicon. Furthermore, a production method for producing a device made of single-crystal silicon is described.

Abstract: By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions.

Abstract: The method for producing a resin package according to the present invention includes a step of forming a copper oxide layer by oxidizing the surface of a lead frame in which at least the surface is made of copper, and a step of forming a resin package main unit by allowing a resin to adhere to the copper oxide layer on the lead frame surface by resin molding for package, and then removing a predetermined area of the copper oxide layer with an acidic solution.

Abstract: Disclosed are an etchant which is used for the manufacture of a semiconductor device using a semiconductor substrate having an electrode and which is capable of selectively etching copper without etching nickel, and a method for manufacturing a semiconductor device using the same. Specifically disclosed are an etchant to be used for the manufacture of a semiconductor device using a semiconductor substrate having an electrode, including hydrogen peroxide, an organic acid, and an organic phosphonic acid, wherein the organic acid is at least one member selected from citric acid and malic acid; a content of hydrogen peroxide is from 0.75 to 12% by mass; a content of the organic acid is from 0.75 to 25% by mass; and a content of the organic phosphonic acid is from 0.0005 to 1% by mass, and a method for manufacturing a semiconductor device using the etchant.

Abstract: A method of manufacturing a ridge-type semiconductor laser includes the steps of forming a stacked semiconductor layer including an active layer and an etch stop layer on first and second surfaces of a substrate, etching the stacked semiconductor layer on the second surface, forming a semiconductor portion on the second surface, forming a ridge waveguide portion by etching the stacked semiconductor layer on the first surface to a first depth, forming semiconductor diffraction grating portions by etching the semiconductor portion to a second depth, and forming a diffraction grating section by providing resin diffraction grating portions between the semiconductor diffraction grating portions. The etching of the stacked semiconductor layer on the first surface and the etching of the semiconductor portion are performed simultaneously by using first and second mask portions.

Abstract: Provided is a spin head for supporting and rotating a substrate. The spin head includes a body, chuck pins disposed at the body and movable between supporting positions and rest positions, and a chuck pin moving unit configured to move the chuck pins straight. The chuck pins supports a substrate at the supporting positions and provides a substrate loading/unloading space at the rest position. The chuck pin moving unit includes movable rods fixed to the chuck pins, a rotatable cam including protrusions on an outer surface thereof so as to move the chuck pins from the supporting positions to the rest positions, and chuck pin return units respectively applying forces to the movable rods so as to move the chuck pins individually from the rest positions to the supporting positions. The chuck pin moving unit further includes contact maintaining members.

Abstract: Disclosed is a technique for attaining high etching selectivity of a silicon nitride film to a silicon oxide film. The etching method includes a step of supplying a silylating agent to a substrate having a silicon nitride film and a silicon oxide film exposed on the surface thereof to thereby form a silylated film as a protective film over the surface of the silicon oxide film. After this step, an etching solution is supplied to the substrate. It is thus possible to selectively etch only the silicon nitride film.