Chemical Etching (epo) Patents (Class 257/E21.219)
  • Publication number: 20120231565
    Abstract: Provided is a process for producing a substrate for a liquid ejection head, including forming a liquid supply port in a silicon substrate, the process including the steps of (a) forming an etch stop layer at a portion of a front surface of the silicon substrate at which portion the liquid supply port is to be formed; (b) performing dry etching using a Bosch process from a rear surface side of the silicon substrate up to the etch stop layer with use of an etching mask formed on a rear surface of the silicon substrate to thereby form the liquid supply port; and (c) simultaneously removing the etch stop layer and a deposition film formed inside the liquid supply port.
    Type: Application
    Filed: March 5, 2012
    Publication date: September 13, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Toshiyasu Sakai
  • Publication number: 20120231607
    Abstract: A method for forming a silicon layer according to inventive concept comprises: preparing an SOI substrate; applying an etchant or vapor of the etchant to the SOI substrate; and irradiating a light to the SOI substrate.
    Type: Application
    Filed: November 29, 2011
    Publication date: September 13, 2012
    Applicant: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Taeyoon LEE, Ja Hoon KOO, Sang Wook LEE, Ka Young LEE
  • Publication number: 20120231632
    Abstract: This disclosure relates to an etching composition containing at least one sulfonic acid, at least one compound containing a halide anion, the halide being chloride or bromide, at least one compound containing a nitrate or nitrosyl ion, and water. The at least one sulfonic acid can be from about 25% by weight to about 95% by weight of the composition. The halide anion can be chloride or bromide, and can be from about 0.01% by weight to about 0.5% by weight of the composition. The nitrate or nitrosyl ion can be from about 0.1% by weight to about 20% by weight of the composition. The water can be at least about 3% by weight of the composition.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 13, 2012
    Applicants: FUJIFILM Corporation, Fujifilm Electronic Materials U.S.A., Inc.
    Inventors: Tomonori Takahashi, Tadashi Inaba, Atsushi Mizutani, Bing Du, William A. Wojtczak, Kazutaka Takahashi, Tetsuya Kamimura
  • Patent number: 8257549
    Abstract: Provided is a spin head for supporting a substrate. The spin head includes a rotatable body, and chuck pins protruding upward from the body and configured to support an edge of a substrate placed at the body when the body is rotated. Each of the chuck pins includes a vertical rod vertically disposed at the body, and a support rod extending from a side of the vertical rod and configured to make contact with the edge of the substrate placed at the body when the body is rotated. When the substrate is rotated, the vertical rod is spaced apart from the edge of the substrate. The contact portion includes a streamlined side surface. The support rod includes a contact portion. The contact portion tapers toward the end of the support rod when viewed from the top of the support rod.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: September 4, 2012
    Assignee: Semes Co., Ltd.
    Inventors: Woo-Seok Lee, Woo-Young Kim, Jeong-Yong Bae
  • Publication number: 20120214306
    Abstract: Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H2F2. The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride. A method is provided for producing an isolated capacitor, which can be used in a dynamic random access memory cell array, on a substrate using sacrificial layers selectively removed to expose outer surfaces of the bottom electrode.
    Type: Application
    Filed: April 30, 2012
    Publication date: August 23, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Kevin R. Shea
  • Publication number: 20120214309
    Abstract: A method of fabricating a SiC semiconductor device includes the steps of preparing a silicon carbide semiconductor including a first surface having impurities implanted at least partially, forming a second surface by dry etching the first surface of the silicon carbide semiconductor using gas including hydrogen gas, and forming an oxide film constituting the silicon carbide semiconductor device on the second surface.
    Type: Application
    Filed: February 23, 2011
    Publication date: August 23, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Satomi Itoh, Hiromu Shiomi, Yasuo Namikawa, Keiji Wada, Mitsuru Shimazu, Toru Hiyoshi
  • Publication number: 20120214267
    Abstract: The present invention relates to a novel method for roughening an epitaxy structure layer, including: providing an epitaxy structure layer; and etching a surface of the epitaxy structure layer by an excimer laser having an energy density of 1000 mJ/cm2 or less to form a roughened surface. In addition, the present invention further provides a method for manufacturing a light-emitting diode having a roughened surface. Accordingly, the present invention can resolve the conventional problems of process complexity, time consumption and high cost.
    Type: Application
    Filed: June 21, 2011
    Publication date: August 23, 2012
    Applicant: National Cheng Kung University
    Inventors: Shui-Jinn WANG, Wei-Chi Lee
  • Publication number: 20120208370
    Abstract: The invention relates to a method for etching of silicon surfaces with the following steps: Furnishing an aqueous alkaline hydrocolloid etching solution containing at least one hydrocolloid, at a temperature of 50° C. to 95° C., bringing the silicon surface in contact with the hydrocolloid etching solution for a specified duration, and Removing the hydrocolloid etching solution from the silicon surface.
    Type: Application
    Filed: June 2, 2010
    Publication date: August 16, 2012
    Applicant: RENA GmbH
    Inventors: Ahmed Abdelbar El Jaouhari, Jürgen Schweckendiek
  • Patent number: 8242026
    Abstract: Provided is a method for performing etching process or film forming process to a substrate W whereupon a prescribed pattern is formed with an opening. The method is provided with a step of mixing a liquid and a gas, at least one of which contains a component that contributes to the etching process or the film forming process, and generating charged nano-bubbles 85 having a diameter smaller than that of the opening formed on the semiconductor substrate W; a step of forming an electric field to attract the nano-bubbles onto the surface of the substrate W; and a step of performing the process by supplying the substrate with the liquid containing the nano-bubbles 85 while forming the electric field.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: August 14, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Sumie Nagaseki
  • Patent number: 8242025
    Abstract: According to a method of the present invention for manufacturing a semiconductor piece, at least two semiconductor layers (12) are first formed on a substrate (10) by stacking a sacrificial layer (11) and the semiconductor layer (12) on the substrate (10) in this order and repeating this stacking. Next, the semiconductor layers (12) are divided into pieces by etching part of the sacrificial layers (11) and part of the semiconductor layers (12). Then, the pieces are separated from the substrate by removing the sacrificial layers (11).
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: August 14, 2012
    Assignee: Panasonic Corporation
    Inventors: Takahiro Kawashima, Tohru Saitoh, Tohru Nakagawa, Hideo Torii
  • Patent number: 8236694
    Abstract: The present invention relates to a method for manufacturing an acceleration sensor. In the method, thin SOI-wafer structures are used, in which grooves are etched, the walls of which are oxidized. A thick layer of electrode material, covering all other material, is grown on top of the structures, after which the surface is ground and polished chemo-mechanically, thin release holes are etched in the structure, structural patterns are formed, and finally etching using a hydrofluoric acid solution is performed to release the structures intended to move and to open a capacitive gap.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: August 7, 2012
    Assignee: Valtion Teknillinen Tutkimuskeskus
    Inventors: Jyrki Kiihamäki, Hannu Kattelus
  • Patent number: 8236696
    Abstract: A method for fabricating a semiconductor device to enlarge a channel region is provided. The channel region is enlarged due to having pillar shaped sidewalls of a transistor. The transistor includes a fin active region vertically protruding on a substrate, an isolation layer enclosing a lower portion of the fin active region, and a gate electrode crossing the fin active region and covering a portion of the fin active region. An isolation layer is formed enclosing a lower portion of the fin active region and the isolation layer under the spacers is partially removed to expose a portion of the sidewalls of the fin active region. Subsequently, dry etching is performed to form the sidewalls having a pillar/neck.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: August 7, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Hee Cho
  • Publication number: 20120193764
    Abstract: The instant disclosure relates to a nanostructuring process for an ingot surface prior to the slicing operation. A surface treatment step is performed for at least one surface of the ingot in forming a nanostructure layer thereon. The nanostructure layer is capable of enhancing the mechanical strength of the ingot surface to reduce the chipping ratio of the wafer during slicing.
    Type: Application
    Filed: January 19, 2012
    Publication date: August 2, 2012
    Applicant: SINO-AMERICAN SILICON PRODUCTS INC.
    Inventors: Jiunn-Yih CHYAN, Jian-Jhih LI, Kun-Lin YANG, Wen-Ching HSU
  • Publication number: 20120193680
    Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
    Type: Application
    Filed: April 9, 2012
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sebastian Ulrich Engelmann, Nicholas C.M. Fuller, Eric Andrew Joseph, Isaac Lauer, Ryan M. Martin, James Vichiconti, Ying Zhang
  • Publication number: 20120196445
    Abstract: An aspect of the invention is to provide a method and apparatus for etching the silicon oxide layer of a semiconductor substrate, whereby the processing time for cleaning or rinsing, as well as any undesired aftereffects by residual hydrofluoric acid, may be reduced, in using the dry etching method involving the use of dense carbon dioxide that contains hydrofluoric acid, during the manufacturing process of a micro-electronic device.
    Type: Application
    Filed: February 10, 2011
    Publication date: August 2, 2012
    Applicant: Pukyong National University
    Inventor: Kwon-Taek LIM
  • Publication number: 20120189143
    Abstract: A micromechanical microphone device includes a membrane that is mounted in an elastically deflectable manner above a substrate and that has at least one gate electrode. The device further includes a source region and a drain region provided in or on the substrate with a channel region therebetween. The channel region is at least partly covered by the gate electrode and is spaced apart from the gate electrode by a gap. The membrane is deflectable under the influence of sound in such a way that the gap is variable.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 26, 2012
    Applicant: Robert Bosch GmbH
    Inventors: Alexander Buhmann, Ando Feyh
  • Publication number: 20120190186
    Abstract: A semiconductor device manufacturing method includes: forming a first insulating film over the surface of a semiconductor substrate having at least two adjacent protrusions in such a manner that the film thickness between the two protrusions is not less than 1.2 times the height of at least one of the two protrusions; and forming a second insulating film over the first insulating film, the second insulating film being harder than the first insulating film.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 26, 2012
    Inventor: Fuminobu NAKASHIMA
  • Publication number: 20120190209
    Abstract: Disclosed is a method for producing ZnO contact layers for solar cells. The layers are etched using hydrofluoric acid so as to generate a texture.
    Type: Application
    Filed: August 7, 2010
    Publication date: July 26, 2012
    Inventors: Eerke Bunte, Jorj Owen, Juergen Huepkes
  • Patent number: 8227354
    Abstract: Provided is a method of forming patterns of a semiconductor device, whereby patterns having various widths can be simultaneously formed, and pattern density can be doubled by a double patterning process in a portion of the semiconductor device. In the method of forming patterns of a semiconductor device, a first mold mask pattern and a second mold mask patter having different widths are formed on a substrate. A pair of first spacers covering both sidewalls of the first mold mask pattern and a pair of second spacers covering both sidewalls of the second mold mask pattern are formed. The first mold mask pattern and the second mold mask pattern are removed, and a wide-width mask pattern covering the second spacer is formed. A lower layer is etched using the first spacers, the second spacers, and the wide-width mask pattern as an etch mask.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-cheol Kim, Dae-youp Lee, Sang-youn Jo, Ja-min Koo, Byeong-hwan Son, Jang-hwan Jeong
  • Patent number: 8222147
    Abstract: The present invention provides a method of fabricating a semiconductor device including forming stop layers (32) that include silicon oxy-nitride films above a semiconductor substrate, forming a cover film (34) between and on the stop layers, in which a top surface of the cover film above a region between the stop layers is higher than top surfaces of the stop layers, and polishing the cover film to the stop layers by using ceria slurry, and also provides a semiconductor device including metal layers (30) provided above a semiconductor substrate, silicon oxy-nitride films (32) provided on the metal layers, and an embedded layer (36) provided between the metal layers to have a top surface substantially coplanar with top surfaces of the silicon oxy-nitride films. According to the present invention, it is possible to provide a semiconductor device having a film of excellent planarization on a surface thereof and fabrication method therefor.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: July 17, 2012
    Assignee: Spansion LLC
    Inventors: Takayuki Enda, Masayuki Moriya
  • Publication number: 20120177891
    Abstract: Methods of forming a patterned, silicon-enriched developable antireflective material. One such method comprises forming a silicon-enriched developable antireflective composition. The silicon-enriched developable antireflective composition comprises a silicon-enriched polymer and a crosslinking agent. The silicon-enriched polymer and the crosslinking agent are reacted to form a silicon-enriched developable antireflective material that is insoluble and has at least one acid-sensitive moiety. A positive-tone photosensitive material, such as a positive-tone photoresist, is formed over the silicon-enriched developable antireflective material and regions thereof are exposed to radiation. The exposed regions of the positive-tone photosensitive material and underlying regions of the silicon-enriched developable antireflective material are removed. Additional methods are disclosed, as are semiconductor device structures including a silicon-enriched developable antireflective material.
    Type: Application
    Filed: January 7, 2011
    Publication date: July 12, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Dan B. Millward, Yuan He, Lijing Gou, Zishu Zhang, Anton J. deVilliers, Jianming Zhou, Kaveri Jain, Scott Light, Michael Hyatt
  • Publication number: 20120168894
    Abstract: A hard mask composition, a method of forming a pattern, and a semiconductor integrated circuit device, the hard mask composition including a solvent; and an aromatic ring-containing compound, the aromatic ring-containing compound including at least one of a moiety represented by the following Chemical Formula 1 and a moiety represented by the following Chemical Formula 2:
    Type: Application
    Filed: September 23, 2011
    Publication date: July 5, 2012
    Inventors: Min-Soo Kim, Hwan-Sung Cheon, Jee-Yun Song, Young-Min Kim, Cheol-Ho Lee, Chung-Heon Lee
  • Publication number: 20120168898
    Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.
    Type: Application
    Filed: March 9, 2012
    Publication date: July 5, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Janos Fucsko, David H. Wells, Patrick Flynn, Whonchee Lee
  • Patent number: 8211802
    Abstract: A substrate processing apparatus cleaning method that includes: containing a cleaning gas in a reaction tube without generating a gas flow of the cleaning gas in the reaction tube by supplying the cleaning gas into the reaction tube and by completely stopping exhaustion of the cleaning gas from the reaction tube or by exhausting the cleaning gas at an exhausting rate which substantially does not affect uniform diffusion of the cleaning gas in the reaction tube from at a point of time of a period from a predetermined point of time before the cleaning gas is supplied into the reaction tube to a point of time when several seconds are elapsed after starting of supply of the cleaning gas into the reaction tube; and thereafter exhausting the cleaning gas from the reaction tube.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: July 3, 2012
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuyuki Okuda, Toru Kagaya, Masanori Sakai
  • Publication number: 20120164840
    Abstract: A substrate processing method includes a liquid processing process that supplies a processing liquid onto a substrate to process the substrate; a heating process that heats the substrate on which a liquid film of the processing liquid is formed; a supplying process that supplies a volatile processing liquid to the substrate on which the liquid film of the processing liquid is formed; a stopping process that stops the supply of the volatile processing liquid to the substrate; and a drying process that dries the substrate by removing the volatile processing liquid, in which the heating process starts before the supplying process that supplies the volatile processing liquid and the substrate is heated so that the surface temperature of the substrate is higher than a dew point before the surface of the substrate is exposed from the volatile processing liquid.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 28, 2012
    Inventors: Satoru Tanaka, Takehiko Orii, Hirotaka Maruyama, Teruomi Minami, Mitsunori Nakamori
  • Publication number: 20120160320
    Abstract: An aqueous acidic etching solution suitable for texturing the surface of single crystal and polycrystal silicon substrates and containing, based on the complete weight of the solution, 3 to 10% by weight of hydrofluoric acid; 10 to 35% by weight of nitric acid; 5 to 40% by weight of sulfuric acid; and 55 to 82% by weight of water; a method for texturing the surface of single crystal and polycrystal silicon substrates comprising the step of (1) contacting at least one major surface of a substrate with the said aqueous acidic etching solution; (2) etching the at least one major surface of the substrate for a time and at a temperature sufficient to obtain a surface texture consisting of recesses and protrusions; and (3) removing the at least one major surface of the substrate from the contact with the aqueous acidic etching solution; and a method for manufacturing photovoltaic cells and solar cells using the said solution and the said texturing method.
    Type: Application
    Filed: September 9, 2010
    Publication date: June 28, 2012
    Applicants: GP SOLAR GmbH, BASF SE
    Inventors: Simon Braun, Julian Proelss, Ihor Melnyk, Michael Michel, Stefan Mathijssen
  • Publication number: 20120164830
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes: preparing a substrate with an etching target, and etching the etching target through a plasma-free etching process that uses an etching gas including one of interhalogen compound, F2, XeF2 and combinations thereof.
    Type: Application
    Filed: November 23, 2011
    Publication date: June 28, 2012
    Inventors: Mongsup Lee, Inseak Hwang
  • Publication number: 20120153424
    Abstract: A hard mask composition, a method of forming a pattern, and a semiconductor integrated circuit device, the hard mask composition including a solvent; and a compound, the compound including a structural unit represented by the following Chemical Formula 1:
    Type: Application
    Filed: September 23, 2011
    Publication date: June 21, 2012
    Inventors: Seung-Bae OH, Hwan-Sung Cheon, Sung-Wook Cho, Min-Soo Kim, Jee-Yun Song, Yoo-Jeong Choi
  • Publication number: 20120156886
    Abstract: Production efficiency of a substrate (in particular, a substrate on which a SiC epitaxial film is formed) is improved and formation of the film inside a gas supply port is suppressed. This is accomplished by a substrate processing apparatus including a reaction chamber configured to accommodate a plurality of substrates 14, a heating part installed to surround the reaction chamber and configured to heat the reaction chamber, and a first gas supply pipe 60 extending in the reaction chamber, wherein the first gas supply pipe 60 includes a first gas supply port 68 configured to inject a first gas toward the plurality of substrates 14, and first shielding walls installed at both sides of the first gas supply port to expose the first gas supply port 68, the first shielding walls extending toward the plurality of substrates 14 from the first gas supply port 68.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 21, 2012
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kenji Shirako, Masanao Fukuda, Takafumi Sasaki, Yoshinori Imai, Daisuke Hara, Shuhei Saido, Koei Kuribayashi
  • Publication number: 20120156802
    Abstract: An optoelectronic swept-frequency semiconductor laser coupled to a microfabricated optical biomolecular sensor with integrated resonator and waveguide and methods related thereto are described. Biomolecular sensors with optical resonator microfabricated with integrated waveguide operation can be in a microfluidic flow cell.
    Type: Application
    Filed: February 18, 2011
    Publication date: June 21, 2012
    Inventors: Richard C. FLAGAN, Amnon YARIV, Jason GAMBA, Naresh SATYAN, Jacob SENDOWSKI, Arseny VASILYEV
  • Publication number: 20120153260
    Abstract: A method of etching active quantum nanostructures provides the step of laterally etching of an intermediate active quantum nanostructure layer interposed between cladding layers. The lateral etching can be carried out on at least one side of the intermediate active quantum nanostructure layer selectively, with respect to the cladding layers to define at least one lateral recess or spacing in the intermediate active quantum nanostructure layer and respective lateral protrusions of cladding layers protruding with respect to the intermediate active quantum nanostructure layer. This method can be applied to create devices including active quantum nanostructures such as, for example, three-dimensional photonic crystals, a photonic crystal double-slab and a photonic crystal laser.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 21, 2012
    Inventors: Seheon KIM, Axel SCHERER, Jingqing HUANG, Dong Yoon OH
  • Publication number: 20120149197
    Abstract: A manufacturing method of a device is provided. In the manufacturing method, a substrate is provided. The substrate has a plurality of patterns and a plurality of openings formed thereon, and the openings are located among the patterns. A first liquid supporting layer is formed on the patterns, and the openings are filled with the first liquid supporting layer. The first liquid supporting layer is transformed into a first solid supporting layer. The first solid supporting layer includes a plurality of supporting elements formed in the openings, and the supporting elements are formed among the patterns. A treatment process is performed on the patterns. The first solid supporting layer that includes the supporting elements is transformed into a second liquid supporting layer. The second liquid supporting layer is removed.
    Type: Application
    Filed: December 8, 2010
    Publication date: June 14, 2012
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Chien-Mao Liao, Yi-Nan Chen
  • Publication number: 20120149208
    Abstract: According to one embodiment, a substrate processing apparatus includes a substrate support unit configured to support a substrate by fixing the substrate from a back surface side of a surface to be processed; and a substrate processing unit in which a pad into which a predetermined liquid is soaked is arranged and which performs a substrate process on the surface to be processed of the substrate with the liquid. The surface to be processed of the substrate is brought into contact with the liquid on the pad surface by bringing the surface to be processed of the substrate close to a side of the pad, without rotating the substrate and the pad, to perform a substrate process.
    Type: Application
    Filed: September 21, 2011
    Publication date: June 14, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takahito NAKAJIMA
  • Patent number: 8198125
    Abstract: A method of making a monolithic photovoltaic module having a flexible substrate is described. The method includes the following steps. First, a flexible substrate is provided, and a first adhesive layer, a metal layer, and a second adhesive layer are formed thereon. The second adhesive layer, the metal layer and the first adhesive layer are etched with at least one etching paste. In addition, a patterned semiconductor body layer patterned by an etching paste or a laser scribing is formed thereon. Furthermore, transparent top electrodes patterned by an etching paste or a cold laser scribing are formed on the patterned semiconductor body layer.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: June 12, 2012
    Assignee: Du Pont Apollo Limited
    Inventors: Chiou-Fu Wang, Huo-Hsien Chiang
  • Patent number: 8193099
    Abstract: A method of forming a semiconductor device includes forming a transistor gate stack over a substrate having an active area and a shallow trench isolation (STI) region. First sidewall spacers are formed on the transistor gate stack, and an isotropic etch process is applied to isotropically remove an excess portion of a metal layer included within the transistor gate stack, the excess portion left unprotected by the first sidewall spacers. Second sidewall spacers are formed on the transistor gate stack, the second sidewall spacers completely encapsulating the metal layer of the transistor gate stack.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Mukesh V. Khare, Renee T. Mo, Ravikumar Ramachandran, Richard S. Wise, Hongwen Yan
  • Patent number: 8192636
    Abstract: The present invention relates to a method for treating copper or copper alloy surfaces for tight bonding to polymeric substrates, for example solder masks found in multilayer printed circuit boards. The substrate generally is a semiconductor-device, a lead frame or a printed circuit board.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: June 5, 2012
    Assignee: Atotech Deutschland GmbH
    Inventors: Dirk Tews, Christian Sparing
  • Publication number: 20120135607
    Abstract: A substrate processing method for forming a space extending along a predetermined line in a silicon substrate includes a first step of converging a laser light which is an elliptically-polarized light having an ellipticity other than 1 at the substrate so as to form a plurality of modified spots within the substrate along the line and produce a modified region including the modified spots, and a second step of anisotropically etching the substrate so as to advance an etching selectively along the modified region and form the space in the substrate. In the first step, the light is converged at the substrate such that a moving direction of the light with respect to the substrate and a direction of polarization of the light form an angle of 45° or greater therebetween, and the modified spots are made align in one row along the line.
    Type: Application
    Filed: July 19, 2011
    Publication date: May 31, 2012
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Hideki Shimoi, Keisuke Araki
  • Publication number: 20120135608
    Abstract: A substrate processing method for forming a space extending along a predetermined line in a silicon substrate includes a first step of converging a laser light which is an elliptically-polarized light having an ellipticity other than 1 at the substrate so as to form a plurality of modified spots within the substrate along the line and construct a modified region including the modified spots, and a second step of anisotropically etching the substrate so as to advance an etching selectively along the modified region and form the space in the substrate. In the first step, the light is converged at the substrate such that a moving direction of the light with respect to the substrate and a direction of polarization of the light form an angle of less than 45° therebetween, and the modified spots are made align in a plurality of rows along the line.
    Type: Application
    Filed: July 19, 2011
    Publication date: May 31, 2012
    Applicant: Hamamatsu Photonics K.K.
    Inventors: Hideki Shimoi, Keisuke Araki
  • Patent number: 8187955
    Abstract: A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: May 29, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Christos D. Dimitrakopoulos, Alfred Grill, Chun-yung Sung
  • Patent number: 8187975
    Abstract: A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: May 29, 2012
    Assignee: STMicroelectronics, Inc.
    Inventors: Prasanna Khare, Nicolas Loubet, Qing Liu
  • Publication number: 20120129355
    Abstract: A method for texturing a surface of a semiconductor substrate is proposed. Therein, the surface is etched with an etching solution which etches the semiconductor substrate material, wherein a wetting agent is added to the etching solution, which wetting agent contains water-soluble polymers, in particular in the form of polyvinyl alcohol. Therein, the process temperatures of the etching solution can be increased in comparison to conventional texturing methods, as a result of which the process time can be reduced. Process guidance is simplified and process stability is increased. A suitable texturing device for carrying out the method can, in addition to a basin for accommodating the etching solution and a heater for heating the etching solution to at least 85° C.
    Type: Application
    Filed: May 20, 2010
    Publication date: May 24, 2012
    Applicant: Universitaet Konstanz
    Inventors: Giso Hahn, Helge Haverkamp, Jose Nestor Ximello-Quiebras
  • Publication number: 20120129350
    Abstract: The method of forming a wordline is provided in the present invention. The proposed method includes steps of: (a) etching a metal-silicide layer and a POLY layer via a hard mask, wherein the metal-silicide layer is disposed on the POLY layer; (b) forming a POLY recess in the POLY layer; and (c) forming a liner film covering the metal-silicide layer.
    Type: Application
    Filed: November 23, 2010
    Publication date: May 24, 2012
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Jeng-Hwa Liao, Jung-Yu Shieh, Ling-Wu Yang
  • Publication number: 20120122299
    Abstract: A method for forming an edge-chamfered substrate with a buried insulating layer is provided, which comprises the following steps: providing a first substrate (S10); forming an etching mask layer on surfaces of the first substrate, wherein said etching mask layer is formed on the whole surfaces of the first substrate (S11); chamfering a glazed surface of the first substrate and the etching mask layer thereon by the edge grinding (S12); by rotary etching, etching the first substrate which is exposed by the edge grinding on the etching mask layer (S13); providing a second substrate (S14); and bonding the first substrate to the second substrate with a buried insulating layer (S15). The method avoids the edge collapses and the changes of the warp degree in subsequent processes.
    Type: Application
    Filed: July 10, 2010
    Publication date: May 17, 2012
    Applicants: SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY, CHINESE ACADEMY OF SCIENCE, SHANGHAI SIMGUI TECHNOLOGY CO., LTD.
    Inventors: Xiang Wang, Xing Wei, Miao Zhang, Chenglu Lin, Xi Wang
  • Publication number: 20120115269
    Abstract: Systems and methods for processing sacrificial layers in MEMS device fabrication are provided. In one embodiment, a method comprises: applying a patterned layer of Aerogel material onto a substrate to form an Aerogel sacrificial layer; applying at least one non-sacrificial silicon layer over the Aerogel sacrificial layer, wherein the non-sacrificial silicon layer is coupled to the substrate through one or more gaps provided in the patterned layer of Aerogel material; and removing the Aerogel sacrificial layer by exposing the Aerogel sacrificial layer to a removal liquid.
    Type: Application
    Filed: November 5, 2010
    Publication date: May 10, 2012
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventor: James F. Detry
  • Publication number: 20120112603
    Abstract: There is provided an electromechanical transducer capable of improving yield and obtaining a cavity having a good internal flatness, and a method of fabricating the same. The electromechanical transducer is fabricated in such a manner that an SOI substrate 209 having an active layer 210 whose surface is planarized on a supporting substrate 201 with a thermal oxide insulating layer 205 interposed therebetween is provided; the active layer is patterned into a cavity shape; insulating films 206 and 207 are formed on the patterned active layer; an etching hole 203 passing through the insulating films and communicating with the active layer is formed; and a cavity 202 is formed by etching away the active layer using the etching hole.
    Type: Application
    Filed: October 24, 2011
    Publication date: May 10, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Yuichi Masaki
  • Publication number: 20120108074
    Abstract: Disclosed is a method for treating semiconductor wafer including: providing a layer that contains lanthanum oxide or a lanthanide oxide (e.g. Dy2O3, Pr2O3, Ce2O3) applying an aqueous solution, wherein the aqueous solution is carbonated water, whereby the layer that contains lanthanum oxide or a lanthanide oxide is removed at specific areas, so that the surface, on which the layer that contains lanthanum oxide or a lanthanide oxide has been deposited, is exposed.
    Type: Application
    Filed: June 14, 2010
    Publication date: May 3, 2012
    Applicant: LAM RESEARCH AG
    Inventor: Kei Kinoshita
  • Publication number: 20120108039
    Abstract: Embodiments of the invention generally relate to methods for treating a silicon-containing material on a substrate surface and performing a chamber clean process. In one embodiment, a method includes positioning a substrate containing a silicon material having a contaminant thereon within a process chamber and exposing the substrate to an etching gas containing chlorine gas and a silicon source gas while removing the contaminant and maintaining a temperature of the substrate within a range from about 500° C. to less than about 800° C. during an etching process. The method further includes exposing the substrate to a deposition gas after the etching process during a deposition process and exposing the process chamber to a chamber clean gas containing chlorine gas and the silicon source gas after the deposition process during a chamber clean process. The chamber clean process limits the etching of quartz and metal surfaces within the process chamber.
    Type: Application
    Filed: January 9, 2012
    Publication date: May 3, 2012
    Inventors: Ali Zojaji, Arkadii V. Samoilov
  • Patent number: 8163655
    Abstract: The present disclosure provides a method for making a semiconductor device. The method includes forming a first material layer on a substrate; forming a second material layer on the first material layer; forming a sacrificial layer on the second material layer; forming a patterned resist layer on the sacrificial layer; applying a first wet etching process using a first etch solution to the substrate to pattern the sacrificial layer using the patterned resist layer as a mask, resulting in a patterned sacrificial layer; applying an ammonia hydroxide-hydrogen peroxide-water mixture (APM) solution to the substrate to pattern the second material layer, resulting in a patterned second material layer; applying a second wet etching process using a second etch solution to the substrate to pattern the first material layer; and applying a third wet etching process using a third etch solution to remove the patterned sacrificial layer.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: April 24, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ching-Yu Chang
  • Publication number: 20120094445
    Abstract: A method for manufacturing a semiconductor device with high electric characteristics is provided. Part of a stacked semiconductor film in which an amorphous semiconductor film is provided on a crystalline semiconductor film is etched using a mixed gas including an HBr gas, a CF4 gas, and an oxygen gas, so that part of the crystalline semiconductor film provided in the stacked semiconductor film is exposed. Etching for forming a back channel portion of a thin film transistor is performed with the method for etching, whereby high electric characteristics can be provided for the thin film transistor.
    Type: Application
    Filed: October 14, 2011
    Publication date: April 19, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shinya Sasagawa, Hiroshi Fujiki
  • Publication number: 20120094501
    Abstract: The present invention relates to an etching composition, in particular, for silicon materials, a method for characterizing defects on surfaces of such materials and a process of treating such surfaces with the etching composition, wherein the etching composition comprises an organic oxidant dissolved in a solvent, and a deoxidant, wherein the deoxidant comprises HF or HBF4 or mixtures thereof.
    Type: Application
    Filed: March 8, 2010
    Publication date: April 19, 2012
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Jochen Maehliss, Bernd Kolbesen, Romana Hakim, Francois Brunier