Abstract: An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.

Abstract: A method for producing micromechanical patterns having a relief-like sidewall outline shape or an angle of inclination that is able to be set, the micromechanical patterns being etched out of a SiGe mixed semiconductor layer that is present on or deposited on a silicon semiconductor substrate, by dry chemical etching of the SiGe mixed semiconductor layer; the sidewall outline shape of the micromechanical pattern being developed by varying the germanium proportion in the SiGe mixed semiconductor layer that is to be etched; a greater germanium proportion being present in regions that are to be etched more strongly; the variation in the germanium proportion in the SiGe mixed semiconductor layer being set by a method selected from the group including depositing a SiGe mixed semiconductor layer having varying germanium content, introducing germanium into a silicon semiconductor layer or a SiGe mixed semiconductor layer, introducing silicon into a germanium layer or an SiGe mixed semiconductor layer and/or by therm

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can rinse a substrate with water, a plurality of protruding patterns being formed on the substrate. The method can dry the substrate by removing water from a recess between the protruding patterns by irradiating microwaves.

Abstract: An optical device includes a ridge on a base. The ridge includes an active medium. An active component on the base is a light sensor and/or a light modulator. The active component is configured to guide a light signal through the active medium included in the ridge. Electrical current carriers contact the lateral sides of the ridge on opposing sides of the ridge. Each of the electrical current carriers includes a carrier material that is doped so as to increase the electrical conductivity of the carrier material. The carrier material is different from the active medium.

Abstract: A method of patterning a substrate includes forming spaced first features over a substrate. Individual of the spaced first features include sidewall portions of different composition than material that is laterally between the sidewall portions. A mixture of immiscible materials is provided between the spaced first features. At least two of the immiscible materials are laterally separated along at least one elevation between adjacent spaced first features. The laterally separating forms a laterally intermediate region including one of the immiscible materials between two laterally outer regions including another of the immiscible materials along the one elevation. The laterally outer regions are removed and material of the spaced first features is removed between the sidewall portions to form spaced second features over the substrate. Other embodiments are disclosed.

Abstract: A method of forming a nanoscale three-dimensional pattern in a porous semiconductor includes providing a film comprising a semiconductor material and defining a nanoscale metal pattern on the film, where the metal pattern has at least one lateral dimension of about 100 nm or less in size. Semiconductor material is removed from below the nanoscale metal pattern to create trenches in the film having a depth-to-width aspect ratio of at least about 10:1, while pores are formed in remaining portions of the film adjacent to the trenches. A three-dimensional pattern having at least one nanoscale dimension is thus formed in a porous semiconductor, which may be porous silicon. The method can be extended to form self-integrated porous low-k dielectric insulators with copper interconnects, and may also facilitate wafer level chip scale packaging integration.

Abstract: An interposer includes grooves (310) for waveguides 104 (e.g. optical fiber cables) coupled to a transducer (120). The grooves are formed by etching a cavity (410) in a substrate (130), filling the cavity with some layer (520), then etching the layer to form the grooves. The grooves can be formed in a separate structure which is then inserted into a cavity in an interposer having electrical circuitry for the transducer. The cavity has outwardly or inwardly sloped sidewalls which can serve as minors (144) or on which the minors are later formed. The substrate can be monocrystalline silicon, in which the inwardly sloped (retrograde) sidewalls are formed by a combination of different etches at least one of which is selective to certain crystal planes. Other features, including non-optical embodiments, are also provided.

Abstract: A method for removing germanium suboxide between a germanium (Ge) substrate and a dielectric layer made of metal oxide includes causing a supercritical fluid composition that includes a supercritical carbon dioxide fluid and an oxidant to diffuse into the germanium suboxide such that metal residues in the dielectric layer, the germanium suboxide and the oxidant are subjected to a redox reaction so as to reduce the germanium suboxide into germanium.

Abstract: A method and system for decapsulating a portion of an encapsulated integrated circuit delivers etchant mixture in variable but precise, high-velocity micro-metered pulses to a single outlet port of a pump from any one of or a combination of separate inlet ports connected to separate etchant source containers holding specific etchant solutions, controls temperature of the etchant mixture by passing the etchant mixture from the outlet port through a serpentine passage in a temperature-controlled metal block, and delivers the etchant mixture from the serpentine passage of the temperature-controlled block via a delivery conduit to an encapsulation surface of the encapsulated integrated circuit.

Abstract: The present invention is a silicon-containing resist underlayer film-forming composition containing a condensation product and/or a hydrolysis condensation product of a mixture comprising: one or more kinds of a compound (A) selected from the group consisting of an organic boron compound shown by the general formula (1) and a condensation product thereof and one or more kinds of a silicon compound (B) shown by the general formula (2). Thereby, there can be provided a silicon-containing resist underlayer film-forming composition being capable of forming a pattern having a good adhesion, forming a silicon-containing film which can be used as a dry-etching mask between a photoresist film which is the upperlayer film of the silicon-containing film and an organic film which is the underlayer film thereof, and suppressing deformation of the upperlayer resist during the time of dry etching of the silicon-containing film; and a patterning process.

Abstract: In some embodiments, the present invention discloses an etchant solution hydrochloric acid and nitric acid to etch doped polysilicon at low etch rates. The doped polysilicon can be doped with Ge, In, B and Ga. Preferably, the concentration of hydrochloric acid can be greater than 1 vol %, and the concentration of nitric acid is greater than 15 vol %.

Abstract: There is provided a silicon substrate including: a first connection part connected to a manifold and having a first width of a first size; a second connection part connected to a pressure chamber and having a second width of a second size; and a restrictor part connecting the first connection part to the second connection part and having a third width of a third size smaller than the first size or the second size, wherein a boundary part connecting the restrictor part to the first connection part or the restrictor part to the second connection part is formed to be curved.

Abstract: A method for combinatorially processing a substrate is provided. The method includes introducing a first etchant into a reactor cell and introducing a fluid into the reactor cell while the first etchant remains in the reactor cell. After initiating the introducing the fluid, contents of the reactor cell are removed through a first removal line and a second removal line, wherein the first removal line extends farther into the reactor cell than the second removal line. A level of the fluid above an inlet to the first removal line is maintained while removing the contents. A second etchant is introduced into the reactor cell while removing the contents through the first removal line and the second removal line. The method includes continuing the introducing of the second etchant until a concentration of the second etchant is at a desired level, wherein the surface of the substrate remains submerged.

Abstract: A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×1018 cm?3 and has the layer thickness of more than 10 nm and not more than 100 nm, a recess that is formed up to the inside of the channel layer in the semiconductor operation layer, source and drain electrodes that are formed on the semiconductor operation layer with the recess intervening therebetween, a gate insulating film that is formed on the semiconductor operation layer so as to cover the recess, and a gate electrode that is formed on the gate insulating film in the recess.

Abstract: Disclosed herein are methods of controlling the etching of a layer of silicon nitride relative to a layer of silicon dioxide. In one illustrative example, the method includes providing an etch bath that is comprised of an existing etchant adapted to selectively etch silicon nitride relative to silicon dioxide, performing an etching process in the etch bath using the existing etchant to selectively remove a silicon nitride material positioned above a silicon dioxide material on a plurality of semiconducting substrates, determining an amount of the existing etchant to be removed based upon a per substrate silicon loading of the etch bath by virtue of etching the plurality of substrates in the etch bath and determining an amount of new etchant to be added to the etch bath based upon a per substrate silicon loading of the etch bath by virtue of etching the plurality of substrates in the etch bath.

Abstract: According to one embodiment, a method for chemical planarization includes: preparing a treatment liquid containing a hydrosilicofluoric acid aqueous solution containing silicon dioxide dissolved therein at a saturated concentration; and decreasing height of irregularity of a silicon dioxide film. In the decreasing, dissolution rate of convex portions is made larger than dissolution rate of concave portion of the irregularity while changing equilibrium state of the treatment liquid at areas being in contact with the convex portions of the irregularity, in a state in which the silicon dioxide film having the irregularity is brought into contact with the treatment liquid.

Abstract: In some embodiments, the present invention discloses sealing mechanisms for generating site isolated regions on a substrate, allowing combinatorial processing without cross contamination between regions. The sealing mechanism can include a thin sharp edge ring for pressing on the substrate surface with small contact area. The small sealing area can concentrate the sealing force, generating higher contact pressure to guard against fluid leakage across the sealing surface, for example, eliminating fluid wicking at the seal interface through capillary action. The sealing mechanism can include multiple protrusions, which contacts the substrate leaving a small gap at the remaining portion of the sealing mechanism. The sealing mechanism can include minimal contact points with the substrate, which can significantly reduce the particle generation during processing. A pressure differential can be established across the sealing surface to prevent fluid leakage.

Abstract: A micromechanical systems (MEMs) pressure sensor includes a semiconductor substrate having a deep well located within a first surface and a cavity located within a second, opposing surface. The semiconductor substrate has a first doping type. The deep well has a second doping type, with a gradient doping profile, thereby forming a PN junction within the substrate. The cavity forms a diaphragm, which is a substrate section that is thinner than the surrounding substrate sections, that comprises the deep well. One or more pizeoresistor elements are located within the deep well. The piezoresistors are sensitive to deformations, such as bending, in the diaphragm caused by changes in the pressure of the cavity.

Abstract: It is an object of the present invention to provide a plasma etching method that can improve a selection ratio of a film to be etched to a film different from the film to be etched than that in the related art. The present invention provides a plasma etching method for selectively etching a film to be etched with respect to another film different from the film to be etched, the plasma etching method including etching, using gas that can generate a deposited film containing components same as components of the another film different from the film to be etched, the film on which generation of the deposited film is suppressed.

Abstract: A liquid composition for wet etching has improved selectivity for polysilicon over silicon dioxide, even when the polysilicon is heavily doped and/or the silicon dioxide is a low temperature oxide. The composition comprises 0.05-0.4 percent by weight hydrofluoric acid, 15-40 percent by weight nitric acid, 55-85 percent by weight sulfuric acid and 2-20 percent by weight water. A method and apparatus for wet etching using the composition are also disclosed.

Abstract: The present invention provides a method of wet etching a silicon slice including a silicon substrate and a metal film layer thereon comprising steps of: performing lithographic process to the silicon slice forming a masked silicon slice comprising the silicon substrate and a partially masked metal film thereon; immersing the masked silicon slice into an etchant; rotating the masked silicon slice in the etchant; injecting high-purity nitrogen gas into the etchant for agitating the etchant; removing the masked silicon slice out of the etchant, upon completion of etching; and rinsing the masked silicon slice with deionized water.

Abstract: A protective chuck is disposed on a substrate with a gas bearing layer between the bottom surface of the protective chuck and the substrate surface. The gas bearing layer protects a surface region against a fluid layer covering the substrate surface. The protection of the gas bearing is a non-contact protection, reducing or eliminating potential damage to the substrate surface due to friction. The gas bearing can enable combinatorial processing of a substrate, providing multiple isolated processing regions on a single substrate with different material and processing conditions.

Abstract: A method of manufacturing a semiconductor device includes preparing a semiconductor wafer having a device area, an end face, and a surface peripheral area located outside the device area and between the end face and the device area. Forming a Cu layer on the semiconductor wafer and rotating the wafer in a horizontal plane. Emitting a first liquid from an edge nozzle towards the surface peripheral area which selectively removes a first unnecessary material in the surface peripheral area. Emitting a protecting liquid toward the semiconductor wafer, thereby protecting the device area from the first liquid. An angle of a longitudinal axis of the edge nozzle with respect to a tangent of the semiconductor wafer at a point, where the longitudinal axis of the edge nozzle intersects the end face of the wafer, is set in the range of 0 to 90 degrees in plan view.

Abstract: A method of removing a high molecular weight organic-comprising hard mask or BARC from a surface of a porous low k dielectric material, where a change in the dielectric constant of the low k dielectric material is less than about 5% after application of the method. The method comprises exposing the organic-comprising hard mask or BARC to nitric acid vapor which contains at least 68% by mass HNO3.

Abstract: A method of forming an aperture (e.g., a through via, a blind via, a trench, an alignment feature, etc.) within a substrate includes irradiating a substrate with a laser beam to form a laser-machined feature having a sidewall. The laser-machined feature is then processed to change at least one characteristic (e.g., the sidewall surface roughness, diameter, taper, aspect ratio, cross-sectional profile, etc.) of the laser-machined feature. The laser-machined feature can be processed to form the aperture by performing an isotropic wet-etch process employing an etchant solution containing HNO3, HF and, optionally acetic acid.

Abstract: A method for forming a pattern includes providing a resist underlayer film on a substrate using a first composition for forming a resist underlayer film. The first composition includes a polymer having a structural unit represented by a following formula (1). In the formula (1), Ar1 and Ar2 each independently represent a bivalent group represented by a following formula (2). A resist coating film is provided on the resist underlayer film using a resist composition. A resist pattern is formed using the resist coating film. A predetermined pattern is formed on the substrate by sequentially dry-etching the resist underlayer film and the substrate using the resist pattern as a mask.

Abstract: A convex part formation method of forming a convex part in parallel with a <110> direction of a backing on the backing having a {100} face as the top surface thereof, includes: (a) forming a mask layer in parallel with the <110> direction on the backing; (b) etch the backing so as to form a convex-part upper layer whose sectional shape on a cutting plane corresponding to a {110} face is an isosceles trapezoid, the base of which is longer than the upper side thereof, and the side surface of which has an inclination of ?U; and (c) further etching the backing so as to form a convex-part lower layer whose sectional shape on the cutting plane corresponding to the {110} face is an isosceles trapezoid, the base of which is longer than the upper side thereof, and the side surface of which has an inclination of ?D (where ?D??U).

Abstract: A polished semiconductor wafer of high flatness is produced by the following ordered steps: slicing a semiconductor wafer from a rod composed of semiconductor material, material-removal processing of at least one side of the semiconductor wafer, and polishing of at least one side of the semiconductor wafer, wherein the semiconductor wafer has, after the material-removing processing and before the polishing on at least one side to be polished, along its margin, a ring-shaped local elevation having a maximum height of at least 0.1 ?m, wherein the local elevation reaches its maximum height within a 10 mm wide ring lying at the edge of the semiconductor wafer.

Abstract: A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture.

Abstract: A method and apparatus to modify the surface structure of a silicon substrate or deposited silicon layer in a controllable manner using gas only in an atmospheric environment, suitable for making photovoltaic (PV) wafer based devices. The method and apparatus comprising the steps of disposing the substrate or deposited layer on a moveable carrier; pre-heating the substrate or deposited layer; and moving the substrate or deposited layer for etching through an atmospheric reactor; under an etchant delivering module inside the reactor and applying at least one etchant in gas form at a controlled flow rate and angle to the substrate or deposited layer in the reactor, wherein the at least one etchant gas is selected from the group comprising fluoride-containing gases and chlorine-based compounds. The technical problem that has been solved is the provision of a high throughput dry etching method at atmospheric pressure.

Abstract: To form a single crystal silicon membrane with a suspension layer, a single crystal silicon substrate with crystal orientation <111> is prepared. A doped layer is formed on the top surface of the single crystal silicon substrate. Multiple main etching windows are formed through the doped layer. A cavity is formed through the single crystal silicon substrate by anisotropic etching. The doped layer is above the cavity to form a suspension layer. If two electrode layers are formed on the two ends of the suspension layer, a micro-heater is constructed. The main etching windows extend in parallel to a crystal plane {111}. By both the single crystal structure and different impurity concentrations of the single crystal silicon substrate, the single crystal silicon substrate has a higher etch selectivity. When a large-area cavity is formed, the thickness of the suspension layer is still controllable.

Abstract: According to one embodiment, an etching method includes: supplying an etching-resistant material; and etching the silicon nitride film. The supplying includes supplying the etching-resistant material to a processing surface including a surface of a silicon nitride film and a surface of a non-etching film, the non-etching film including a material different from the silicon nitride film. The etching includes etching the silicon nitride film using an etchant in a state of the etching-resistant material being formed relatively more densely on the surface of the non-etching film than on the surface of the silicon nitride film.

Abstract: A silicon compound film is dry etched by parallel-plate type dry etching using an etching gas including at least COF2.

Abstract: A pattern formation method, mask pattern formation method and a method for manufacturing semiconductor devices are provided in this disclosure, which are directed to the field of semiconductor processes. The pattern formation method comprises: providing a substrate; forming a polymer thin film containing a block copolymer on the substrate; forming a first pattern through imprinting the polymer thin film with a stamp; forming domains composed of different copolymer components through directed self assembly of the copolymer in the first pattern; selectively removing the domains composed of copolymer components to form a second pattern. In the embodiments of the present invention, finer pitch patterns can be obtained through combining the imprinting and DSA process without exposure, which as compared to the prior art methods has the advantage of simplicity. Furthermore, stamps used in imprinting may have relative larger pitches, facilitating and simplifying the manufacture and alignment of the stamps.

Abstract: A method and system for performing gas cluster ion beam (GCIB) etch processing of metal-containing material is described. In particular, the GCIB etch processing includes forming a GCIB that contains a halogen element.

Abstract: The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.

Abstract: In an embodiment, a fluid ejection device includes a die including a fluid feed slot that extends from a back side to a front side of the die, a firing chamber formed on the front side to receive fluid from the feed slot, a fluid distribution manifold adhered to the back side to provide fluid to the feed slot, and a corrosion-resistant layer coating the back side of the die so as not to extend into the feed slot.

Abstract: An etchant according to exemplary embodiments of the present invention includes about 0.5 wt % to about 20 wt % of persulfate, about 0.01 wt % to about 2 wt % of a fluorine compound, about 1 wt % to about 10 wt % of inorganic acid, about 0.5 wt % to about 5 wt % of a cyclic amine compound, about 0.1 wt % to about 5 wt % of a chlorine compound, about 0.05 wt % to about 3 wt % of copper salt, about 0.1 wt % to about 10 wt % of organic acid or organic acid salt, and water.

Abstract: A method includes providing a wafer and providing a first spray bar spaced a distance from the wafer. A first spray is dispensed from the first spray bar onto a first portion (e.g., half) of the wafer. Thereafter, the wafer is rotated. A second spray is dispensed from the first spray bar onto a second portion (e.g., half) of the rotated wafer. In embodiments, a plurality of spray bars are positioned above the wafer. One or more of the spray bars may be tunable in separation distance and/or angle of dispensing.

Abstract: A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. The liner is removed from a bottom surface of the at least one trench to expose the underlying silicon. A portion of the underlying exposed silicon is removed to form a cavity in the silicon. At least one removal cycle is conducted to remove exposed silicon in the cavity to form a bulb-shaped cross-sectional profile, with each removal cycle comprising subjecting the silicon in the cavity to ozonated water to oxidize the silicon and subjecting the oxidized silicon to a hydrogen fluoride solution to remove the oxidized silicon. A semiconductor device structure comprising the at least one trench comprising a cavity with a bulb-shaped cross-sectional profile is also disclosed.

Abstract: Methods are disclosed that include selectively etching diffused regions to form recesses in semiconductor material, and forming charge storage structures in the recesses. Additional embodiments are disclosed.

Abstract: A method of fabricating a semiconductor device for improving the performance of “?” shaped embedded source/drain regions is disclosed. A “U” shaped recess is formed in a Si substrate. The recess is treated with a surfactant, the amount of surfactant adsorbed on the recess sidewalls being greater than that on the recess bottom. An oxide is formed on the bottom. The presence of surfactant on the sidewalls, prevents oxide from forming thereon. The surfactant on the sidewalls is then removed and an orientation selective wet etching process is performed on the sidewalls. The oxide protects the Si at the bottom is from being etched.

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

Abstract: A method of semiconductor fabrication including providing a semiconductor wafer and dispensing a first chemical spray onto the wafer using a first nozzle and dispensing a second chemical spray using a second nozzle onto the wafer. These dispensing may be performed simultaneously. The method may further include moving the first and second nozzle. The first and second nozzle may provide the first and second chemical spray having at least one different property. For example, different chemical compositions, concentrations, temperatures, angles of dispensing, or flow rate. A chemical dispersion apparatus providing two nozzles which are operable to be separately controlled is also provided.

Abstract: This invention provides a semiconductor having a functionalized surface that is resistant to oxidation and that includes a plurality of atoms of a Group III element bonded to organic groups. The functionalized surface has less than or equal to about 1 atom of the Group III element bonded to an oxygen atom per every 1,000 atoms of the Group III element bonded to the organic groups, as determined using X-ray photoelectron spectroscopy. This invention also provides a method of functionalizing the surface and includes the step of halogenating at least one of the plurality of atoms of the Group III element to form halogenated Group III element atoms. The method also includes the step of reacting at least one of the halogenated Group III element atoms with a Grignard reagent to form a bond between the at least one Group III element atom and the organic groups.

Abstract: According to the invention, a monitoring device (12) is created for monitoring a thinning of at least one semiconductor wafer (4) in a wet etching unit (5), wherein the monitoring device (12) comprises a light source (14), which is designed to emit coherent light of a light wave band for which the semiconductor wafer (4) is optically transparent. The monitoring device (12) further comprises a measuring head (13), which is arranged contact-free with respect to a surface of the semiconductor wafer (4) to be etched, wherein the measuring head (13) is designed to irradiate the semiconductor wafer (4) with the coherent light of the light wave band and to receive radiation (16) reflected by the semiconductor wafer (4). Moreover, the monitoring device (12) comprises a spectrometer (17) and a beam splitter, via which the coherent light of the light wave band is directed to the measuring head (13) and the reflected radiation is directed to the spectrometer (17).

Abstract: Methods for selectively depositing high quality epitaxial material include introducing pulses of a silicon-source containing vapor while maintaining a continuous etchant flow. Epitaxial material is deposited on areas of a substrate, such as source and drain recesses. Between pulses, the etchant flow continues such that lower quality epitaxial material may be removed, as well as any non-epitaxial material that may have been deposited. The pulse of silicon-source containing vapor may be repeated until a desired thickness of epitaxial material is selectively achieved in semiconductor windows, such as recessed source/drain regions.

Abstract: A substrate processing apparatus cleaning method that includes: containing a cleaning gas in a reaction tube without generating a gas flow of the cleaning gas in the reaction tube by supplying the cleaning gas into the reaction tube and by completely stopping exhaustion of the cleaning gas from the reaction tube or by exhausting the cleaning gas at an exhausting rate which substantially does not affect uniform diffusion of the cleaning gas in the reaction tube from at a point of time of a period from a predetermined point of time before the cleaning gas is supplied into the reaction tube to a point of time when several seconds are elapsed after starting of supply of the cleaning gas into the reaction tube; and thereafter exhausting the cleaning gas from the reaction tube.

Abstract: According to one embodiment, a method for manufacturing a nonvolatile memory device including a plurality of memory cells is disclosed. Each of the plurality of memory cells includes a base layer including a first electrode, a magnetic tunnel junction device provided on the base layer, and a second electrode provided on the magnetic tunnel junction device. The magnetic tunnel junction device includes a first magnetic layer, a tunneling barrier layer provided on the first magnetic layer, and a second magnetic layer provided on the tunneling barrier layer. The method can include etching a portion of the second magnetic layer and a portion of the first magnetic layer by irradiating gas clusters onto a portion of a surface of the second magnetic layer or a portion of a surface of the first magnetic layer.

Abstract: A method to remove excess material during the manufacturing of semiconductor devices includes providing a semiconductor wafer comprising silicon nitride deposited thereon and applying a chemical solution to the semiconductor wafer, wherein the chemical solution comprises a combination of sulfuric acid and deionized water.