Abstract: An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a semiconductor oxide by the oxidant, and the oxide remover subtracts the semiconductor oxide.

Abstract: In an inventive resist removing method, sulfuric acid and hydrogen peroxide water are supplied to a surface of a substrate to remove a resist from the substrate surface. Thereafter, hydrogen peroxide water is supplied to the substrate surface to remove the sulfuric acid from the substrate surface.

Abstract: An apparatus and method used to selectively etch materials from the edge and bevel areas of a silicon wafer are provided. In one configuration, a bevel etch spin chuck, for use in a device for removing unwanted material from an edge and bevel area of a wafer, includes a fluid channel, a separation barrier, and a gas channel that are substantially circular and concentric. A fluid, such as an etching solution, is provided to the fluid channel and contacts one or more areas at the edge and bevel area of the wafer. A stream of continuously flowing gas, such as nitrogen, is provided to the gas channel and purges an active side of the wafer.

Abstract: A process for producing an insulation structure with openings of a low aspect ratio is disclosed. In one embodiment, a dopant is introduced into the insulation structure with a concentration which on average increases or decreases in the vertical direction from a pre-processed semiconductor surface, the openings are formed in a dry-etching step and the aspect ratio of the openings is reduced by increasing the basic surface area of the openings using a subsequent wet-chemical etching step.

Abstract: A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing the nano-crystals to a high density plasma comprising a source of free radical chlorine, ionic chlorine, or both to modify the nano-crystals; and removing the modified nano-crystals with a wet etchant.

Abstract: The invention relates to a method for fabricating a composite structure having heat dissipation properties greater than a bulk single crystal silicon structure having the same dimensions. The structure includes a support substrate, a top layer and an oxide layer between the support substrate and the top layer.

Abstract: Disclosed is a method for stripping a photoresist comprising: (I) providing a photoresist pattern on a substrate where the substrate has at least a copper (Cu) wiring and a low-dielectric layer thereon, and selectively etching the low-dielectric layer by using the photoresist pattern as a mask; (II) contacting the substrate after the step (I), with ozone water and/or aqueous hydrogen peroxide; and (III) contacting the substrate after the step (II), with a photoresist stripping solution that contains at least a quaternary ammonium hydroxide.

Abstract: In a film formation method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of the silicon surface in advance, and the film formation method removes the hydrogen by exposing the silicon surface to a first inert gas plasma. Thereafter a silicon compound layer is formed on the surface of the silicon gas by generating plasma while using a mixed gas of a second inert gas and one or more gaseous molecules, such that there is formed a silicon compound layer containing at least a pat of the elements constituting the gaseous molecules, on the surface of the silicon gas.

Abstract: A semiconductor device includes: a semiconductor substrate that has an integrated circuit and an electrode, the electrode being electrically coupled to the integrated circuit; a resin layer that is formed on the semiconductor substrate, the resin layer having an upper surface and a lower surface, the upper surface and the lower surface opposing each other, the lower surface facing the substrate; and a spiral inductor that is formed on the upper surface of the resin layer with a spiral wiring line, the spiral inductor being electrically coupled to the electrode. The wiring line has both ends in a width direction intersecting an axial line spirally extending and a mid-portion between the both ends. At least a part of the mid-portion makes contact with the upper surface of the resin layer, and at least the both ends are positioned apart from the upper surface of the resin layer.

Abstract: A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).

Abstract: An apparatus for leveling and centering a catch-cup chamber to a diverter chamber of a semiconductor processing chamber is described. In one embodiment, the apparatus has a frame with branches. A coupler is mounted to the end of each branch. A measuring device is mounted to each branch. The apparatus is placed in the diverter. The measuring device measures a distance from a branch to a top surface of the catch-cup chamber.

Abstract: There are provided the steps of loading a substrate into a reaction vessel; forming a film on the substrate while supplying a film forming gas into the reaction vessel; unloading the substrate after film formation from the reaction vessel; supplying a cleaning gas into the reaction vessel while lowering a temperature in the reaction vessel and removing a deposit deposited on at least an inner wall of the reaction vessel in the film forming step.

Abstract: A method for forming a semiconductor device includes forming a liner over a semiconductor material including a control electrode. The method further includes forming a first spacer adjacent to the control electrode, wherein the first spacer has a first width. The method further includes implanting current electrode dopants. The method further includes removing the first spacer. The method further includes forming a second spacer adjacent the control electrode, wherein the second spacer has a second width and wherein the second width is less than the first width. The method further includes using the second spacer as a protective mask to selectively remove the liner. The method further includes forming a stressor layer overlying the control electrode and current electrode regions.

Abstract: One embodiment of the present invention provides a process for obtaining high-quality boundaries for individual multilayer structures which are fabricated on a trench-partitioned substrate. During operation, the process receives a trench-partitioned substrate wherein the substrate surface is partitioned into arrays of isolated deposition platforms which are separated by arrays of trenches. The process then forms a multilayer structure, which comprises a first doped layer, an active layer, and a second doped layer, on one of the deposition platforms. Next, the process removes sidewalls of the multilayer structure.

Abstract: A method for fabrication of single crystal silicon micromechanical resonators using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, a capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of the base wafer; the active layer of the resonator wafer is bonded directly to the active layer of the base wafer; the handle and dielectric layers of the resonator wafer are removed; viewing windows are opened in the active layer of the resonator wafer; masking the single crystal silicon semiconductor material active layer of the resonator wafer with photoresist material; a single crystal silicon resonator is machined in the active layer of the resonator wafer using silicon dry etch micromachining technology; and the photoresist material is subsequently dry stripped.

Abstract: A method of making a light emitting element, the light emitting element with a semiconductor layer represented by: AlxInyGa1-x-yN (0?X?1, 0?Y?1, 0?X+Y?1), has the step of wet-etching a surface of the semiconductor layer by using an etching solution to have a roughened surface on the semiconductor layer. The wet-etching is conducted without irradiating the surface of the semiconductor layer with a light with a wavelength region corresponding to energy higher than bandgap energy of the semiconductor layer.

Abstract: Methods which comprise: providing a stack to be etched, the stack comprising a metal interconnect layer disposed above a substrate, a barrier layer disposed above the metal interconnect layer, a hard mask layer disposed on the barrier layer, and a patterning layer disposed above the hard mask layer wherein the patterning layer defines a pattern above the hard mask layer; and etching the pattern through the hard mask layer and at least a portion of the barrier layer, wherein the etching through an interface between the hard mask layer and the barrier layer is carried out using a fluorine-containing etch recipe.

Abstract: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.

Abstract: The present invention provides a process control method in spin etching capable of realizing uniformity in etching amount in etching treatment for even wafers each having various conditions, and achieving uniformity of thickness values among etched wafers. In the present invention, weight of a wafer before etching is measured in units of 1/1000 g, followed by predetermined etching treatment in a spin etching section. Thereafter, weight of the wafer is again measured in units of 1/1000 g after rinsing and drying treatment of the wafer, and then an actual etching amount is calculated from a difference between weight before and after etching of the wafer, confirming an etching rate each time etching to thereby control an etching time.

Abstract: Methods of selectively etching BPSG over TEOS are disclosed. In one embodiment, a TEOS layer may be used to prevent contamination of other components in a semiconductor device by the boron and phosphorous in a layer of BPSG deposited over the TEOS layer. An etchant of the present invention may be used to etch desired areas in the BPSG layer, wherein the high selectivity for BPSG to TEOS of etchant would result in the TEOS layer acting as an etch stop. A second etchant may be utilized to etch the TEOS layer. The second etchant may be less aggressive and, thus, not damage the components underlying the TEOS layer.

Abstract: A method for fabricating a semiconductor device to enlarge a channel region is provided. The channel region is enlarged due to having pillar shaped sidewalls of a transistor. The transistor includes a fin active region vertically protruding on a substrate, an isolation layer enclosing a lower portion of the fin active region, and a gate electrode crossing the fin active region and covering a portion of the fin active region. An isolation layer is formed enclosing a lower portion of the fin active region and the isolation layer under the spacers is partially removed to expose a portion of the sidewalls of the fin active region. Subsequently, dry etching is performed to form the sidewalls having a pillar/neck.

Abstract: Provided is a method for manufacturing a floating structure of a MEMS. The method for manufacturing a floating structure of a microelectromechanical system (MEMS), comprising the steps of: a) forming a sacrificial layer including a thin layer pattern doped with impurities on a substrate; b) forming a support layer on the sacrificial layer; c) forming a structure to be floated on the support layer by using a subsequent process; d) forming an etch hole exposing both side portions of the thin layer pattern; and e) removing the sacrificial layer through the etch hole to form an air gap between the support layer and the substrate.

Abstract: A process for manufacturing a semiconductor device, comprising: preparing a substrate in which a silicon-containing resist pattern is formed on a processed-material layer, dry-etching the processed-material layer using the silicon-containing resist pattern as a mask to form a processed-material layer pattern, ashing the silicon-containing resist pattern to leave a silicon-containing residual resist, immersing the substrate on which the silicon-containing residual resist remains into pure water to swell and deform the silicon-containing residual resist, and immersing the substrate on which the swelled and deformed silicon-containing residual resist remains into diluted hydrofluoric acid to remove the silicon-containing residual resist.

Abstract: A method of manufacturing the semiconductor device is provided, which provides a prevention for a “dug” of a silicon substrate caused by the etching in regions except a region for forming a film during a removal of the film with a chemical solution. A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first silicon oxide film on a surface of a silicon substrate or on a surface of a gate electrode when a silicon nitride film for a dummy side wall is etched off, to provide a protection for such surfaces, and then etching a portion of the silicon nitride film with a chemical solution, and then a second oxide film for supplementing a simultaneously-etched portion of the first silicon oxide film is formed, and eventually performing an etching for completely removing the silicon nitride film for the dummy side wall.

Abstract: By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions.

Abstract: The present invention relates to a novel printable etching medium having non-Newtonian flow behaviour for the etching of surfaces in the production of solar cells, and to the use thereof. The present invention furthermore also relates to etching and doping media which are suitable both for the etching of inorganic layers and also for the doping of underlying layers. In particular, they are corresponding particle-containing compositions by means of which extremely fine structures can be etched very selectively without damaging or attacking adjacent areas.

Abstract: In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer 106 includes columnar interconnects which may be fabricated by etching a conductive member such as copper foil, for example. In one application, the pitch or center to center spacing of the columnar interconnects may be defined by masking techniques to provide an interconnect pitch suitable for a particular application. In yet another aspect, etching rates may be controlled to provide height to width aspect ratios of the columnar interconnects which are suitable for various applications.

Abstract: A method for forming a photoresist pattern includes forming a photoresist, and forming a photoresist pattern having a step portion by performing a light exposure process a different number of times according to a region. A method for manufacturing a display panel and a method for manufacturing a display device are also provided.

Abstract: The invention includes methods of cleaning a surface of a cobalt-containing material, methods of forming an opening to a cobalt-containing material, semiconductor processing methods of forming an integrated circuit comprising a copper-containing conductive line, and cobalt-containing film cleaning solutions. In one implementation, a method of cleaning a surface of a cobalt-containing material includes forming a cobalt-containing material over a substrate. The surface of the cobalt-containing material is exposed to an aqueous mixture. The aqueous mixture has an acidic pH and comprises acetic acid, a multiprotic acid, and HF. Other aspects and implementations are contemplated.

Abstract: In a method of chemically and mechanically polishing a layer, a substrate on which the layer having stepped portions is formed is prepared. The layer is primarily chemically and mechanically polished at a temperature of about 30° C. to about 80° C. to remove the stepped portions of the layer. The layer is secondarily chemically and mechanically polished without the stepped portions at a temperature of about 5° C. to about 25° C. to form a flat layer having a desired thickness. Thus, the stepped portions may be rapidly removed in an initial period so that the method may have an improved throughput.

Abstract: A moving element includes at least a substrate including a support, a moving body, and an elastic body connecting the moving body to the support. The support includes a buried film formed in it. The buried film of the support is formed only near end faces of the support that faces the moving body.

Abstract: A method of a CMOS image sensor is disclosed. A method of manufacturing a CMOS image sensor includes forming an epi layer formed over a semiconductor substrate including a pixel region and a peripheral region. At least one oxide film may be formed over the epi layer, including the peripheral region and an upper pad formed therein. A nitride film may be formed over the oxide film. A primary array etching process may be performed with respect to the nitride film using a first photoresist pattern for opening a main pixel region in the pixel region. A secondary array etching process may be performed with respect to the nitride film and the oxide film using a second photoresist pattern for opening the upper pad. The oxide film of the pixel region may be obliquely removed to a predetermined depth. A plurality of color filters and a plurality of micro lenses may be formed over the pixel region after the secondary array etching process.

Abstract: A manufacturing process technology creates a pattern on a first layer using a focused ion beam process. The pattern is transferred to a second layer, which may act as a traditional etch stop layer. The pattern can be formed on the second layer without irradiation by light through a reticle and without wet chemical developing, thereby enabling conformal coverage and very fine critical feature control. Both dark field patterns and light field patterns are disclosed, which may enable reduced or minimal exposure by the focused ion beam.

Abstract: A capacitor can prevent a problem of step coverage in semiconductor device, caused by a thickness of an insulator film and an upper metal film included a metal-insulator-metal (MIM) capacitor, between the MIM capacitor region and its circumferential region. A capacitor in a semiconductor device includes a first metal film provided with a recess having a predetermined depth over a semiconductor substrate. An insulator film and a second metal film may be formed in the recess with a thickness corresponding to a depth of the recess. The insulator and second metal films are disconnected from an inner lateral side of the recess. A dielectric film including a plurality of plugs is in contact with the first and second metal films and the insulator film. A plurality of metal electrodes is in contact with the plugs over the dielectric film.

Abstract: An etching method in a semiconductor device includes forming a nitride-based first hard mask layer over a target etch layer, forming a carbon-based second hard mask pattern over the first hard mask layer, etching the first hard mask layer using the second hard mask pattern as an etch barrier to form a first hard mask pattern, cleaning a resultant structure including the first hard mask pattern, and etching the target etch layer using the second hard mask pattern as an etch barrier.

Abstract: Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O2 and one or more fluorocarbons. The openings formed in the silicon oxide-containing material may be utilized for fabrication of container capacitors, and such capacitors may be incorporated into DRAM.

Abstract: A method for protecting exposed silicon from attack by phosphoric acid during wet etching and stripping processes is provided. According to various embodiments of the method, a thick chemical oxide layer can be formed on the exposed silicon to protect the exposed portion from etching by phosphoric acid. The method can include exposing the silicon to at least one of a hot ozonated sulfuric acid and a hot peroxide sulfuric acid to form the thick chemical oxide.

Abstract: By forming a protection layer on the back side of a substrate prior to any process sequences, which may deposit material or material residues on the back side, the respective back side uniformity may be significantly enhanced, thereby also increasing process efficiency of subsequent back side critical processes, such as lithography, back end of line processes and the like. In one illustrative embodiment, silicon carbide may be used as a material for forming a respective protection layer.

Abstract: An etchant which includes an aqueous solution of between about 30% and about 38% concentrated hydrogen peroxide, said percentages being by volume, based on the total volume of the solution; between about 3.5 ml and about 20 ml per liter of phosphoric acid; and an amount of potassium hydroxide to adjust the pH of the solution to between about 7.8 and about 9.1. The etchant is useful in removing a layer of an alloy of titanium and tungsten or a layer of tungsten from a precision surface.

Abstract: A solution for wet etching a copper film within a ball limiting metallurgy (BLM) of a semiconductor device includes, in an exemplary embodiment, an ammonium persulfate etching agent, a potassium sulfate passivation agent for protecting a PbSn solder material, and a pH modifier for controlling the etch rate of the copper film.

Abstract: A method of planar etching of dissimilar materials with a Focused Ion Beam (FIB) system such as the OptiFIB manufactured by Credence Systems. The method includes adjusting the selectivity between the two materials, which varies when the ratio of the assisting chemistry pressure to the ion dose rate changes. This method can be used in such applications as FIB circuit edit, failure analysis, and cross sectioning.

Abstract: A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the of the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.

Abstract: There is provided a semiconductor wafer fabricating method comprising at least: a double-side polishing step of mirror-polishing a front surface and a back surface of a semiconductor wafer; and a mirror edge polishing step of mirror-polishing a chamfered part of the double-side-polished semiconductor wafer, wherein a protection film made of a resin which suppresses polishing is formed on the front surface or both the front and back surfaces of the semiconductor wafer after the double-side polishing step, then the mirror edge polishing step is carried out, and thereafter the protection film made of a resin is removed. As a result, it is possible to provide a step of eliminating an increase in a cost due to, e.g.

Abstract: A method of using a film formation apparatus for a semiconductor process includes a step of removing a by-product film deposited on an inner surface of a reaction chamber of the film formation apparatus. This step is performed while supplying a cleaning gas containing hydrogen fluoride into the reaction chamber, and forming a first atmosphere within the reaction chamber, which allows water to be present as a liquid film.

Abstract: a semiconductor Array and method for Manufacturing a semiconductor array is provided that includes a substrate, an element layer of a single-crystal semiconductor material, an isolation layer that is formed between the substrate and the element layer and isolates the element layer from the substrate, a number of elements that are formed in the element layer, a trench structure that is adjacent to the isolation layer and that is filled with a filling, to isolate at least one element of the number of elements within the element layer in a lateral direction, whereby the filling has a dielectric, and a self-supporting microstructure that is formed in a structure region defined by the trench structure.

Abstract: A method for fabricating capacitor in a semiconductor device includes forming an sacrificial layer and over a substrate, forming a mask pattern over the sacrificial layer, etching the sacrificial layer in two steps with differentiated top and bottom power levels using the mask pattern as an etch mask to form an opening, and forming a bottom electrode over the opening.

Abstract: An etching liquid used for selectively etching silicon nitride, the etching liquid includes: water; a first liquid that can be mixed with the water to produce a mixture liquid having a boiling point of 150° C. or more; and a second liquid capable of producing protons (H+). Alternatively, an etching liquid includes: water; phosphoric acid; and sulfuric acid, the phosphoric acid and the sulfuric acid having a volume ratio of 300:32 to 150:300.

Abstract: A method that controls the distribution of plasma generated in a vacuum chamber, for example, as part of a plasma thin film deposition or plasma etching process. For thin film deposition, the method serves to minimize variations in film thickness caused by the variations of the film deposition conditions. The vacuum chamber includes a high-frequency-wave electrode connected to a high-frequency electric power supply and an earth electrode connected to ground potential. High frequency-electric power is fed to the high-frequency-wave electrode and peak-to peak voltages are measured at multiple measuring points on one of the two electrodes. The distribution of the plasma is controlled by adjusting the chamber pressure to minimize the differences between the measured peak-to-peak voltages.

Abstract: Provided is: a process for producing safely at low cost a semiconductor substrate excellent in photoelectric transduction efficiency, in which a fine uneven structure suitable for a solar cell can be formed uniformly with desired size on the surface of the semiconductor substrate; a semiconductor substrate for solar application in which a uniform and fine pyramid-shaped uneven structure is provided uniformly within the surface thereof; and an etching solution for forming a semiconductor substrate having a uniform and fine uneven structure. A semiconductor substrate is etched with the use of an alkali etching solution containing at least one kind selected from the group consisting of carboxylic acids having a carbon number of 1 to 12 and having at least one carboxyl group in a molecule, and salts thereof, to thereby form an uneven structure on the surface of the semiconductor substrate.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of oxide film and uniformity in thickness of the oxide film.