Abstract: An apparatus for wet etching metal from a semiconductor wafer comprises a wafer holder for rotating a wafer and a plurality of nozzles for applying separate flow patterns of etching liquid to the surface of the wafer. The flow patterns impact the wafer in distinct band-like impact zones. The flow pattern of etching liquid from at least one nozzle is modulated during a total etching time control the cumulative etching rate in one local etch region relative to the cumulative etching rate in one or more other local etch regions. Some embodiments include a lower etch chamber and an upper rinse chamber separated by a horizontal splash shield. Some embodiments include a retractable vertical splash shield used to prevent splashing of etching liquid onto the inside walls of a treatment container. An etch-liquid delivery system includes a plurality of nozzle flow paths having corresponding nozzle flow resistances, and a plurality of drain flow paths having corresponding drain flow resistances.

Abstract: A pattern size is arbitrarily adjusted with the use of the same template in imprint lithography.

Abstract: A method for removing (e.g., etching) different dielectric materials from a semiconductor substrate includes exposing the semiconductor substrate to a solution at temperatures below and at or above a set threshold. Below the threshold temperature, the solution removes one dielectric material (e.g., silicon nitride) faster than it removes another, different dielectric material (e.g., silicon oxide). At or above the threshold temperature, the selectivity of the solution is reversed.

Abstract: Exposed copper regions on a semiconductor substrate can be etched by a wet etching solution comprising (i) one or more complexing agents selected from the group consisting of bidentate, tridentate, and quadridentate complexing agents; and (ii) an oxidizer, at a pH of between about 5 and 12. In many embodiments, the etching is substantially isotropic and occurs without visible formation of insoluble species on the surface of copper. The etching is useful in a number of processes in semiconductor fabrication, including for partial or complete removal of copper overburden, for planarization of copper surfaces, and for forming recesses in copper-filled damascene features. Examples of suitable etching solutions include solutions comprising a diamine (e.g., ethylenediamine) and/or a triamine (e.g., diethylenetriamine) as bidentate and tridentate complexing agents respectively and hydrogen peroxide as an oxidizer.

Abstract: A process for producing a silicon wafer comprising a single-wafer etching step of performing an etching by supplying an etching solution through a supplying-nozzle to a surface of a single and a thin-discal wafer obtained by slicing a silicon single crystal ingot and rotating the wafer to spread the etching solution over all the surface of the wafer; and a grinding step of grinding the surface of the wafer, in this order, wherein the etching solution used in the single-wafer etching step is an aqueous acid solution which contains hydrogen fluoride, nitric acid, and phosphoric acid in an amount such that the content of which by weight % at a mixing rate of fluoric acid:nitric acid:phosphoric acid is 0.5 to 40%:5 to 50%:5 to 70%, respectively.

Abstract: In accordance with the invention, a lateral dimension of a microscale device on a substrate is reduced or adjusted by the steps of providing the device with a soft or softened exposed surface; placing a guiding plate adjacent the soft or softened exposed surface; and pressing the guiding plate onto the exposed surface. Under pressure, the soft material flows laterally between the guiding plate and the substrate. Such pressure induced flow can reduce the lateral dimension of line spacing or the size of holes and increase the size of mesas. The same process also can repair defects such as line edge roughness and sloped sidewalls. This process will be referred to herein as pressed self-perfection by liquefaction or P-SPEL.

Abstract: The edge profile (and optionally the physical and electrical characteristics) of a wafer is determined. Useful regions of the wafer in an edge exclusion zone may then be identified. A customized grid array layout is created specific to that wafer from an analysis of the edge profile, for example having a grid array with interconnection lines located within the useful portions of the edge exclusion zone. This working file is then used by a system, such as a digital lithography system, to form the grid array on the surface of the wafer. The grid array is specific to that wafer. Various aspects of the grid array may also be controlled in the process. For example, the line width, inter-line spacing, and position of the lines comprising the grid array are configurable on a wafer-by-wafer basis.

Abstract: Provided is a method for performing etching process or film forming process to a substrate W whereupon a prescribed pattern is formed with an opening. The method is provided with a step of mixing a liquid and a gas, at least one of which contains a component that contributes to the etching process or the film forming process, and generating charged nano-bubbles 85 having a diameter smaller than that of the opening formed on the semiconductor substrate W; a step of forming an electric field to attract the nano-bubbles onto the surface of the substrate W; and a step of performing the process by supplying the substrate with the liquid containing the nano-bubbles 85 while forming the electric field.

Abstract: A self-aligned pitch fragmentation method for manufacturing an integrated circuit includes forming openings in a first layer, wherein the openings uncover first sections of a second layer arranged below the first layer. The first sections of the second layer are removed. The first layer is shrunk and the openings are expanded to form a first mask from the first layer, wherein the first mask exposes second sections and covers third sections of the second layer. The etch properties of the second sections are altered selectively to the third sections to facilitate the self-aligned pitch fragmentation method.

Abstract: First and second sacrificial materials are deposited on a substrate. The first and second patterns are respectively formed in the first and second sacrificial materials. The first pattern made from the first sacrificial material is arranged on the second pattern made from a second sacrificial material. The first pattern leaves an area of predefined width free on the periphery of a top surface of the second pattern. The active layer covers at least the whole of the side walls of the first and second patterns and said predefined area of the second pattern. The active area is patterned so as to allow access to the first sacrificial material. The first and second sacrificial materials are selectively removed forming a mobile structure comprising a free area secured to the substrate by a securing area.

Abstract: A filter connectable to an external circulating system, the circulating system being included by a substrate treatment apparatus which etches a substrate with an H3PO4 solution, the filter includes: a chemical feeding port which permits feed of H3PO4 solution containing particles deposited due to etching of a substrate; an H2O adding port which permits the addition of H2O; a filter film which removes the particles from the H3PO4 solution whose heat distribution is made ununiform by the addition of H2O; and a protection member which is disposed between the H2O adding port and the filter film and which protects the filter film from bumping of the H3PO4 solution that is causable by the addition of H2O.

Abstract: The disclosure concerns a manufacturing method of a semiconductor device includes dry-etching a semiconductor substrate or a structure formed on the semiconductor substrate; supplying a solution onto the semiconductor substrate; measuring a specific resistance or a conductivity of the supplied solution; and supplying a removal solution for removing the etching residual material onto the semiconductor substrate for a predetermined period of time based on the specific resistance or the conductivity of the solution, when an etching residual material adhering to the semiconductor substrate or the structure is removed.

Abstract: A semiconductor wafer is produced by a method comprising a slicing step of cutting out a thin disc-shaped semiconductor wafer from a crystalline ingot; a fixed grain bonded abrasive grinding step of sandwiching the semiconductor wafer between a pair of upper and lower plates each having a pad of fixed grain bonded abrasive to simultaneously grind both surfaces of the semiconductor wafer; and a one-side polishing step subjected to both surfaces of the semiconductor wafer after the fixed grain bonded abrasive grinding step.

Abstract: A semiconductor wafer is produced by a method comprising a slicing step, an one-side polishing step and a chemical treating step, in which the kerf loss is reduced and the flatness is improved.

Abstract: The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.

Abstract: A semiconductor device is provided with a semiconductor substrate having circuit elements formed therein, and an insulating protective film formed on the semiconductor substrate. Hydroxyl groups (OH) are attached to a surface of the protective film. As a result, the contact angle between surface of the protective film and a water droplet is less than or equal to 40 degrees.

Abstract: The invention includes an etchant composition containing isopropyl alcohol and one or more of HF, NH4F and tetramethyl ammonium fluoride (TMAF). The invention encompasses a method of processing a substrate. A substrate is provided which has a first material containing at least one of polysilicon, monocrystalline silicon and amorphous silicon, and a second material. The substrate is exposed to an etch composition which comprises isopropyl alcohol and at least one of HF, NH4F and TMAF. The invention includes a method of processing a semiconductor construction including providing a construction which has a capacitor electrode material and an oxide material along at least a portion of the capacitor electrode material. At least some of the oxide material is removed by isotropic etching utilizing an etchant composition comprising isopropyl alcohol.

Abstract: The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometers from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method includes fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometers, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the critical lateral extension, using an etchant that selectively removes the etch layer-material relative to the mask-layer material.

Abstract: A method for photoelectrochemical (PEC) etching of a p-type semiconductor layer simply and efficiently, by providing a driving force for holes to move towards a surface of a p-type cap layer to be etched, wherein the p-type cap layer is on a heterostructure and the heterostructure provides the driving force from an internal bias generated internally in the heterostructure; generating electron-hole pairs in a separate area of the heterostructure than the surface to be etched; and using an etchant solution to etch the surface of the p-type layer.

Abstract: In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.

Abstract: A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.

Abstract: A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the substrate in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. One submerges the metallized substrate into an etchant aqueous solution comprising HF and an oxidizing agent. In this way arrays of nanowires with controlled diameter and length are produced.

Abstract: The inventive method for processing a silicon wafer is a method comprising step 11 in which a single crystal ingot is sliced into thin disc-like wafers; step 13 in which the surface of each wafer is lapped to be planar; step 14 in which the wafer is subjected to alkaline cleaning to be removed of contaminants resulting from preceding machining; and step 16 in which the wafer is alternately transferred between two groups of etching tanks one of which contain acidic etching solutions and the other alkaline etching solutions, wherein an additional step 12 is introduced between step 11 and step 13 in which a wafer is immersed in an acidic solution containing hydrofluoric acid (HF) and nitric acid (HNO3) at a volume ratio of ? to ½ (HF/HNO3) so that degraded superficial layers occurring on the front and rear surfaces of the wafer as a result of machining can be removed and the edge surface of the wafer can be beveled.

Abstract: A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming a line-type photoresist pattern on the silicon oxynitride layer such that the photoresist pattern in the cell region has a width larger than that of a final pattern structure and the photoresist pattern in the peripheral region has a width that reduces an incidence of pattern collapse; etching the silicon oxynitride layer and the silicon nitride layer until widths of a remaining silicon oxynitride layer and a remaining silicon nitride layer are smaller than the width of the photoresist pattern used as an etch mask through suppressing generation of polymers; and over-etching the remaining silicon nitride layer.

Abstract: Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate.

Abstract: A semiconductor surface treatment agent containing a fluorine compound, a water-soluble organic solvent and an inorganic acid, with the balance being water and a method for manufacturing a semiconductor device by etching a high dielectric constant insulating material using the subject semiconductor surface treatment agent are provided. According to the present invention, it is possible to selectively and efficiently etch a high dielectric constant insulating material to be used in a transistor formation process of the semiconductor device manufacture; and it is also possible to achieve etching with ease within a short period of time even for a high dielectric constant insulating material to which etching is hardly applied.

Abstract: It is an object of the present invention to provide a semiconductor device including a wiring having a preferable shape. A manufacturing method includes the steps of forming a first conductive layer connected to an element and a second conductive layer thereover; forming a resist mask over the second conductive layer; processing the second conductive layer by dry etching with the use of the mask; and processing the first conductive layer by wet etching with the mask left, wherein the etching rate of the second conductive layer is higher than that of the first conductive layer in the dry etching, and wherein the etching rate of the second conductive layer is the same as or more than that of the first conductive layer in the wet etching.

Abstract: In a method for texturing silicon wafers for producing solar cells, the step of introducing a silicon wafer involves the use of a texturing solution which is at a temperature of at least 80 degrees Celsius and which comprises water admixed with 1 percent by weight to 6 percent by weight KOH or 2 percent by weight to 8 percent by weight NaOH and with a surfactant or a surfactant mixture constituting less than 0.01 percent by weight. Very economic texturing can be performed in this way.

Abstract: A discharge hole of a lower nozzle is directed at an angle of 5 degrees to 40 degrees slanting inward with respect to a normal to the upper surface of a bottom plate. Thus, the flow pressure of a processing solution discharged through the discharge hole is not excessively reduced. Further, a circulation area of the processing solution does not expand widely in an inner bath. As a result, the processing solution in the inner bath is effectively displaced while the processing solution smoothly flows into gaps between substrates.

Abstract: A method of recycling a control wafer having a dielectric layer deposited thereon involves removing most of the dielectric layer by plasma etching leaving a residual film of the dielectric and then removing the residual dielectric film by a wet etching process. The combination of the dry and wet etching provides effective removal of the dielectric material without damaging the wafer substrate and any residual wet etching byproduct particulate remaining on the wafer substrate is then removed by APM cleaning and scrubbing.

Abstract: The present invention relates to methods of forming substrate elements, including semiconductor elements such as nanowires, transistors and other structures, as well as the elements formed by such methods.

Abstract: Disclosed are an etching solution for a substrate and a substrate-etching method, which can prevent the contamination of a substrate, particularly a semiconductor substrate, with metal impurities. The etching solution comprises a dicarboxylic acid represented by the general formula (1) or a salt thereof and 20% (W/W) or more of an alkali metal hydroxide. The substrate-etching method comprises the step of etching a substrate with said etching solution.

Abstract: Methods in accordance with the invention involve patterning and etching very small dimension pillars, such as in formation of a memory array in accordance with the invention. When dimensions of pillars become very small, the photoresist pillars used to pattern them may not have sufficient mechanical strength to survive the photoresist exposure and development process. Using methods according to the present invention, these photoresist pillars are printed and developed larger than their intended final dimension, such that they have increased mechanical strength, then are shrunk to the desired dimension during a preliminary etch performed before the etch of underlying material begins.

Abstract: New temporary bonding methods and articles formed from those methods are provided. The methods comprise bonding a device wafer to a carrier wafer or substrate only at their outer perimeters in order to assist in protecting the device wafer and its device sites during subsequent processing and handling. The edge bonds formed by this method are chemically and thermally resistant, but can also be softened, dissolved, or mechanically disrupted to allow the wafers to be easily separated with very low forces and at or near room temperature at the appropriate stage in the fabrication process.

Abstract: A method of fabricating a semiconductor device according to an embodiment includes: forming a core material on a workpiece material; forming a cover film to cover the upper and side surfaces of the core material; after forming the cover film, removing the core material; after removing the core material, removing the cover film while leaving portions thereof located on the side surfaces of the core material, so as to form sidewall spacer masks; and etching the workpiece material by using the sidewall spacer masks as a mask.

Abstract: Etching solution for etching a layer system that has at least one layer of aluminum, at least one layer of copper and at least one third layer, selected from nickel vanadium, nickel and alloys thereof, which is arranged between the at least one aluminum layer and the at least one copper layer, wherein the solution contains phosphoric acid, nitric acid, deionized water and at least one salt that can release halogen ions, or comprises these components. The claimed etching solution is the basis for a one-step structuring method of a UBM layer system which is used in the production of components that are produced by semiconductor technology methods.

Abstract: Method for fabricating a semiconductor device, including the steps of providing a first conductive type semiconductor substrate having a cell region and a logic region defined thereon, forming a first insulating film, second conductive type polysilicon, and a second insulating film in succession on the semiconductor substrate, selectively removing the first insulating film, the polysilicon, and the second insulating film, to form a floating gate pattern at the cell region, elevating a temperature initially in a state O2 gas is injected, maintaining a fix temperature, and dropping the temperature in a state N2 gas is injected, to form a gate oxide film on a surface of the semiconductor substrate at the logic region, and forming a gate electrode pattern at each of the cell region and the logic region, whereby preventing a threshold voltage of a semiconductor device from dropping due to infiltration of impurities from doped polysilicon at the cell region to the active channel region.

Abstract: The method serves for producing a micromechanical structure element (13) on or in a crystal substrate (3), wherein the micromechanical structure element (13) is arranged in vibratable fashion in a recess (4) of the crystal substrate (3) and is connected to the crystal substrate (3) by means of a web (15), comprising the following steps: providing the crystal substrate (3); depositing an etching mask layer (1); locally removing the etching mask layer (1), such that the remaining etching mask layer (1) has a border (8) extending at a predeterminable angle ? of less than 180° on both sides of a connection region (19) of the web (15) to the crystal substrate (3), and etching the crystal substrate (3) in order to form the recess (4) and the micromechanical structure element (13). What is thereby achieved is that an uncovered crystal plane (7) runs through the connection region (19).

Abstract: The present invention provides an etching solution for revealing defects in a germanium layer, a method for revealing defects in a germanium layer using such an etching solution and to a method for making such an etching solution. The etching solution according to embodiments of the present invention is able to exhibit an etch rate of between 4 nm·min?1 and 450 nm·min?1, which makes it suitable to be used for revealing defects in a thin layer of germanium, i.e. in a layer of germanium with a thickness of between 20 nm and 10 ?m, for example between 20 nm and 2 ?m, between 20 nm and 1 ?m or between 20 nm and 200 nm.

Abstract: A method is provided for post-processing lithographically patterned resists to reduce surface defects on a patterned resist feature. The method includes providing a substrate with a patterned resist feature containing surface defects with convex and concave regions, applying an acid solution to the patterned resist feature to form a surface acid layer on the patterned resist feature, heat-treating the patterned resist feature, where the heat-treating causes acid concentration in the convex regions and acid dispersion in the concave regions. The method further includes exposing the heat-treated patterned resist feature to a developing solution to preferentially remove resist material from the convex regions and form a trimmed patterned resist feature with reduced surface defects. According to one embodiment, the method further includes repeating the applying, heat-treating, and exposing at least once to further trim and reduce surface defects on the trimmed patterned resist feature.

Abstract: A recessed region containing a line portion and a bulge portion is formed in a hard mask layer. Self-assembling block copolymers containing two or more different polymeric block components that are immiscible with one another are applied within the recessed region and annealed. A cylindrical polymeric block centered at the bulge portion is removed selective to a polymeric block matrix surrounding the cylindrical polymeric block. A via cavity is formed by transferring the cavity formed by removal of the cylindrical polymeric block into a dielectric layer. The pattern in the hard mask layer is subsequently transferred into the dielectric layer to form a line cavity. A metal via and a metal line are formed by deposition and planarization of metal. The metal via is self-aligned to the metal line.

Abstract: The present invention relates to a method for manufacturing an acceleration sensor. In the method, thin SOI-wafer structures are used, in which grooves are etched, the walls of which are oxidized. A thick layer of electrode material, covering all other material, is grown on top of the structures, after which the surface is ground and polished chemo-mechanically, thin release holes are etched in the structure, structural patterns are formed, and finally etching using a hydrofluoric acid solution is performed to release the structures intended to move and to open a capacitive gap.

Abstract: A method of forming an electronic device can include forming a patterned mask layer overlying a underlying layer such that the mask layer has a first feature, a second feature, and a third feature, and the first feature is between the second feature and the third feature. The first feature can be spaced apart from the second feature by a first opening in the mask layer, and can be spaced apart from the third feature by a second opening in the mask layer. The method can further include selectively removing portions of the underlying layer under the first opening, the second opening, the second feature, and the third feature, and also removing the second feature and the third feature while leaving substantially all of the first feature and a significant portion of the underlying layer under the first feature.

Abstract: A solar cell and a method of texturing a solar cell are disclosed. The method includes coating an ink containing metal particles on a surface of a substrate, drying the ink to attach the metal particles to the surface of the substrate, and differentially etching the surface of the substrate using the metal particles as a catalyst to form an uneven portion.

Abstract: The invention relates to a process for producing a semiconductor wafer by double-side grinding of the semiconductor wafer, in which the semiconductor wafer is simultaneously ground on both sides, first by rough-grinding and then by finish-grinding, using a grinding tool. The semiconductor wafer, between the rough-grinding and the finish-grinding, remains positioned in the grinding machine, and the grinding tool continues to apply a substantially constant load during the transition from rough-grinding to finish-grinding. The invention also relates to an apparatus for carrying out the process and to a semiconductor wafer having a local flatness value on a front surface of less than 16 nm in a measurement window of 2 mm×2 mm area and of less than 40 nm in a measurement window of 10 mm×10 mm area.

Abstract: Silicon nano wires having silicon nitride shells and a method of manufacturing the same are provided. Each silicon nano wire has a core portion formed of silicon, and a shell portion formed of silicon nitride surrounding the core portion. The method includes removing silicon oxide formed on the shell of the silicon nano wire and forming a silicon nitride shell.

Abstract: The invention relates to a method for dry chemical treatment of substrates selected from the group comprising silicon, ceramic, glass, and quartz glass, in which the substrate is treated in a heated reaction chamber with a gas which contains hydrogen chloride as etching agent, and also to a substrate which can be produced in this way. The invention likewise relates to uses of the previously mentioned method.

Abstract: Certain example embodiments of this invention relate to a photovoltaic (PV) device including an electrode such as a front electrode/contact, and a method of making the same. In certain example embodiments, the front electrode has a textured (e.g., etched) surface that faces the photovoltaic semiconductor film of the PV device. In certain example embodiments, the front electrode is formed on a flat or substantially flat (non-textured) surface of a glass substrate (e.g., via sputtering), and the surface of the front electrode is textured (e.g., via etching). In certain example embodiments, a combination of two or more different etchants can be used in order to provide the front electrode with a textured surface having at least two different feature sizes. In completing manufacture of the PV device, the etched surface of the front electrode faces the active semiconductor film of the PV device.

Abstract: A device mounting board includes: an insulating resin layer; a wiring layer disposed on one main surface of the insulating resin layer; and a bump electrode connected electrically to the wiring layer and protruding on a side of the insulating resin layer from the wiring layer. A side surface of the bump electrode is curved inwardly toward the center axis of the bump electrode as viewed in a cross section including the center axis of the bump electrode, and the radius of curvature of the side surface changes continuously from a wiring layer end to a head end of the bump electrode.