Abstract: Provided are: a safe, low-cost method of producing a polycrystalline silicon substrate excellent in photoelectric conversion efficiency by which a uniform, fine uneven structure suited to a solar cell can be simply formed on the surface of the polycrystalline silicon substrate; and a polycrystalline silicon substrate having a uniform, fine, pyramid-shaped uneven structure so that its reflectance can be significantly reduced. The uneven structure is formed on the surface of the polycrystalline silicon substrate by etching the polycrystalline silicon substrate with an alkaline etching solution containing at least one kind selected from the group consisting of a carboxylic acid having 1 or more and 12 or less carbon atoms and each having at least one carboxyl group in one molecule, and salts of the acids.

Abstract: In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.

Abstract: The present invention concerns an improved method for treating germanium surfaces in order to reveal crystal defects.

Abstract: The present invention provides a water and a method for strengthening, homogenization and construction thereof. The concave and convex portions are processed by laser or etching, and then formed at intervals on the grinding surface of the wafer. The concave and convex portions are round or polygonal shapes. With the alternated arrangement of the concave and convex portions, a mesh structure of consistent construction is formed on the grinding surface of the wafer, making it possible to cut down greatly the interference and influence generated by the texture of grinding surface, and improve substantially the structural strength of the grinding surface for a consistent quality of wafer with better applicability and industrial benefits.

Abstract: A method of manufacturing a semiconductor device, the method including forming a photoresist film on a substrate, and removing the photoresist film from the substrate using a composition that includes a sulfuric acid solution, a hydrogen peroxide solution, and a corrosion inhibitor.

Abstract: In a method of vapor etching, a sample that includes a first layer atop of and in contact with a second layer which is atop of and in contact with a third layer, wherein at least the first and second layers are comprised of different materials. The sample is etched by a vapor etchant under first process conditions that cause at least a part of the first layer to be fully removed while leaving the third layer and the second layer underlying the removed part of the first layer substantially unetched. The sample is then etched by the same or a different vapor etchant under second process conditions that cause at least the part of the second layer exposed by the removal of the at least part of the first layer to be fully removed while leaving the third layer underlying the removed part of the second layer substantially unetched.

Abstract: Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.

Abstract: A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.

Abstract: A fin field effect transistor (FinFET) memory cell and method of formation has a substrate for providing mechanical support. A first dielectric layer overlies the substrate. A fin structure overlies the dielectric layer and has a first current electrode and a second current electrode separated by a channel. A floating gate has a vertical portion that is adjacent to and electrically insulated from a side of the channel and has a horizontal portion overlying the first dielectric layer and extending laterally away from the channel. The floating gate stores electrical charge. A second dielectric layer is adjacent the floating gate. A control gate adjacent the second dielectric layer and physically separated from the floating gate by the second dielectric layer. The “L-shape” of the floating gate enhances capacitive coupling ratio between the control gate and the floating gate.

Abstract: A method is provided for thinning a wafer, for example a wafer containing Through Silicon Vias (TSV). The method includes providing a bonding wafer coupled to a handling wafer, and performing a wafer edge trimming process that forms a trimmed bonding wafer, where the wafer edge trimming process removes an edge portion of the bonding wafer and exposes an upper surface of the handling wafer. The method further includes forming a protective mask on the trimmed bonding wafer and on the exposed upper surface of the handling wafer, planarizing the protective mask and the trimmed bonding wafer, and selectively removing the planarized protective mask by an etching process. In one embodiment, the removing includes performing a first wet etching process that selectively removes a portion of the planarized trimmed bonding wafer relative to the planarized protective mask, and performing a second wet etching process that selectively removes the planarized protective mask.

Abstract: Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.

Abstract: Disclosed herein are various embodiments related to metal-assisted chemical etching of substrates on the micron, sub-micron and nano scales. In one embodiment, among others, a method for metal-assisted chemical etching includes providing a substrate; depositing a non-spherical metal catalyst on a surface of the substrate; etching the substrate by exposing the non-spherical metal catalyst and the substrate to an etchant solution including a composition of a fluoride etchant and an oxidizing agent; and removing the etched substrate from the etchant solution.

Abstract: Described herein are exemplary methods and apparatuses for etching a nitride layer disposed above a substrate to form trenches without micro-trenching in accordance with one embodiment. The method includes forming openings in a resist layer and one or more dielectric layers. The dielectric layers may be disposed on a hard mask layer (e.g., nitride, polysilicon). Next, the method includes etching openings in the hard mask layer disposed above a substrate layer without micro-trenching. The etching occurs in a process chamber during a main etch with a first process gas mixture having a fluorocarbon gas, a hydrofluorocarbon gas, and an oxygenating gas. Next, the method includes etching openings partially into the substrate without micro-trenching with a second process gas mixture during an over etch having the fluorocarbon gas, the hydrofluorocarbon gas, and the oxygenating gas.

Abstract: A method of forming fine patterns of a semiconductor device by using carbon (C)-containing films includes forming an etching target film on a substrate including first and second regions; forming a plurality of first C-containing film patterns on the etching target film in the first region; forming a buffer layer which covers top and side surfaces of the plurality of first C-containing film patterns; forming a second C-containing film; removing the second C-containing film in the second region; exposing the plurality of first C-containing film patterns by removing a portion of the buffer layer in the first and second regions; and etching the etching target film by using the plurality of first C-containing film patterns, and portions of the second C-containing film which remain in the first region, as an etching mask.

Abstract: A silicon etching liquid characterized by anisotropically dissolving monocrystalline silicon therein by using an aqueous solution containing a quaternary ammonium hydroxide and an aminoguanidine salt and an etching method of silicon using the instant etching liquid are an etching liquid and an etching method enabling one to perform processing at a high etching rate in etching processing of silicon, particularly in etching processing of silicon in a manufacturing process of MEMS parts or semiconductor devices.

Abstract: A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming a line-type photoresist pattern on the silicon oxynitride layer such that the photoresist pattern in the cell region has a width larger than that of a final pattern structure and the photoresist pattern in the peripheral region has a width that reduces an incidence of pattern collapse; etching the silicon oxynitride layer and the silicon nitride layer until widths of a remaining silicon oxynitride layer and a remaining silicon nitride layer are smaller than the width of the photoresist pattern used as an etch mask through suppressing generation of polymers; and over-etching the remaining silicon nitride layer.

Abstract: A method of texturizing a silicon substrate comprising a) contacting the substrate with an etching solution comprising glycolic acid, b) etching a surface of the substrate thereby forming disruptions in said surface of the substrate, and c) removing the etching solution to yield a texturized substrate, said texturized substrate having a plurality of disruptions in at least one surface with a surface density of disruptions of a minimum of 60 disruptions in a 400 micron square area.

Abstract: A method is described of selectively etching a silicon substrate in small local areas in order to form columns or pillars in the etched surface. The silicon substrate is held in an etching solution of hydrogen fluoride, a silver salt and an alcohol. The inclusion of the alcohol provides a greater packing density of the silicon columns.

Abstract: A process apparatus and a method for making semiconductor devices is implemented in a semiconductor equipment and utilizes three magnetic objects arranged in a helical path. Chemicals within the chemical pipe are magnetized, and the chemicals include etch acids, photoresist stripper and clean chemicals. Then, efficiency of semiconductor process is increased.

Abstract: A semiconductor optoelectronic device with enhanced light extraction efficiency includes at least one protrusion structure, which can be formed around a light-emitting region of the device. The at least one protrusion structure can include a plurality of protrusion structures in one embodiment. In addition, a fabricating method for forming a semiconductor optoelectronic device with enhanced light extraction efficiency is provided in the present invention.

Abstract: Provided are a substrate processing apparatus and a method of manufacturing a semiconductor device which can prevent a sealing member from being deteriorated due to a thermal radiation from a heater. The substrate processing apparatus includes a processing container, a substrate stage installed in the processing container, on which a substrate is placed, a heater installed in the substrate stage and configured to heat the substrate, a thermal radiation attenuator adjacent to the processing container, and a gas supply pipe connected to a gas inlet part with a sealing member interposed therebetween and configured to supply a processing gas to an inside of the processing container, wherein the thermal radiation attenuator is installed on a line connecting the heater and the sealing member.

Abstract: Disclosed herein is a method of fabricating a device having a microstructure. The method includes forming a connector on a semiconductor substrate, coating the connector with a polymer layer, and immersing the semiconductor substrate and the coated connector in an etchant solution to form the microstructure from the semiconductor substrate and to release the coated connector and the microstructure from the semiconductor substrate such that the microstructure remains coupled to a further element of the device via the coated connector. In some cases, the microstructure is defined by forming an etch stop in the semiconductor substrate, and the microstructure and the semiconductor substrate are coated with a polymer layer, which may then be selectively patterned. The microstructure may then be released from the semiconductor substrate in accordance with the etch stop.

Abstract: The invention includes methods in which one or more components of a carboxylic acid having an aqueous acidic dissociation constant of at least 1×10?6 are utilized during the etch of oxide (such as silicon dioxide or doped silicon dioxide). Two or more carboxylic acids can be utilized. Exemplary carboxylic acids include trichloroacetic acid, maleic acid, and citric acid.

Abstract: A method for selective etching of an SiGe mixed semiconductor layer on a silicon semiconductor substrate by dry chemical etching of the SiGe mixed semiconductor layer with the aid of an etching gas selected from the group including ClF3 and/or ClF5, a gas selected from the group including Cl2 and/or HCl being added to the etching gas.

Abstract: A method for processing a semiconductor structure includes the steps of capping a top surface of the semiconductor structure that defines the metallization layer with a thin stop layer, forming a dielectric layer over the thin stop layer, wherein the dielectric layer defines at least one area where the thin stop layer is exposed, and removing the exposed thin stop layer to expose a top surface of the metallization layer using etchant gases substantially free from oxygen, so that the metallization layer is substantially free of damage.

Abstract: A process for selectively freeing an epitaxial layer from a single crystal substrate upon which it was grown, by providing a first substrate; depositing a separation layer on said first substrate; depositing on said separation layer a sequence of layers of semiconductor material forming a solar cell; mounting and bonding a surrogate substrate on top of the sequence of layers; attaching a connecting link element to at least two opposed points on the periphery of the surrogate substrate; and etching said separation layer while applying tension to said link element so as to remove said epitaxial layer from said first substrate.

Abstract: Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern.

Abstract: A method and apparatus for selective etching a substrate using a focused beam. For example, multiple gases may be used that are involved in competing beam-induced and spontaneous reactions, with the result depending on the materials on the substrate. The gases may include, for example, an etchant gas and an auxiliary gas that inhibits etching.

Abstract: Methods for performing damage etch and texturing of single crystal silicon substrates, particularly for use as solar cells or photovoltaic cells. Damage etch with a TMAH solution followed by texturing using solution of KOH or NaOH mixed with IPA is particularly advantageous. The substitution of some of the IPA with ethylene glycol further improves results. Also disclosed is a process that combines both damage etch and texturing etch into a single step.

Abstract: A method of cleaning for removing metal compounds attached to a surface of a substrate, wherein the cleaning is conducted by supplying a supercritical fluid of carbon dioxide comprising at least one of triallylamine and tris(3-aminopropyl)amine to the surface of the substrate and a process for producing a semiconductor device using the method of cleaning are provided. In accordance with the method of cleaning and the method for producing a semiconductor device using the method, etching residues or polishing residues containing metal compounds are efficiently removed selectively from the electroconductive material forming the electroconductive layer. When the electroconductive layer is a wiring, an increase in resistance due to residual metal compounds can be suppressed, and an increase in the leak current due to diffusion of the metal from the metal compounds to the insulating film can be prevented. Therefore, reliability on the wiring is improved, and the yield of the semiconductor device can be increased.

Abstract: The preferred embodiment provides for development and use of an array of nanowires with a period smaller then 150 nm for applications such as an optical polarizer. To manufacture such structures the preferred embodiment employs a hard nanomask. This nanomask includes a substantially periodic array of substantially parallel elongated elements having a wavelike cross-section.

Abstract: In a method of forming fine patterns, a photocurable coating layer is formed on a substrate. A first surface of a template makes contact with the photocurable coating layer. The first surface of the template includes at least two first patterns having a first dispersion degree of sizes, and at least one portion of the first surface of the template includes a photo attenuation member. A light is irradiated onto the photocurable coating layer through the template to form a cured coating layer including second patterns having a second dispersion degree of sizes. The second patterns are generated from the first patterns and the second dispersion degree is less than the first dispersion degree. The template is separate from the cured coating layer. A size dispersion degree of the patterns used in a nanoimprint lithography process may be adjusted by the light attenuation member, so that the fine patterns may be formed to have an improved size dispersion degree.

Abstract: Embodiments of the present invention describe a removal chemistry for removing hard mask. The removal chemistry is a wet-etch solution that removes a metal hard mask formed on a dielectric layer, and is highly selective to a metal conductor layer underneath the dielectric layer. The removal chemistry comprises an aqueous solution of hydrogen peroxide (H2O2), a hydroxide source, and a corrosion inhibitor. The hydrogen peroxide and hydroxide source have the capability to remove the hard mask while the corrosion inhibitor prevents the metal conductor layer from chemically reacting with the hydrogen peroxide and hydroxide source during the hard mask removal.

Abstract: A semiconductor device having fins and a method of manufacture are provided. A patterned mask is formed over a substrate. Trenches are formed in the substrate and the trenches are filled with a dielectric material. Thereafter, the patterned mask is removed and one or more etch processes are performed to recess the dielectric material, wherein at least one of the etch processes is an etch process that removes or prevents fences from being formed along sidewalls of the trench. The etch process may be, for example, a plasma etch process using NH3 and NF3, an etch process using a polymer-rich gas, or an H2 etch process.

Abstract: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a dielectric layer overlying another dielectric layer, contacting the substrate at a first temperature with an acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with an acid solution exhibiting a positive etch selectivity at the second temperature. The dielectric layers exhibit different etch rates when etched at the first and second temperatures. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175° C. and the second temperature may be about 155° C.

Abstract: Methods for processing a microelectronic topography include selectively etching a layer of the topography using an etch solution which includes a fluid in a supercritical or liquid state. In some embodiments, the etch process may include introducing a fresh composition of the etch solution into a process chamber while simultaneously venting the chamber to inhibit the precipitation of etch byproducts. A rinse solution including the fluid in a supercritical or liquid state may be introduced into the chamber subsequent to the etch process. In some cases, the rinse solution may include one or more polar cosolvents, such as acids, polar alcohols, and/or water mixed with the fluid to help inhibit etch byproduct precipitation. In addition or alternatively, at least one of the etch solution and rinse solution may include a chemistry which is configured to modify dissolved etch byproducts within an ambient of the topography to inhibit etch byproduct precipitation.

Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F—] concentration greater than 0.01 M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than ?1.4 volts.

Abstract: The present invention relates to compositions for chemical-mechanical polishing comprising A 0.01% to 40% by weight based on the total amount of the composition of abrasive particles of at least one porous metal-organic framework material, wherein the framework material comprises at least one at least bidentate organic compound which is coordinately bound to at least one metal ion; B 40% to 99.8% by weight based on the total amount of the composition of a liquid carrier; and C 0.01% to 20% by weight based on the total amount of the composition of a polishing additive component. The invention further relates to the use of said composition as well as methods for chemical-mechanical polishing of a surface with the aid of said compositions.

Abstract: Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.

Abstract: We suggest a method of anisotropic etching of the substrates, where ultra-thin and conformable layers of materials are used to passivate sidewalls of the etched features. According to an exemplary embodiment such sidewall passivation layer is a Self-assembled monolayer (SAM) material deposited in-situ etching process from a vapor phase. According to another exemplary embodiment such sidewall passivation layer is an inorganic-based material deposited using Atomic Layer Deposition (ALD) method. SAM or ALD layers deposition can be carried out in a pulsing regime alternating with an sputtering and/or etching processes using process gasses with or without plasma. Alternatively, SAM deposition process is carried out continuously, while etch or sputtering process turns on in a pulsing regime. Alternatively, SAM deposition process and etch or sputtering processes are carried out continuously.

Abstract: A semiconductor substrate shaped to have a curved surface profile by anodization. Prior to being anodized, the substrate is finished with an anode pattern on its bottom surface so as to be consolidated into a unitary structure in which the anode pattern is precisely reproduced on the substrate. The anodization utilizes an electrolytic solution which etches out an oxidized portion as soon as it is formed as a result of the anodization, to thereby develop a porous layer in a pattern in match with the anode pattern. The anode pattern brings about an in-plane distribution of varying electric field intensity by which the porous layer develops into a shape complementary to a desired surface profile. Upon completion of the anodization, the curves surface is revealed on the surface of the substrate by etching out the porous layer and the anode pattern from the substrate.

Abstract: A method for producing a component having at least one diaphragm formed in the upper surface of the component, which diaphragm spans a cavity, and having at least one access opening to the cavity from the back side of the component, at least one first diaphragm layer and the cavity being produced in a monolithic semiconductor substrate from the upper surface of the component, and the access opening being produced in a temporally limited etching step from the back side of the substrate. The access opening is placed in a region in which the substrate material comes up to the first diaphragm layer.

Abstract: A method of manufacturing a semiconductor device may include forming a first oxide film, a nitride film and/or a second oxide film over a substrate, and may include forming a trench over a semiconductor substrate by etching a portion of a first oxide film, a nitride film, a second oxide film and/or a semiconductor substrate. A method of manufacturing a semiconductor device may include performing wet etching to form a divot, which may be performed over a semiconductor substrate having a trench, and/or which may expose a portion of a nitride film. A method of manufacturing a semiconductor device may include removing a second oxide film having a portion thereof etched and a portion of a first oxide film exposed by a divot, while rounding upper edge portions of a trench using a mixed solution of deionized water and HF. A semiconductor device formed by a method is disclosed.

Abstract: A method for manufacturing a semiconductor device comprises performing an exposing and developing process using an exposure mask including shading patterns and assistant patterns arranged in parallel to the shading patterns to prevent a scum phenomenon generated when a main pattern is formed in a cell region over a semiconductor substrate, thereby improving characteristics, reliability and yield of the semiconductor device. As a result, the method enables high-integration of the semiconductor device.

Abstract: A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.

Abstract: Disclosed is a method for smoothing the surface of at least one side of a wafer which is obtained by slicing a semiconductor ingot. In this method, a fluid is applied according to projections of the wafer surface, thereby reducing the projections. Alternatively, a fluid is applied over the wafer surface, thereby smoothing the entire surface of the wafer while reducing the projections in the wafer surface.

Abstract: Embodiments of the invention generally relate to apparatuses and methods for producing epitaxial thin films and devices by epitaxial lift off (ELO) processes. In one embodiment, a method for forming thin film devices during an ELO process is provided which includes coupling a plurality of substrates to an elongated support tape, wherein each substrate contains an epitaxial film disposed over a sacrificial layer disposed over a wafer, exposing the substrates to an etchant during an etching process while moving the elongated support tape, and etching the sacrificial layers and peeling the epitaxial films from the wafers while moving the elongated support tape. Embodiments also include several apparatuses, continuous-type as well as a batch-type apparatuses, for forming the epitaxial thin films and devices, including an apparatus for removing the support tape and epitaxial films from the wafers on which the epitaxial films were grown.

Abstract: A method of removing a multi-layered structure includes the following processes. A semiconductor substrate is prepared. The semiconductor substrate has a multi-layered structure including a first film over the semiconductor substrate, a second film on the first film, and a mask pattern film on the second film. Then, the mask pattern film is removed. Then, the second film is removed by etching the second film with a first etching selectivity of the second film to the first film. The first etching selectivity is greater than a second etching selectivity of the second film to the first film with which the second film is patterned by etching using the mask pattern film. Then, the third film is removed.

Abstract: A method to integrate a micro electro mechanical system and a CMOS image sensor is disclosed. First a substrate is provided. The substrate includes a micro electro mechanical system (MEMS) region and a CMOS image sensor (CIS) region. The micro electro mechanical system region includes a micro electro mechanical system component and the CMOS image sensor region includes a CMOS image sensor element. Second, an etching procedure is performed on the substrate to form a micro electro mechanical system trench and a CMOS image sensor trench. The etching procedure includes at least a dry etching and at least a wet etching.

Abstract: A sample holding tool is provided with a base plate, a plurality of convex portions formed on the base plate so as to stick out from the upper face thereof; and at least one holding plate having a plurality of curved face portions corresponding to the convex portions, with a lower face concave portion of each of the curved face portions being made in contact with the tip portion of each of the convex portions, so that a sample is supported on the upper face convex portion of each of the curved face portions; thus, since the sample is supported by the curved face portion of the holding plate, the contact area to the sample is made very small so that it becomes possible to greatly reduce pointed peak portions, scratches and the like at contact portions between the sample and the curved face portions. Consequently, generation of particles due to abrasion of the sample can be reduced and the particles are reduced from intruding into scratches and voids and occasionally readhering to the sample.