Chemical Etching (epo) Patents (Class 257/E21.219)
  • Publication number: 20100252810
    Abstract: Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.
    Type: Application
    Filed: April 3, 2009
    Publication date: October 7, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas C. M. Fuller, Sarunya Bangsaruntip, Guy Cohen, Sebastian U. Engelmann, Lidija Sekaric, Qingyun Yang, Ying Zhang
  • Publication number: 20100248449
    Abstract: Disclosed herein are various embodiments related to metal-assisted chemical etching of substrates on the micron, sub-micron and nano scales. In one embodiment, among others, a method for metal-assisted chemical etching includes providing a substrate; depositing a non-spherical metal catalyst on a surface of the substrate; etching the substrate by exposing the non-spherical metal catalyst and the substrate to an etchant solution including a composition of a fluoride etchant and an oxidizing agent; and removing the etched substrate from the etchant solution.
    Type: Application
    Filed: March 31, 2010
    Publication date: September 30, 2010
    Applicant: GEORGIA TECH RESEARCH CORPORATION
    Inventors: Owen Hildreth, C. P. Wong, Yonghao Xiu
  • Publication number: 20100248487
    Abstract: Described herein are exemplary methods and apparatuses for etching a nitride layer disposed above a substrate to form trenches without micro-trenching in accordance with one embodiment. The method includes forming openings in a resist layer and one or more dielectric layers. The dielectric layers may be disposed on a hard mask layer (e.g., nitride, polysilicon). Next, the method includes etching openings in the hard mask layer disposed above a substrate layer without micro-trenching. The etching occurs in a process chamber during a main etch with a first process gas mixture having a fluorocarbon gas, a hydrofluorocarbon gas, and an oxygenating gas. Next, the method includes etching openings partially into the substrate without micro-trenching with a second process gas mixture during an over etch having the fluorocarbon gas, the hydrofluorocarbon gas, and the oxygenating gas.
    Type: Application
    Filed: March 3, 2010
    Publication date: September 30, 2010
    Inventors: Gene H. Lee, Wallace Wang, Bei Hao
  • Publication number: 20100248492
    Abstract: A method of forming fine patterns of a semiconductor device by using carbon (C)-containing films includes forming an etching target film on a substrate including first and second regions; forming a plurality of first C-containing film patterns on the etching target film in the first region; forming a buffer layer which covers top and side surfaces of the plurality of first C-containing film patterns; forming a second C-containing film; removing the second C-containing film in the second region; exposing the plurality of first C-containing film patterns by removing a portion of the buffer layer in the first and second regions; and etching the etching target film by using the plurality of first C-containing film patterns, and portions of the second C-containing film which remain in the first region, as an etching mask.
    Type: Application
    Filed: December 29, 2009
    Publication date: September 30, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-ki Yoon, Shi-yong Yi, Seong-woon Choi, Seok-hwan Oh, Kwang-sub Yoon, Myeong-cheol Kim, Young-ju Park
  • Publication number: 20100248495
    Abstract: A silicon etching liquid characterized by anisotropically dissolving monocrystalline silicon therein by using an aqueous solution containing a quaternary ammonium hydroxide and an aminoguanidine salt and an etching method of silicon using the instant etching liquid are an etching liquid and an etching method enabling one to perform processing at a high etching rate in etching processing of silicon, particularly in etching processing of silicon in a manufacturing process of MEMS parts or semiconductor devices.
    Type: Application
    Filed: September 22, 2008
    Publication date: September 30, 2010
    Applicant: MITSUBISHI GAS CHEMINCAL COMPANY, INC.
    Inventors: Kazuyoshi Yaguchi, Ryuji Sotoaka
  • Patent number: 7803710
    Abstract: A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming a line-type photoresist pattern on the silicon oxynitride layer such that the photoresist pattern in the cell region has a width larger than that of a final pattern structure and the photoresist pattern in the peripheral region has a width that reduces an incidence of pattern collapse; etching the silicon oxynitride layer and the silicon nitride layer until widths of a remaining silicon oxynitride layer and a remaining silicon nitride layer are smaller than the width of the photoresist pattern used as an etch mask through suppressing generation of polymers; and over-etching the remaining silicon nitride layer.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: September 28, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyung-Won Lee, Ki-Won Nam
  • Publication number: 20100239818
    Abstract: A method of texturizing a silicon substrate comprising a) contacting the substrate with an etching solution comprising glycolic acid, b) etching a surface of the substrate thereby forming disruptions in said surface of the substrate, and c) removing the etching solution to yield a texturized substrate, said texturized substrate having a plurality of disruptions in at least one surface with a surface density of disruptions of a minimum of 60 disruptions in a 400 micron square area.
    Type: Application
    Filed: March 18, 2009
    Publication date: September 23, 2010
    Inventors: Seung Jin Lee, Hee Soo Yeo
  • Publication number: 20100233539
    Abstract: A method is described of selectively etching a silicon substrate in small local areas in order to form columns or pillars in the etched surface. The silicon substrate is held in an etching solution of hydrogen fluoride, a silver salt and an alcohol. The inclusion of the alcohol provides a greater packing density of the silicon columns.
    Type: Application
    Filed: January 23, 2007
    Publication date: September 16, 2010
    Inventors: Mino Green, Feng-Ming Liu
  • Publication number: 20100233884
    Abstract: A process apparatus and a method for making semiconductor devices is implemented in a semiconductor equipment and utilizes three magnetic objects arranged in a helical path. Chemicals within the chemical pipe are magnetized, and the chemicals include etch acids, photoresist stripper and clean chemicals. Then, efficiency of semiconductor process is increased.
    Type: Application
    Filed: September 25, 2009
    Publication date: September 16, 2010
    Inventor: JEN-SHENG LUNG
  • Publication number: 20100227478
    Abstract: Provided are a substrate processing apparatus and a method of manufacturing a semiconductor device which can prevent a sealing member from being deteriorated due to a thermal radiation from a heater. The substrate processing apparatus includes a processing container, a substrate stage installed in the processing container, on which a substrate is placed, a heater installed in the substrate stage and configured to heat the substrate, a thermal radiation attenuator adjacent to the processing container, and a gas supply pipe connected to a gas inlet part with a sealing member interposed therebetween and configured to supply a processing gas to an inside of the processing container, wherein the thermal radiation attenuator is installed on a line connecting the heater and the sealing member.
    Type: Application
    Filed: March 3, 2010
    Publication date: September 9, 2010
    Applicant: HITACHI-KOKUSAI ELECTRIC INC.
    Inventor: Koichiro HARADA
  • Publication number: 20100224897
    Abstract: A semiconductor optoelectronic device with enhanced light extraction efficiency includes at least one protrusion structure, which can be formed around a light-emitting region of the device. The at least one protrusion structure can include a plurality of protrusion structures in one embodiment. In addition, a fabricating method for forming a semiconductor optoelectronic device with enhanced light extraction efficiency is provided in the present invention.
    Type: Application
    Filed: March 2, 2010
    Publication date: September 9, 2010
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY INC.
    Inventors: SHIH CHENG HUANG, CHIH PANG MA, PO MIN TU, YING CHAO YEH, WEN YU LIN, PENG YI WU, SHIH HSIUNG CHAN
  • Patent number: 7790493
    Abstract: Disclosed herein is a method of fabricating a device having a microstructure. The method includes forming a connector on a semiconductor substrate, coating the connector with a polymer layer, and immersing the semiconductor substrate and the coated connector in an etchant solution to form the microstructure from the semiconductor substrate and to release the coated connector and the microstructure from the semiconductor substrate such that the microstructure remains coupled to a further element of the device via the coated connector. In some cases, the microstructure is defined by forming an etch stop in the semiconductor substrate, and the microstructure and the semiconductor substrate are coated with a polymer layer, which may then be selectively patterned. The microstructure may then be released from the semiconductor substrate in accordance with the etch stop.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: September 7, 2010
    Assignee: The Regents of the University of Michigan
    Inventors: Kensall D. Wise, Mayurachat Ning Gulari, Ying Yao
  • Publication number: 20100221916
    Abstract: The invention includes methods in which one or more components of a carboxylic acid having an aqueous acidic dissociation constant of at least 1×10?6 are utilized during the etch of oxide (such as silicon dioxide or doped silicon dioxide). Two or more carboxylic acids can be utilized. Exemplary carboxylic acids include trichloroacetic acid, maleic acid, and citric acid.
    Type: Application
    Filed: May 11, 2010
    Publication date: September 2, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Niraj B. Rana, Kevin R. Shea, Janos Fucsko
  • Publication number: 20100203727
    Abstract: Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern.
    Type: Application
    Filed: February 17, 2010
    Publication date: August 12, 2010
    Applicant: Micron Technology, Inc.
    Inventors: Mirzafer K. Abatchev, Gurtej Sandhu, Luan Tran, William T. Rericha, D. Mark Durcan
  • Publication number: 20100203739
    Abstract: A method for selective etching of an SiGe mixed semiconductor layer on a silicon semiconductor substrate by dry chemical etching of the SiGe mixed semiconductor layer with the aid of an etching gas selected from the group including ClF3 and/or ClF5, a gas selected from the group including Cl2 and/or HCl being added to the etching gas.
    Type: Application
    Filed: July 2, 2008
    Publication date: August 12, 2010
    Inventors: Volker Becker, Franz Laermer, Tino Fuchs, Christina Leinenbach
  • Publication number: 20100203730
    Abstract: A process for selectively freeing an epitaxial layer from a single crystal substrate upon which it was grown, by providing a first substrate; depositing a separation layer on said first substrate; depositing on said separation layer a sequence of layers of semiconductor material forming a solar cell; mounting and bonding a surrogate substrate on top of the sequence of layers; attaching a connecting link element to at least two opposed points on the periphery of the surrogate substrate; and etching said separation layer while applying tension to said link element so as to remove said epitaxial layer from said first substrate.
    Type: Application
    Filed: February 9, 2009
    Publication date: August 12, 2010
    Applicant: Emcore Solar Power, Inc.
    Inventors: Arthur Cornfeld, Daniel McGlynn, Tansen Varghese
  • Publication number: 20100203722
    Abstract: A method for processing a semiconductor structure includes the steps of capping a top surface of the semiconductor structure that defines the metallization layer with a thin stop layer, forming a dielectric layer over the thin stop layer, wherein the dielectric layer defines at least one area where the thin stop layer is exposed, and removing the exposed thin stop layer to expose a top surface of the metallization layer using etchant gases substantially free from oxygen, so that the metallization layer is substantially free of damage.
    Type: Application
    Filed: April 22, 2010
    Publication date: August 12, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tien-I BAO, Syun-Ming JANG
  • Publication number: 20100197144
    Abstract: Methods for performing damage etch and texturing of single crystal silicon substrates, particularly for use as solar cells or photovoltaic cells. Damage etch with a TMAH solution followed by texturing using solution of KOH or NaOH mixed with IPA is particularly advantageous. The substitution of some of the IPA with ethylene glycol further improves results. Also disclosed is a process that combines both damage etch and texturing etch into a single step.
    Type: Application
    Filed: February 5, 2009
    Publication date: August 5, 2010
    Inventors: Curtis Dove, Cindy Dutton, Greg Bauer, Christopher Myers, Mehdi Balooch
  • Publication number: 20100197142
    Abstract: A method and apparatus for selective etching a substrate using a focused beam. For example, multiple gases may be used that are involved in competing beam-induced and spontaneous reactions, with the result depending on the materials on the substrate. The gases may include, for example, an etchant gas and an auxiliary gas that inhibits etching.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 5, 2010
    Applicant: FEI COMPANY
    Inventors: STEVEN RANDOLPH, CLIVE D. CHANDLER
  • Patent number: 7768018
    Abstract: The preferred embodiment provides for development and use of an array of nanowires with a period smaller then 150 nm for applications such as an optical polarizer. To manufacture such structures the preferred embodiment employs a hard nanomask. This nanomask includes a substantially periodic array of substantially parallel elongated elements having a wavelike cross-section.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: August 3, 2010
    Assignee: Wostec, Inc.
    Inventors: Valery K. Smirnov, Dmitry S. Kibalov
  • Patent number: 7767585
    Abstract: A method of cleaning for removing metal compounds attached to a surface of a substrate, wherein the cleaning is conducted by supplying a supercritical fluid of carbon dioxide comprising at least one of triallylamine and tris(3-aminopropyl)amine to the surface of the substrate and a process for producing a semiconductor device using the method of cleaning are provided. In accordance with the method of cleaning and the method for producing a semiconductor device using the method, etching residues or polishing residues containing metal compounds are efficiently removed selectively from the electroconductive material forming the electroconductive layer. When the electroconductive layer is a wiring, an increase in resistance due to residual metal compounds can be suppressed, and an increase in the leak current due to diffusion of the metal from the metal compounds to the insulating film can be prevented. Therefore, reliability on the wiring is improved, and the yield of the semiconductor device can be increased.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: August 3, 2010
    Assignees: Sony Corporation, Mitsubishi Gas Chemical Company, Inc.
    Inventors: Koichiro Saga, Kenji Yamada, Tomoyuki Azuma, Yuji Murata
  • Publication number: 20100190345
    Abstract: A semiconductor device having fins and a method of manufacture are provided. A patterned mask is formed over a substrate. Trenches are formed in the substrate and the trenches are filled with a dielectric material. Thereafter, the patterned mask is removed and one or more etch processes are performed to recess the dielectric material, wherein at least one of the etch processes is an etch process that removes or prevents fences from being formed along sidewalls of the trench. The etch process may be, for example, a plasma etch process using NH3 and NF3, an etch process using a polymer-rich gas, or an H2 etch process.
    Type: Application
    Filed: November 12, 2009
    Publication date: July 29, 2010
    Inventors: Neng-Kuo Chen, Kuo-Hwa Tzeng, Cheng-Yuan Tsai
  • Publication number: 20100190347
    Abstract: Embodiments of the present invention describe a removal chemistry for removing hard mask. The removal chemistry is a wet-etch solution that removes a metal hard mask formed on a dielectric layer, and is highly selective to a metal conductor layer underneath the dielectric layer. The removal chemistry comprises an aqueous solution of hydrogen peroxide (H2O2), a hydroxide source, and a corrosion inhibitor. The hydrogen peroxide and hydroxide source have the capability to remove the hard mask while the corrosion inhibitor prevents the metal conductor layer from chemically reacting with the hydrogen peroxide and hydroxide source during the hard mask removal.
    Type: Application
    Filed: January 23, 2009
    Publication date: July 29, 2010
    Inventors: Vijayakumar SubramanyaRao RamachandraRao, Kanwal Jit Singh
  • Publication number: 20100190351
    Abstract: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a dielectric layer overlying another dielectric layer, contacting the substrate at a first temperature with an acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with an acid solution exhibiting a positive etch selectivity at the second temperature. The dielectric layers exhibit different etch rates when etched at the first and second temperatures. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175° C. and the second temperature may be about 155° C.
    Type: Application
    Filed: April 6, 2010
    Publication date: July 29, 2010
    Applicant: Micron Technology, Inc.
    Inventors: Li Li, Don L. Yates
  • Publication number: 20100190340
    Abstract: In a method of forming fine patterns, a photocurable coating layer is formed on a substrate. A first surface of a template makes contact with the photocurable coating layer. The first surface of the template includes at least two first patterns having a first dispersion degree of sizes, and at least one portion of the first surface of the template includes a photo attenuation member. A light is irradiated onto the photocurable coating layer through the template to form a cured coating layer including second patterns having a second dispersion degree of sizes. The second patterns are generated from the first patterns and the second dispersion degree is less than the first dispersion degree. The template is separate from the cured coating layer. A size dispersion degree of the patterns used in a nanoimprint lithography process may be adjusted by the light attenuation member, so that the fine patterns may be formed to have an improved size dispersion degree.
    Type: Application
    Filed: January 27, 2010
    Publication date: July 29, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Hoon Lee, Jeong-Ho Yeo, Joo-On Park, In-Sung Kim, Doo-Hoon Goo, Jin-Hong Park, Chang-Min Park
  • Publication number: 20100184301
    Abstract: Methods for processing a microelectronic topography include selectively etching a layer of the topography using an etch solution which includes a fluid in a supercritical or liquid state. In some embodiments, the etch process may include introducing a fresh composition of the etch solution into a process chamber while simultaneously venting the chamber to inhibit the precipitation of etch byproducts. A rinse solution including the fluid in a supercritical or liquid state may be introduced into the chamber subsequent to the etch process. In some cases, the rinse solution may include one or more polar cosolvents, such as acids, polar alcohols, and/or water mixed with the fluid to help inhibit etch byproduct precipitation. In addition or alternatively, at least one of the etch solution and rinse solution may include a chemistry which is configured to modify dissolved etch byproducts within an ambient of the topography to inhibit etch byproduct precipitation.
    Type: Application
    Filed: January 20, 2009
    Publication date: July 22, 2010
    Applicant: LAM RESEARCH
    Inventors: Mark I. Wagner, James P. DeYoung
  • Publication number: 20100178772
    Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F—] concentration greater than 0.01 M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than ?1.4 volts.
    Type: Application
    Filed: January 15, 2009
    Publication date: July 15, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Simon Su-Horng Lin, Yu-Ming Lee, Shao-Yen Ku, Chi-Ming Yang, Chyi-Shyuan Chern, Chin-Hsiang Lin
  • Publication number: 20100178767
    Abstract: The present invention relates to compositions for chemical-mechanical polishing comprising A 0.01% to 40% by weight based on the total amount of the composition of abrasive particles of at least one porous metal-organic framework material, wherein the framework material comprises at least one at least bidentate organic compound which is coordinately bound to at least one metal ion; B 40% to 99.8% by weight based on the total amount of the composition of a liquid carrier; and C 0.01% to 20% by weight based on the total amount of the composition of a polishing additive component. The invention further relates to the use of said composition as well as methods for chemical-mechanical polishing of a surface with the aid of said compositions.
    Type: Application
    Filed: May 21, 2008
    Publication date: July 15, 2010
    Applicant: BASF SE
    Inventors: Markus Schubert, Sven Thate
  • Publication number: 20100173494
    Abstract: We suggest a method of anisotropic etching of the substrates, where ultra-thin and conformable layers of materials are used to passivate sidewalls of the etched features. According to an exemplary embodiment such sidewall passivation layer is a Self-assembled monolayer (SAM) material deposited in-situ etching process from a vapor phase. According to another exemplary embodiment such sidewall passivation layer is an inorganic-based material deposited using Atomic Layer Deposition (ALD) method. SAM or ALD layers deposition can be carried out in a pulsing regime alternating with an sputtering and/or etching processes using process gasses with or without plasma. Alternatively, SAM deposition process is carried out continuously, while etch or sputtering process turns on in a pulsing regime. Alternatively, SAM deposition process and etch or sputtering processes are carried out continuously.
    Type: Application
    Filed: October 1, 2009
    Publication date: July 8, 2010
    Applicant: ROLITH, INC
    Inventor: Boris Kobrin
  • Publication number: 20100173498
    Abstract: Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.
    Type: Application
    Filed: February 2, 2010
    Publication date: July 8, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mirzafer K. Abatchev, Krupaker Murali Subramanian, Baosuo Zhou
  • Patent number: 7749868
    Abstract: A semiconductor substrate shaped to have a curved surface profile by anodization. Prior to being anodized, the substrate is finished with an anode pattern on its bottom surface so as to be consolidated into a unitary structure in which the anode pattern is precisely reproduced on the substrate. The anodization utilizes an electrolytic solution which etches out an oxidized portion as soon as it is formed as a result of the anodization, to thereby develop a porous layer in a pattern in match with the anode pattern. The anode pattern brings about an in-plane distribution of varying electric field intensity by which the porous layer develops into a shape complementary to a desired surface profile. Upon completion of the anodization, the curves surface is revealed on the surface of the substrate by etching out the porous layer and the anode pattern from the substrate.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: July 6, 2010
    Assignee: Panasonic Electric Works Co., Ltd.
    Inventors: Yoshiaki Honda, Takayuki Nishikawa
  • Publication number: 20100164027
    Abstract: A method for producing a component having at least one diaphragm formed in the upper surface of the component, which diaphragm spans a cavity, and having at least one access opening to the cavity from the back side of the component, at least one first diaphragm layer and the cavity being produced in a monolithic semiconductor substrate from the upper surface of the component, and the access opening being produced in a temporally limited etching step from the back side of the substrate. The access opening is placed in a region in which the substrate material comes up to the first diaphragm layer.
    Type: Application
    Filed: November 28, 2007
    Publication date: July 1, 2010
    Inventors: Torsten Kramer, Kathrin Knese, Hubert Benzel, Gregor Schuermann, Simon Armbruster, Christoph Schelling
  • Publication number: 20100159701
    Abstract: A method for manufacturing a semiconductor device comprises performing an exposing and developing process using an exposure mask including shading patterns and assistant patterns arranged in parallel to the shading patterns to prevent a scum phenomenon generated when a main pattern is formed in a cell region over a semiconductor substrate, thereby improving characteristics, reliability and yield of the semiconductor device. As a result, the method enables high-integration of the semiconductor device.
    Type: Application
    Filed: June 30, 2009
    Publication date: June 24, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventors: Joo Kyoung SONG, Hyoung Soon Yune
  • Publication number: 20100159709
    Abstract: A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
    Type: Application
    Filed: March 4, 2010
    Publication date: June 24, 2010
    Inventors: Toshiya KOTANI, Satoshi Tanaka, Shigeki Nojima, Koji Hashimoto, Soichi Inoue
  • Publication number: 20100159697
    Abstract: A method of manufacturing a semiconductor device may include forming a first oxide film, a nitride film and/or a second oxide film over a substrate, and may include forming a trench over a semiconductor substrate by etching a portion of a first oxide film, a nitride film, a second oxide film and/or a semiconductor substrate. A method of manufacturing a semiconductor device may include performing wet etching to form a divot, which may be performed over a semiconductor substrate having a trench, and/or which may expose a portion of a nitride film. A method of manufacturing a semiconductor device may include removing a second oxide film having a portion thereof etched and a portion of a first oxide film exposed by a divot, while rounding upper edge portions of a trench using a mixed solution of deionized water and HF. A semiconductor device formed by a method is disclosed.
    Type: Application
    Filed: December 8, 2009
    Publication date: June 24, 2010
    Inventor: Chung-Kyung Jung
  • Publication number: 20100151597
    Abstract: Disclosed is a method for smoothing the surface of at least one side of a wafer which is obtained by slicing a semiconductor ingot. In this method, a fluid is applied according to projections of the wafer surface, thereby reducing the projections. Alternatively, a fluid is applied over the wafer surface, thereby smoothing the entire surface of the wafer while reducing the projections in the wafer surface.
    Type: Application
    Filed: January 17, 2007
    Publication date: June 17, 2010
    Applicant: SUMCO CORPORATION
    Inventors: Takeo Katoh, Tomohiro Hashii, Katsuhiko Murayama, Sakae Koyata, Kazushige Takaishi
  • Publication number: 20100151685
    Abstract: A method of removing a multi-layered structure includes the following processes. A semiconductor substrate is prepared. The semiconductor substrate has a multi-layered structure including a first film over the semiconductor substrate, a second film on the first film, and a mask pattern film on the second film. Then, the mask pattern film is removed. Then, the second film is removed by etching the second film with a first etching selectivity of the second film to the first film. The first etching selectivity is greater than a second etching selectivity of the second film to the first film with which the second film is patterned by etching using the mask pattern film. Then, the third film is removed.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 17, 2010
    Applicant: Elpida Memory, Inc.
    Inventor: Taizo YASUDA
  • Publication number: 20100151689
    Abstract: Embodiments of the invention generally relate to apparatuses and methods for producing epitaxial thin films and devices by epitaxial lift off (ELO) processes. In one embodiment, a method for forming thin film devices during an ELO process is provided which includes coupling a plurality of substrates to an elongated support tape, wherein each substrate contains an epitaxial film disposed over a sacrificial layer disposed over a wafer, exposing the substrates to an etchant during an etching process while moving the elongated support tape, and etching the sacrificial layers and peeling the epitaxial films from the wafers while moving the elongated support tape. Embodiments also include several apparatuses, continuous-type as well as a batch-type apparatuses, for forming the epitaxial thin films and devices, including an apparatus for removing the support tape and epitaxial films from the wafers on which the epitaxial films were grown.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 17, 2010
    Applicant: ALTA DEVICES, INC.
    Inventors: Thomas Gmitter, Gang He, Melissa Archer, Andreas Hegedus
  • Publication number: 20100144156
    Abstract: A method to integrate a micro electro mechanical system and a CMOS image sensor is disclosed. First a substrate is provided. The substrate includes a micro electro mechanical system (MEMS) region and a CMOS image sensor (CIS) region. The micro electro mechanical system region includes a micro electro mechanical system component and the CMOS image sensor region includes a CMOS image sensor element. Second, an etching procedure is performed on the substrate to form a micro electro mechanical system trench and a CMOS image sensor trench. The etching procedure includes at least a dry etching and at least a wet etching.
    Type: Application
    Filed: December 9, 2008
    Publication date: June 10, 2010
    Inventor: Hui-Shen Shih
  • Publication number: 20100144147
    Abstract: A sample holding tool is provided with a base plate, a plurality of convex portions formed on the base plate so as to stick out from the upper face thereof; and at least one holding plate having a plurality of curved face portions corresponding to the convex portions, with a lower face concave portion of each of the curved face portions being made in contact with the tip portion of each of the convex portions, so that a sample is supported on the upper face convex portion of each of the curved face portions; thus, since the sample is supported by the curved face portion of the holding plate, the contact area to the sample is made very small so that it becomes possible to greatly reduce pointed peak portions, scratches and the like at contact portions between the sample and the curved face portions. Consequently, generation of particles due to abrasion of the sample can be reduced and the particles are reduced from intruding into scratches and voids and occasionally readhering to the sample.
    Type: Application
    Filed: July 28, 2006
    Publication date: June 10, 2010
    Applicants: KYOCERA CORPORATION, OKUTEC CO., LTD
    Inventors: Takeshi Muneishi, Katsuya Okumura
  • Patent number: 7732344
    Abstract: A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; forming a hard mask layer over the substrate; forming protected portions and unprotected portions of the hard mask layer; performing a first etching process, a second etching process, and a third etching process on the unprotected portions of the hard mask layer, wherein the first etching process partially removes the unprotected portions of the hard mask layer, the second etching process treats the unprotected portions of the hard mask layer, and the third etching process removes the remaining unprotected portions of the hard mask layer; and performing a fourth etching process to remove the protected portions of the hard mask layer.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: June 8, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang Wen Tsai, Matt Yeh, Ming-Jun Wang, Shun Wu Lin, Chi-Chun Chen, Zin-Chang Wei, Chyi-Shyuan Chern
  • Publication number: 20100136794
    Abstract: A method for cleaning structured surfaces of semiconductor components to remove photoresist and etching residues after the etching of the surface, comprising: a) treatment of the surface with an acidic aqueous solution comprising one or more acids and one or more oxidizing agents, b) removal of the photoresist and c) washing with demineralized water in the stated sequence.
    Type: Application
    Filed: May 9, 2008
    Publication date: June 3, 2010
    Applicant: BASF SE
    Inventors: Berthold Ferstl, Andreas Kuehner
  • Publication number: 20100136716
    Abstract: A manufacturing apparatus for a semiconductor device, treating a SiN film formed on a wafer with phosphoric acid solution, including a processing bath to store phosphoric acid solution provided for treatment of the wafer, a control unit for calculating integrated SiN etching amount of the phosphoric acid solution, determining necessity of quality adjustment of the phosphoric acid solution, based on correlation between the integrated SiN etching amount calculated and etching selectivity to oxide film, and calculating a quality adjustment amount of the phosphoric acid solution as needed, and also including a mechanism to adjust the quality of the phosphoric acid solution based on the quality adjustment amount calculated.
    Type: Application
    Filed: November 10, 2009
    Publication date: June 3, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hisashi Okuchi
  • Patent number: 7727900
    Abstract: A cleaning sequence usable in semiconductor manufacturing efficiently cleans semiconductor substrates while preventing chemical oxide formation thereon. The sequence includes the sequence of: 1) treating with an HF solution; 2) treating with pure H2SO4; 3) treating with an H2O2 solution; 4) a DI water rinse; and 5) treatment with an HCl solution. The pure H2SO4 solution may include an H2SO4 concentration of about ninety-eight percent (98%) or greater. After the HCl solution treatment, the cleaned surface may be a silicon surface that is free of a chemical oxide having a thickness of 5 angstroms or greater. The invention finds particular advantage in semiconductor devices that utilize multiple gate oxide thicknesses.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: June 1, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Matt Yeh, Shun Wu Lin, Chi-Chun Chen, Shih-Chang Chen
  • Publication number: 20100130021
    Abstract: A method is disclosed for processing the cleaved surface of a silicon-on-insulator structure. The silicon-on-insulator structures comprises a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The methods disclosed include an etching process to reduce the time and cost required to process the silicon-on-insulator structure to remove the surface damage and defects formed when a portion of the donor wafer is separated along a cleave plane from the silicon-on-insulator structure. The method includes, annealing the structure, etching the cleaved surface, and performing a non-contact smoothing process on the cleaved surface.
    Type: Application
    Filed: November 23, 2009
    Publication date: May 27, 2010
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Michael J. Ries, Robert W. Standley, Jeffrey L. Libbert, Andrew M. Jones, Gregory M. Wilson
  • Publication number: 20100129958
    Abstract: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to methods and apparatus for trench and via profile modification prior to filling the trench and via. One embodiment of the present invention comprises forming a sacrifice layer to pinch off a top opening of a trench structure by exposing the trench structure to an etchant. In one embodiment, the etchant is configured to remove the first material by reacting with the first material and generating a by-product, which forms the sacrifice layer.
    Type: Application
    Filed: November 18, 2009
    Publication date: May 27, 2010
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Mei Chang, Chien-Teh Kao, Xinliang Lu, Zhenbin Ge
  • Publication number: 20100124824
    Abstract: An etch apparatus, especially for silicon nitride etch includes a control unit coupled to at least one component of the group of components comprising heater current sensors, a pump transducer sensor and a flow sensor provided for a diluting liquid. A malfunction of the apparatus is avoided and the etching process can be controlled for better performance.
    Type: Application
    Filed: November 19, 2008
    Publication date: May 20, 2010
    Applicant: austriamicrosystems AG
    Inventors: Gerhard EILMSTEINER, Johann NINAUS
  • Publication number: 20100116316
    Abstract: The present disclosure presents a partially-transparent (see-through) three-dimensional thin film solar cell (3-D TFSC) substrate. The substrate includes a plurality of unit cells. Each unit cell structure has the shape of a truncated pyramid, and its parameters may be varied to allow a desired portion of sunlight to pass through.
    Type: Application
    Filed: November 27, 2009
    Publication date: May 13, 2010
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, David Xuan-Qi Wang
  • Publication number: 20100120177
    Abstract: A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.
    Type: Application
    Filed: January 21, 2010
    Publication date: May 13, 2010
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Haoren Zhuang, Alois Gutmann, Matthias Lipinski, Chandrasekhar Sarma, Jingyu Lian
  • Publication number: 20100117951
    Abstract: An electrophoretic display device includes: a transparent substrate positioned at a display side and having a transparent front electrode; a wiring substrate disposed to face the transparent substrate and having a field applying unit; a spacer disposed between the transparent substrate and the wiring substrate and having a plurality of accommodating holes with upper and lower portions open; and a plurality of microcapsules respectively positioned in the plurality of accommodating holes and including a dispersion solvent encapsulated with a plurality of charged particles contained therein, wherein the accommodating holes comprise upper holes with a width for receiving the microcapsules and lower holes allowing the microcapsules to be mounted thereon.
    Type: Application
    Filed: June 5, 2009
    Publication date: May 13, 2010
    Inventors: Sang Jin KIM, Yongsoo Oh, Hwan-Soo Lee, Jeong Bok Kwak, Sang Moon Lee