Deposition Of Silicon Oxide (epo) Patents (Class 257/E21.278)
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Publication number: 20110281417Abstract: This invention relates to materials and processes for thin film deposition on solid substrates. Silica/alumina nanolaminates were deposited on heated substrates by the reaction of an aluminum-containing compound with a silanol. The nanolaminates have very uniform thickness and excellent step coverage in holes with aspect ratios over 40:1. The films are transparent and good electrical insulators. This invention also relates to materials and processes for producing improved porous dielectric materials used in the insulation of electrical conductors in microelectronic devices, particularly through materials and processes for producing semi-porous dielectric materials wherein surface porosity is significantly reduced or removed while internal porosity is preserved to maintain a desired low-k value for the overall dielectric material.Type: ApplicationFiled: July 22, 2011Publication date: November 17, 2011Inventors: Roy G. GORDON, Jill Becker, Dennis Hausmann
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Patent number: 8021991Abstract: Oxide films are deposited under conditions generating a silicon-rich oxide in which silicon nanoclusters form either during deposition or during subsequent annealing. Such deposition conditions include those producing films with optical indices (n) greater than 1.46. The method of the present invention reduces the TID radiation-induced shifts for the oxides.Type: GrantFiled: February 28, 2006Date of Patent: September 20, 2011Assignee: The United States of America as represented by the Secretary of the NavyInventors: Harold L Hughes, Bernard J Mrstik, Reed K Lawrence, Patrick J McMarr
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Patent number: 8021936Abstract: A thin film transistor (TFT) and a method of manufacturing the same are provided. The TFT includes a transparent substrate, an insulating layer on a region of the transparent substrate, a monocrystalline silicon layer, which includes source, drain, and channel regions, on the insulating layer and a gate insulating film and a gate electrode on the channel region of the monocrystalline silicon layer.Type: GrantFiled: March 26, 2009Date of Patent: September 20, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Takashi Noguchi, Wenxu Xianyu, Hans S. Cho, Huaxiang Yin
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Publication number: 20110223774Abstract: Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.Type: ApplicationFiled: August 13, 2010Publication date: September 15, 2011Applicant: Applied Materials, Inc.Inventors: Sasha Kweskin, Paul Edward Gee, Shankar Venkataraman, Kedar Sapre
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Publication number: 20110215445Abstract: Described herein are methods of forming dielectric films comprising silicon, oxide, and optionally nitrogen, carbon, hydrogen, and boron. Also disclosed herein are the methods to form dielectric films or coatings on an object to be processed, such as, for example, a semiconductor wafer.Type: ApplicationFiled: January 28, 2011Publication date: September 8, 2011Applicant: AIR PRODUCTS AND CHEMICALS, INC.Inventors: Liu Yang, Manchao Xiao, Bing Han, Kirk S. Cuthill, Mark L. O'Neill
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Patent number: 8008188Abstract: A method is provided comprising: coating an electrically conductive core with a first removable material, creating openings in the first removable material to expose portions of the electrically conductive core, plating a conductive material onto the exposed portions of the electrically conductive core, coating the conductive material with a second removable material, removing the first removable material, electrophoretically coating the electrically conductive core with a dielectric coating, and removing the second removable material.Type: GrantFiled: June 11, 2007Date of Patent: August 30, 2011Assignee: PPG Industries Ohio, Inc.Inventors: Kevin C. Olson, Alan E. Wang
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Patent number: 8008694Abstract: A light source with enhanced brightness includes an angle-selective optical filter and a light emitting diode (LED) having a high reflective layer. The angle-selective filter is located on the top surface of emitting diode to pass lights at specified angles. According to one embodiment, the angle-selective filter includes index-alternating layers. With a reflective polarizer, the light source can produce polarized light with enhanced brightness.Type: GrantFiled: September 22, 2007Date of Patent: August 30, 2011Assignee: YLX, Ltd.Inventors: Li Xu, Yi Li
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Patent number: 8003531Abstract: A method for manufacturing a flash memory device is capable of controlling a phenomenon in which a length of the channel between a source and a drain is decreased due to undercut. The method includes forming a gate electrode comprising a floating gate, an ONO film and a control gate using a hard mask pattern over a semiconductor substrate, forming a spacer over the sidewall of the gate electrode, forming an low temperature oxide (LTO) film over the entire surface of the semiconductor substrate including the gate electrode and the spacer, etching the LTO film such that a top portion of the source/drain region and a top portion of the gate electrode are exposed, and removing the LTO film present over the sidewall of the gate electrode by wet-etching.Type: GrantFiled: September 29, 2009Date of Patent: August 23, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Chung-Kyung Jung
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Patent number: 7994070Abstract: A method for depositing a dielectric film on a substrate includes positioning a plurality of substrates in a process chamber, heating the process chamber to a deposition temperature between 400° C. and less than 650° C., flowing a first process gas comprising water vapor into the process chamber, flowing a second process gas comprising dichlorosilane (DCS) into the process chamber, establishing a gas pressure of less than 2 Torr, and reacting the first and second process gases to thermally deposit a silicon oxide film on the plurality of substrates. One embodiment further includes flowing a third process gas comprising nitric oxide (NO) gas into the process chamber while flowing the first process gas and the second process gas; and reacting the oxide film with the third process gas to form a silicon oxynitride film on the substrate.Type: GrantFiled: September 30, 2010Date of Patent: August 9, 2011Assignee: Tokyo Electron LimitedInventors: Anthony Dip, Kimberly G Reid
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Patent number: 7989354Abstract: Disclosed is a patterning method including: forming a first film on a substrate; forming a first resist film on the first film; processing the first resist film into a first resist pattern having a preset pitch by photolithography; forming a silicon oxide film on the first resist pattern and the first film by alternately supplying a first gas containing organic silicon and a second gas containing an activated oxygen species to the substrate; forming a second resist film on the silicon oxide film; processing the second resist film into a second resist pattern having a preset pitch by the photolithography; and processing the first film by using the first resist pattern and the second resist pattern as a mask.Type: GrantFiled: June 6, 2008Date of Patent: August 2, 2011Assignee: Tokyo Electron LimitedInventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
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Patent number: 7989365Abstract: Methods of seasoning a remote plasma system are described. The methods include the steps of flowing a silicon-containing precursor into a remote plasma region to deposit a silicon containing film on an interior surface of the remote plasma system. The methods reduce reactions with the seasoned walls during deposition processes, resulting in improved deposition rate, improved deposition uniformity and reduced defectivity during subsequent deposition.Type: GrantFiled: August 18, 2009Date of Patent: August 2, 2011Assignee: Applied Materials, Inc.Inventors: Soonam Park, Soo Jeon, Toan Q. Tran, Jang-Gyoo Yang, Qiwei Liang, Dmitry Lubomirsky
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Patent number: 7985700Abstract: A method for fabricating a semiconductor device utilizing the step of forming a first insulating film of a porous material over a substrate; the step of forming on the first insulating film a second insulating film containing a silicon compound containing Si—CH3 bonds by 30-90%, and the step of irradiating UV radiation with the second insulating film formed on the first insulating film to cure the first insulating film. Thus, UV radiation having the wavelength which eliminates CH3 groups is sufficiently absorbed by the second insulating film, whereby the first insulating film is highly strengthened with priority by the UV cure, and the first insulating film can have the film density increased without having the dielectric constant increased.Type: GrantFiled: December 8, 2008Date of Patent: July 26, 2011Assignee: Fujitsu LimitedInventors: Shirou Ozaki, Yoshihiro Nakata, Ei Yano
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Patent number: 7985690Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.Type: GrantFiled: June 4, 2009Date of Patent: July 26, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Harry Chuang, Su-Chen Lai, Gary Shen
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Patent number: 7981799Abstract: The present invention relates to a room temperature-operating single-electron device and a fabrication method thereof, and more particularly, to a room temperature-operating single-electron device in which a plurality of metal silicide dots formed serially is used as multiple quantum dots, and a fabrication method thereof.Type: GrantFiled: September 11, 2008Date of Patent: July 19, 2011Assignee: Chungbuk National University Industry-Academic Cooperation FoundationInventors: Jung Bum Choi, Chang Keun Lee, Min Sik Kim
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Patent number: 7981815Abstract: Disclosed is a producing method or a semiconductor device including: loading at least one substrate into a processing chamber; forming a metal oxide film or a silicon oxide film on a surface of the substrate by repeatedly supplying a metal compound or a silicon compound, each of which is a first material, an oxide material which is a second material including an oxygen atom, and a hydride material which is a third material, into the processing chamber predetermined times; and unloading the substrate from the processing chamber.Type: GrantFiled: July 19, 2007Date of Patent: July 19, 2011Assignees: Hitachi Kokusai Electric Inc., Shin-Etsu Chemical Co., Ltd.Inventors: Hironobu Miya, Kazuhiro Hirahara, Yoshitaka Hamada, Atsuhiko Suda
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Patent number: 7981812Abstract: Methods for forming an ultra thin structure using a method that includes multiple cycles of polymer deposition of photoresist (PDP) process and etching process. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on a dielectric layer, performing a polymer deposition process to deposit a polymer layer on the pattered photoresist layer, thus reducing a critical dimension of an opening in the patterned photoresist layer, and etching the underlying hardmask layer through the opening having the reduced dimension.Type: GrantFiled: July 3, 2008Date of Patent: July 19, 2011Assignee: Applied Materials, Inc.Inventors: Kang-Lie Chiang, Chia-Ling Kao
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Patent number: 7972941Abstract: A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten.Type: GrantFiled: July 1, 2008Date of Patent: July 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Won Hong, Gil-Heyun Choi, Jong-Myeong Lee, Geum-Jung Seong
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Publication number: 20110151679Abstract: A silicon-containing insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas including di-iso-propylaminosilane gas and a second process gas including an oxidizing gas or nitriding gas. The film is formed by performing a plurality of times a cycle alternately including first and second steps. The first step performs supply of the first process gas, thereby forming an adsorption layer containing silicon on a surface of the target substrate. The second performs supply of the second process gas, thereby oxidizing or nitriding the adsorption layer on the surface of the target substrate. The second step includes an excitation period of supplying the second process gas to the process field while exciting the second process gas by an exciting mechanism.Type: ApplicationFiled: March 4, 2011Publication date: June 23, 2011Applicant: Tokyo Electron LimitedInventors: Kazuhide HASEBE, Shigeru Nakajima, Jun Ogawa
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Patent number: 7960281Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.Type: GrantFiled: November 26, 2008Date of Patent: June 14, 2011Assignee: Renesas Electronics CorporationInventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
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Patent number: 7955948Abstract: A manufacturing method of a semiconductor device includes the steps of carrying a substrate in a processing chamber, bringing the processing chamber into a state at a first pressure by supplying a silicon compound gas which contains carbon and hydrogen into the processing chamber, forming a silicon oxide film on the substrate by irradiating a UV light to the silicon compound gas supplied into the processing chamber in the state kept at the first pressure, and decompression process to bring the processing chamber into a state at a second pressure lower than the first pressure. This makes it possible to form the dense silicon oxide film in the trench with high aspect ratio and small width.Type: GrantFiled: September 1, 2009Date of Patent: June 7, 2011Assignee: Hitachi Kokusai Electric Inc.Inventors: Naofumi Ohashi, Yuichi Wada, Nobuo Owada, Takeshi Taniguchi
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Patent number: 7956393Abstract: A composition for a photoresist stripper and a method of fabricating a thin film transistor array substrate are provided according to one or more embodiments. In one or more embodiments, the composition includes about 5-30 weight % of a chain amine compound, about 0.5-10 weight % of a cyclic amine compound, about 10-80 weight % of a glycol ether compound, about 5-30 weight % of distilled water, and about 0.1-5 weight % of a corrosion inhibitor.Type: GrantFiled: September 21, 2009Date of Patent: June 7, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hyun Choung, Bong-Kyun Kim, Hong-Sick Park, Sun-Young Hong, Young-Joo Choi, Byeong-Jin Lee, Nam-Seok Suh, Byung-Uk Kim, Suk-Il Yoon, Jong-Hyun Jeong, Sung-Gun Shin, Soon-Beom Huh, Se-Hwan Jung, Doo-Young Jang, Sun-Joo Park, Oh-Hwan Kweon
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Patent number: 7951685Abstract: The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.Type: GrantFiled: September 14, 2007Date of Patent: May 31, 2011Assignee: Sumitomo Chemical Company, LimitedInventors: Hiroyuki Sazawa, Naohiro Nishikawa, Masahiko Hata
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Patent number: 7947607Abstract: A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.Type: GrantFiled: December 23, 2008Date of Patent: May 24, 2011Assignee: Macronix International Co., Ltd.Inventor: Chao-I Wu
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Patent number: 7943531Abstract: A method of depositing a silicon oxide layer over a substrate includes providing a substrate to a deposition chamber. A first silicon-containing precursor, a second silicon-containing precursor and a NH3 plasma are reacted to form a silicon oxide layer. The first silicon-containing precursor includes at least one of Si—H bond and Si—Si bond. The second silicon-containing precursor includes at least one Si—N bond. The deposited silicon oxide layer is annealed.Type: GrantFiled: October 22, 2007Date of Patent: May 17, 2011Assignee: Applied Materials, Inc.Inventors: Srinivas D. Nemani, Abhijit Basu Mallick, Ellie Y. Yieh
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Patent number: 7939436Abstract: A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.Type: GrantFiled: January 14, 2009Date of Patent: May 10, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Kim, Min-Sang Kim, Keun-Hwi Cho, Ji-Myoung Lee
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Patent number: 7939438Abstract: Methods of inhibiting background plating on semiconductor substrates using oxidizing agents are disclosed.Type: GrantFiled: March 19, 2009Date of Patent: May 10, 2011Assignee: Rohm and Haas Electronic Materials LLCInventors: Gary Hamm, David L. Jacques, Carl J. Colangelo
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Patent number: 7935555Abstract: A method of sealing a microelectromechanical system (MEMS) device from ambient conditions is described. The MEMS device is formed on a substrate and a substantially hermetic seal is formed as part of the MEMS device manufacturing process. The method may include forming a metal seal on the substrate proximate to a perimeter of the MEMS device using a method such as photolithography. The metal seal is formed on the substrate while the MEMS device retains a sacrificial layer between conductive members of MEMS elements, and the sacrificial layer is removed after formation of the seal and prior to attachment of a backplane.Type: GrantFiled: November 30, 2009Date of Patent: May 3, 2011Assignee: QUALCOMM MEMS Technologies, Inc.Inventor: Philip D Floyd
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Patent number: 7927957Abstract: A bonded silicon wafer is produced by a method including an oxygen ion implantation step on a silicon wafer for active layer having the specified wafer face; a step of bonding the silicon wafer for active layer to a silicon wafer for support; a first heat treatment step; an inner SiO2 layer exposing step; a step of removing the inner SiO2 layer; and a planarizing step of polishing a silicon wafer composite or subjecting the silicon wafer composite to a heat treatment in a reducing atmosphere (a second heat treatment step).Type: GrantFiled: September 11, 2009Date of Patent: April 19, 2011Assignee: SUMCO CorporationInventors: Tatsumi Kusaba, Akihiko Endo, Hideki Nishihata, Nobuyuki Morimoto
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Patent number: 7927988Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a first layer, a second layer, an ion implantation layer between the first and second layers, and an anti-oxidation layer on the second layer, and performing a heat treating process to form an insulating layer between the first and second layers while preventing loss of the second layer using the anti-oxidation layer.Type: GrantFiled: June 21, 2009Date of Patent: April 19, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: In-Gyoo Kim, O-Kyun Kwon, Dong-Woo Suh, Gyung-Ock Kim
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Patent number: 7923384Abstract: In a formation method of a porous insulating film by supplying at least organosiloxane and an inert gas to a reaction chamber and forming an insulating film by a plasma vapor deposition method, a partial pressure of the organosiloxane in the reaction chamber is changed by varying a volume ratio of the organosiloxane and the inert gas to be supplied during deposition. Thus, the dielectric constant of the insulating film in the semiconductor device is reduced while the adhesion of the insulating film with other materials is improved. It is desirable that the organosiloxane be cyclic organosiloxane including at least silicon, oxygen, carbon, and hydrogen, and that the total pressure of the reaction chamber be constant during deposition.Type: GrantFiled: November 24, 2006Date of Patent: April 12, 2011Assignee: NEC CorporationInventors: Munehiro Tada, Naoya Furutake, Tsuneo Takeuchi, Yoshihiro Hayashi
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Publication number: 20110081786Abstract: Methods for reducing and inhibiting defect formation on silicon dioxide formed by atomic layer deposition (ALD) are disclosed. Defect reduction is accomplished by performing processing on the silicon dioxide subsequent to deposition by ALD. The post-deposition processing may include at least one of a pump/purge cycle and a water exposure cycle performed after formation of the silicon dioxide on a substrate.Type: ApplicationFiled: December 10, 2010Publication date: April 7, 2011Applicant: MICRON TECHNOLOGY, INC.Inventor: Shyam Surthi
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Patent number: 7910970Abstract: In one aspect of the present invention, a programmable element, may include a semiconductor substrate, source/drain layers formed apart from each other in the upper surface of the semiconductor substrate, a gate insulating film including a charge-trapping film containing Hf and formed on a portion between the source/drain layers of the semiconductor substrate, and a gate electrode formed on the gate insulating film with a program voltage applied to the gate electrode.Type: GrantFiled: June 20, 2008Date of Patent: March 22, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Mariko Takayanagi
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Patent number: 7910419Abstract: A method for making a transistor with self-aligned gate and ground plane includes forming a stack, on one face of a semi-conductor substrate, the stack including an organometallic layer and a dielectric layer. The method also includes exposing a part of the organometallic layer, a portion of the organometallic layer different to the exposed part being protected from the electron beams by a mask, the shape and the dimensions of a section, in a plane parallel to the face of the substrate, of the gate of the transistor being substantially equal to the shape and to the dimensions of a section of the organometallic portion in said plane. The method also includes removing the exposed part, and forming dielectric portions in empty spaces formed by the removal of the exposed part of the organometallic layer, around the organometallic portion.Type: GrantFiled: June 11, 2009Date of Patent: March 22, 2011Assignee: Commissariat a l'Energie AtomiqueInventors: Claire Fenouillet-Beranger, Philippe Coronel
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Patent number: 7906830Abstract: Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer.Type: GrantFiled: December 17, 2008Date of Patent: March 15, 2011Assignee: Micron Technology, Inc.Inventors: David H. Wells, Du Li
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Patent number: 7902061Abstract: A method of making an interconnect structure: which includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric material; and depositing an encasing cap over the extended portion of the interconnect structure.Type: GrantFiled: August 27, 2008Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Timothy J. Dalton, Louis C. Hsu, Carl Radens, Theodorus E. Standaert, Keith Kwong Hon Wong, Chih-Chao Yang
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Patent number: 7897503Abstract: A device having the capability for electrical, thermal, optical, and fluidic interconnections to various layers. Through-substrate vias in the interconnect device are filled to enable electrical and thermal connection or optionally hermetically sealed relative to other surfaces to enable fluidic or optical connection. Optionally, optical components may be placed within the via region in order to manipulate optical signals. Redistribution of electrical interconnection is accomplished on both top and bottom surfaces of the substrate of the interconnect chip.Type: GrantFiled: May 12, 2006Date of Patent: March 1, 2011Assignee: The Board of Trustees of the University of ArkansasInventors: Ron B. Foster, Ajay P. Malshe, Matthew W. Kelley
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Patent number: 7897414Abstract: A method of manufacturing a semiconductor device has forming a ferroelectric film over a substrate, placing the substrate having the ferroelectric film in a chamber substantially held in vacuum, introducing oxygen and an inert gas into the chamber, annealing the ferroelectric film in the chamber, and containing oxygen and the inert gas while the chamber is maintained sealed.Type: GrantFiled: January 8, 2009Date of Patent: March 1, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Kouichi Nagai
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Publication number: 20110034039Abstract: A method of forming a silicon oxide layer is described. The method may include the steps of mixing a carbon-free silicon-and-nitrogen containing precursor with a radical precursor, and depositing a silicon-and-nitrogen containing layer on a substrate. The silicon-and-nitrogen containing layer is then converted to the silicon oxide layer.Type: ApplicationFiled: July 21, 2010Publication date: February 10, 2011Applicant: Applied Materials, Inc.Inventors: Jingmei Liang, Nitin K. Ingle, Shankar Venkataraman
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Patent number: 7875912Abstract: The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO2), hafnium oxide (HfO2) and tin oxide (SnO2) acting as a single dielectric layer with a formula of Zrx Hfy Sn1-x-y O2, and a method of fabricating such a dielectric layer is described that produces a reliable structure with a high dielectric constant (high k). The dielectric structure is formed by depositing zirconium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing hafnium oxide onto the substrate using precursor chemicals, followed by depositing tin oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric may be used as a gate insulator, a capacitor dielectric, or as a tunnel insulator in non-volatile memories, because the high dielectric constant (high k) provides the functionality of a much thinner silicon dioxide film.Type: GrantFiled: May 23, 2008Date of Patent: January 25, 2011Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Publication number: 20110008972Abstract: Methods of forming a silicon dioxide material by an atomic layer deposition process and methods of preparing a substrate for the formation of a silicon dioxide material by an atomic layer deposition process are provided. In at least one such method, prior to forming the silicon oxide material, at least one pump and exhaust cycle is conducted. Such a pump and exhaust cycle includes at least one pump step, whereby a purge gas is pumped into the reaction chamber, and at least one exhaust step, whereby the purge gas is exhausted from a reaction chamber. The silicon oxide material is then formed on a surface of the substrate.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Inventors: Daniel Damjanovic, Shyam Surthi
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Patent number: 7867918Abstract: A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dieletric thickness of less than approximately 20 angstroms.Type: GrantFiled: March 11, 2008Date of Patent: January 11, 2011Assignee: Cypress Semiconductor CorporationInventor: Krishnaswamy Ramkumar
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Patent number: 7867921Abstract: A processing chamber is seasoned by providing a flow of season precursors to the processing chamber. A high-density plasma is formed from the season precursors by applying at least 7500 W of source power distributed with greater than 70% of the source power at a top of the processing chamber. A season layer having a thickness of at least 5000 ? is deposited at one point using the high-density plasma. Each of multiple substrates is transferred sequentially into the processing chamber to perform a process that includes etching. The processing chamber is cleaned between sequential transfers of the substrates.Type: GrantFiled: September 4, 2008Date of Patent: January 11, 2011Assignee: Applied Materials, Inc.Inventors: Anchuan Wang, Young S. Lee, Manoj Vellaikal, Jason Thomas Bloking, Jin Ho Jeon, Hemant P. Mungekar
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Patent number: 7858535Abstract: Methods for reducing and inhibiting defect formation on silicon dioxide formed by atomic layer deposition (ALD) are disclosed. Defect reduction is accomplished by performing processing on the silicon dioxide subsequent to deposition by ALD. The post-deposition processing may include at least one of a pump/purge cycle and a water exposure cycle performed after formation of the silicon dioxide on a substrate.Type: GrantFiled: May 2, 2008Date of Patent: December 28, 2010Assignee: Micron Technology, Inc.Inventor: Shyam Surthi
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Patent number: 7858534Abstract: A semiconductor device manufacturing method comprises a process of forming a film on each of multiple substrates arrayed in a processing chamber by a thermal CVD method by supplying a film forming gas into the processing chamber while heating the interior of the processing chamber, wherein in the film forming process, a cycle is performed one time or multiple times with one cycle including a step of flowing the film forming gas from one end towards the other end along the substrate array direction, and a step of flowing the film forming gas from the other end towards the one end along the substrate array direction, without forming temperature gradient along the substrate array direction in the processing chamber.Type: GrantFiled: August 7, 2008Date of Patent: December 28, 2010Assignee: Hitachi Kokusai Electric Inc.Inventor: Kiyohiko Maeda
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Patent number: 7855121Abstract: Provided are a method of forming an organic semiconductor thin film and a method of manufacturing a semiconductor device using the. According to example embodiments, a method of forming an organic semiconductor thin film at least may include exposing a lower substrate coated with an organic semiconductor solution using a method of generating a shearing stress to the portion of the lower substrate coated with the organic semiconductor solution. A guide structure may be formed adjacent to the organic semiconductor solution.Type: GrantFiled: March 27, 2009Date of Patent: December 21, 2010Assignees: Samsung Electronics Co., Ltd., The Board of Trustees of the Laland Stanford Junior UniversityInventors: Do Hwan Kim, Sangyoon Lee, Hector Alejandro Becerril Garcia, Mark Roberts, Zhenan Bao, Zihong Liu
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Patent number: 7855404Abstract: A complementary BiCMOS semiconductor device comprises a substrate of a first conductivity type and a number of active regions which are provided therein and which are delimited in the lateral direction by shallow field insulation regions, in which vertical npn-bipolar transistors with an epitaxial base are arranged in a first subnumber of the active regions and vertical pnp-bipolar transistors with an epitaxial base are arranged in a second subnumber of the active regions, wherein either one transistor type or both transistor types have both a collector region and also a collector contact region in one and the same respective active region. To improve the high-frequency properties exclusively in a first transistor type in which the conductivity type of the substrate is identical to that of the collector region, an insulation doping region is provided between the collector region and the substrate.Type: GrantFiled: December 1, 2004Date of Patent: December 21, 2010Assignee: IHP GmbH—Innovations for High Performance Microelectronics/Leibniz-Instituit fur Innovative MikroelektronikInventors: Bernd Heinenman, Jürgen Drews, Steffen Marschmayer, Holger Rücker
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Patent number: 7851385Abstract: The present invention generally provides apparatus and method for processing a semiconductor substrate. Particularly, embodiments of the present invention relate to a method and apparatus for forming semiconductor devices having a conformal silicon oxide layer formed at low temperature. One embodiment of the present invention provides a method for forming a semiconductor gate structure. The method comprises forming a gate stack on a semiconductor substrate, forming a conformal silicon oxide layer on the semiconductor substrate using a low temperature cyclic method, and forming a spacer layer on the conformal silicon oxide layer.Type: GrantFiled: September 30, 2008Date of Patent: December 14, 2010Assignee: Applied Materials, Inc.Inventors: Matthew Spuller, Melody Agustin, Meiyee (Maggie Le) Shek, Li-Qun Xia, Reza Arghavani
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Patent number: 7838443Abstract: The invention concerns a method for minimizing “corner” effects in shallow silicon oxide trenches, by densifying the silicon oxide layer after it has been deposited in the trenches. Said densification is preferably carried out by irradiating the layer under luminous radiation with weak wavelength.Type: GrantFiled: June 29, 2007Date of Patent: November 23, 2010Inventors: Patrick Schiavone, Frédéric Gaillard
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Patent number: 7838400Abstract: A method of manufacturing a solar cell is provided. One surface of a semiconductor substrate is doped with a n-type dopant. The substrate is then subjected to a thermal oxidation process to form an oxide layer on one or both surfaces of the substrate. The thermal process also diffuses the dopant into the substrate, smoothing the concentration profile. The smoothed concentration gradient enables the oxide layer to act as a passivating layer. Anti-reflective coatings may be applied over the oxide layers, and a reflective layer may be applied on the surface opposite the doped surface to complete the solar cell.Type: GrantFiled: July 17, 2008Date of Patent: November 23, 2010Assignee: Applied Materials, Inc.Inventor: Peter Borden
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Patent number: 7838353Abstract: Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.Type: GrantFiled: August 12, 2008Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak