Deposition Of Silicon Oxide (epo) Patents (Class 257/E21.278)
-
Patent number: 7498273Abstract: Methods of depositing a dielectric layer in a gap formed on a substrate are described. The methods include introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber. The organo-silicon precursor has a C:Si atom ratio of less than 8, and the oxygen precursor comprises atomic oxygen that is generated outside the deposition chamber. The precursors are reacted to form the dielectric layer in the gap. Methods of filling gaps with dielectric materials are also described. These methods include providing an organo-silicon precursor having a C:Si atom ratio of less than 8 and an oxygen precursor, and generating a plasma from the precursors to deposit a first portion of the dielectric material in the gap. The dielectric material may be etched, and a second portion of dielectric material may be formed in the gap. The first and second portions of the dielectric material may be annealed.Type: GrantFiled: October 16, 2006Date of Patent: March 3, 2009Assignee: Applied Materials, Inc.Inventors: Abhijit Basu Mallick, Jeffrey C. Munro, Srinivas D. Nemani
-
Publication number: 20090053906Abstract: Disclosed is a producing method of a semiconductor device including: loading at least one substrate into a processing chamber; forming a metal oxide film or a silicon oxide film on a surface of the substrate by repeatedly supplying a metal compound or a silicon compound, each of which is a first material, an oxide material which is a second material including an oxygen atom, and a hydride material which is a third material, into the processing chamber predetermined times; and unloading the substrate from the processing chamber.Type: ApplicationFiled: July 19, 2007Publication date: February 26, 2009Inventors: Hironobu Miya, Kazuhiro Hirahara, Yoshitaka Hamada, Atsuhiko Suda
-
Patent number: 7495337Abstract: A dual-gate device is formed over and insulated from a semiconductor substrate which may include additional functional circuits that can be interconnected to the dual-gate device. The dual-gate device includes two semiconductor devices formed on opposite surfaces of a common active semiconductor region which is provided a thickness and material sufficient to isolate the semiconductor devices from electrostatically interacting. In one embodiment, one of the semiconductor devices includes a charge storing layer, such as an ONO layer. Such a dual-gate device is suitable for use in a non-volatile memory array.Type: GrantFiled: February 6, 2007Date of Patent: February 24, 2009Inventors: Andrew J. Walker, Maitreyee Mahajani
-
Patent number: 7491656Abstract: A silicon oxide film (1701) serving as a gate insulating film of a semiconductor device contains Kr. Therefore, the stress in the silicon oxide film (1701) and the stress at the interface between silicon and the silicon oxide film are relaxed, and the silicon oxide film has a high quality even though it was formed at a low temperature. The uniformity of thickness of the silicon oxide film (1701) on the silicon of the side wall of a groove (recess) in the element isolating region is 30% or less. Consequently, the silicon oxide film (1701) has its characteristics and reliability superior to those of a silicon thermal oxide film, and the element isolating region can be made small, thereby realizing a high-performance transistor integrated circuit preferably adaptable to an SOI transistor and a TFT.Type: GrantFiled: September 20, 2004Date of Patent: February 17, 2009Assignee: Foundation for Advancement of International ScienceInventor: Tadahiro Ohmi
-
Patent number: 7488673Abstract: A trench MOS Schottky barrier device has a metal oxide gate dielectric such as TiSi lining the trench wall to increase the efficiency of the elemental cell and to improve depletion in the mesa during reverse bias. A reduced mask process is used in which a single layer of titanium or other metal is deposited on an underlying gate oxide layer on the trench walls and directly atop the mesa between adjacent trenches. A common thermal treatment causes the Ti to diffuse into the SiO2 gate oxide to form the TiO2 gate and to form the TiSi Schottky barrier on the top surface of the mesa.Type: GrantFiled: February 23, 2007Date of Patent: February 10, 2009Assignee: International Rectifier CorporationInventors: Carmelo Sanfilippo, Rossano Carta, Giovanni Richieri, Paolo Mercaldi
-
Patent number: 7488677Abstract: A method of making an interconnect that includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure.Type: GrantFiled: August 14, 2006Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Kwong Hon Wong, Louis C. Hsu, Timothy J. Dalton, Carol Radens, Chih-Chao Yang, Lawrence A. Clevenger, Theodorus E. Standaert
-
Publication number: 20090029564Abstract: In a plasma oxidation treatment apparatus 100, dual plate structure 60 is arranged above a susceptor 2. An upper plate 61 and a lower plate 62 are made of a dielectric material such as quartz, separately arranged in parallel at a prescribed interval, for instance an interval of 5 mm, and have a plurality of through holes 61a, 62a. The two plates are arranged one over another by shifting the positions so that the through hole 62a of the lower plate 62 and the through hole 61a of the upper plate 61 are not overlapped.Type: ApplicationFiled: May 30, 2006Publication date: January 29, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Jun Yamashita, Toshio Nakanishi, Tatsuo Nishita
-
Patent number: 7476970Abstract: A method for fabricating a semiconductor device utilizing the step of forming a first insulating film of a porous material over a substrate; the step of forming on the first insulating film a second insulating film containing a silicon compound containing Si—CH3 bonds by 30-90%, and the step of irradiating UV radiation with the second insulating film formed on the first insulating film to cure the first insulating film. Thus, UV radiation having the wavelength which eliminates CH3 groups is sufficiently absorbed by the second insulating film, whereby the first insulating film is highly strengthened with priority by the UV cure, and the first insulating film can have the film density increased without having the dielectric constant increased.Type: GrantFiled: June 27, 2006Date of Patent: January 13, 2009Assignee: Fujitsu LimitedInventors: Shirou Ozaki, Yoshihiro Nakata, Ei Yano
-
Patent number: 7473649Abstract: A method of forming a slot in a substrate comprises growing an oxide layer on a first side of a substrate, patterning and etching the oxide layer to form an opening, forming a material overlying the opening and the oxide layer, removing substrate material through a second side to a first distance from the first side, and anisotropic etching the substrate to create a substrate opening at the first side which is aligned with the opening in the oxide layer during anisotropic etching. The material overlying the opening and the oxide layer is selected so that an anisotropic etch rate of the substrate at an interface of the material and the substrate is greater than an anisotropic etch rate of the substrate at an interface of the oxide layer and the substrate.Type: GrantFiled: July 24, 2006Date of Patent: January 6, 2009Inventors: Steven D Leith, Jeffrey S Obert, Eric L. Nikkel, Kenneth M Kramer
-
Patent number: 7470635Abstract: This invention includes methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming bit line over capacitor arrays of memory cells. In one implementation, a semiconductor substrate having an exposed outer first surface comprising silicon-nitrogen bonds and an exposed outer second surface comprising at least one of silicon and silicon dioxide is provided. A layer comprising a metal is deposited over at least the outer second surface. A silanol is flowed to the metal of the outer second surface and to the outer first surface effective to selectively deposit a silicon dioxide comprising layer over the outer second surface as compared to the outer first surface. Other aspects and implementations are contemplated.Type: GrantFiled: March 17, 2006Date of Patent: December 30, 2008Assignee: Micron Technology, Inc.Inventors: Weimin Li, Gurtej S. Sandhu
-
Patent number: 7470618Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.Type: GrantFiled: February 5, 2007Date of Patent: December 30, 2008Assignee: Renesas Technology Corp.Inventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
-
Patent number: 7465663Abstract: In fabrication of a semiconductor device which is provided with resistances and MOS transistors on the same substrate, conduction failures of contacts and leaching of wiring metal into a silicon substrate is prevented. Firstly, an underlying structure is prepared. Then, a silicon oxide layer is formed on the underlying structure. Then, a silicon nitride layer is formed on the silicon oxide layer. Then, an inter-layer insulation layer is formed on the silicon nitride layer. Then, a contact hole is formed penetrating through a laminate of the silicon oxide layer, the silicon nitride layer and the inter-layer insulation layer. A thickness of the silicon oxide layer is a value in a range from 32 nm to 48 nm.Type: GrantFiled: March 8, 2007Date of Patent: December 16, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Hiroshi Yonekura
-
Patent number: 7465625Abstract: According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric materials may be used to reduce conductivity between the two stacks. A dielectric material that is resistant to conductivity has a low dielectric constant (k). The lowest-k dielectric material is air, which has a dielectric constant of approximately 1. By creating a void between the two gate stacks, the least conductive material (air) is left filling the space between the gate stacks, and the likelihood of parasitic coupling of two adjacent floating gates is substantially reduced.Type: GrantFiled: October 17, 2006Date of Patent: December 16, 2008Inventors: Been-jon K. Woo, Yudong Kim, Albert Fazio
-
Patent number: 7462896Abstract: The object is simplification of a manufacturing process for nonvolatile memory by reducing additional processes for forming a charge storage structure, and downsizing of nonvolatile memory.Type: GrantFiled: June 29, 2006Date of Patent: December 9, 2008Assignee: Oki Electric Industry Co., Ltd.Inventors: Takaharu Nakamura, Tetsuhiro Maruyama, Masao Tsujimoto, Ikuo Kurachi
-
Patent number: 7459388Abstract: Methods of forming interconnect structures include forming a first metal wiring pattern on a first dielectric layer and forming a capping layer (e.g., SiCN layer) on the first copper wiring pattern. An adhesion layer is deposited on the capping layer, using a first source gas containing octamethylcyclotetrasilane (OMCTS) at a volumetric flow rate in a range from about 500 sccm to about 700 sccm and a second gas containing helium at a volumetric flow rate in a range from about 1000 to about 3000 sccm. The goal of the deposition step is to achieve an adhesion layer having an internal compressive stress of greater than about 150 MPa therein, so that the adhesion layer is less susceptible to etching/cleaning damage and moisture absorption during back-end processing steps. Additional dielectric and metal layers are then deposited on the adhesion layer.Type: GrantFiled: September 6, 2006Date of Patent: December 2, 2008Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing, Ltd., International Business Machines CorporationInventors: Jaehak Kim, Darryl D. Restaino, Johnny Widodo
-
Patent number: 7446060Abstract: Disclosed is a film-forming method, comprising supplying into a plasma processing chamber at least three kinds of gases including a silicon compound gas, an oxidizing gas, and a rare gas, the percentage of the partial pressure of the rare gas (Pr) based on the total pressure being not smaller than 85%, i.e., 85%?Pr<100%, and generating a plasma within the plasma processing chamber so as to form a film of silicon oxide on a substrate to be processed.Type: GrantFiled: January 3, 2007Date of Patent: November 4, 2008Assignee: Advanced LCD Technologies Development Center Co., Ltd.Inventors: Masashi Goto, Kazufumi Azuma, Yukihiko Nakata
-
Patent number: 7442640Abstract: Methods of manufacturing a semiconductor device including a high-voltage device region and a low-voltage device region are provided. An illustrated method includes forming, on a substrate, a gate pattern for a high-voltage device and a low-voltage device; implanting ions into opposite sides of the gate pattern, to form a lightly doped drain structure while implanting ions into a portion of the high-voltage device region under the same conditions as the low-voltage device region to form an electrostatic discharge protecting device region; forming a spacer at the side surface of the gate pattern; forming a source region and a drain source at field regions disposed at the opposite sides of the gate pattern, respectively; and forming a metal layer on the front surface of the substrate including the gate pattern.Type: GrantFiled: November 9, 2005Date of Patent: October 28, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: San Hong Kim
-
Patent number: 7439117Abstract: A method is described for designing a micro electromechanical device in which the risk of self-actuation of the device in use is reduced. The method includes locating a first conductor in a plane and locating a second conductor with its collapsible portion at a predetermined distance above the plane. The method also includes laterally offsetting the first conductor by a predetermined distance from a region of maximum actuation liability. The region of maximum actuation liability is where an attraction force to be applied to activate the device is at a minimum.Type: GrantFiled: December 23, 2005Date of Patent: October 21, 2008Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Hendrikus Tilmans, Xavier Rottenberg
-
Patent number: 7435691Abstract: A micromechanical component having a silicon substrate; a cavity provided in the substrate; and a diaphragm, provided on the surface of the substrate, which closes the cavity; the diaphragm featuring a silicon-oxide layer having an opening that is formed by silicon-oxide wedges pointing to each other; and the diaphragm having at least one closing layer which closes the opening. Also, a suitable manufacturing method.Type: GrantFiled: September 7, 2005Date of Patent: October 14, 2008Assignee: Robert Bosch GmbHInventor: Heribert Weber
-
Patent number: 7435684Abstract: This invention relates to electronic device fabrication processes for making devices such as semiconductor wafers and resolves the fluorine loading effect in the reaction chamber of a HDP CVD apparatus used for forming dielectric layers in high aspect ratio, narrow width recessed features. The fluorine loading effect in the chamber is minimized and wafers are provided having less deposition thickness variations by employing the method using a hydrogen plasma treatment of the chamber and the substrate after the chamber has been used to grow a dielectric film on a substrate. After the hydrogen plasma treatment of the chamber, the chamber is treated with an etchant gas to etch the substrate. Preferably a hydrogen gas is then introduced into the chamber after the etching process and the process repeated until the fabrication process is complete. The wafer is then removed from the chamber and a new wafer placed in the chamber and the above fabrication process repeated.Type: GrantFiled: July 26, 2006Date of Patent: October 14, 2008Assignee: Novellus Systems, Inc.Inventors: Chi-I Lang, Ratsamee Limdulpaiboon, Kan Quan Vo
-
Patent number: 7416986Abstract: A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.Type: GrantFiled: September 5, 2006Date of Patent: August 26, 2008Assignee: International Business Machines CorporationInventors: Huilong Zhu, Shih-Fen Huang, Effendi Leobandung
-
Patent number: 7416908Abstract: A method for fabricating a micro structure includes depositing a first layer of a first material over a substrate; patterning a first hard mask over the first layer; depositing a second layer of a second material over the first layer and the first hard mask; patterning a second hard mask over the second layer; and selectively removing the first material and the second material not covered by any of the first mask and the second mask to produce over the substrate the micro structure having a first structure portion having a first height and a second structure portion having a second height.Type: GrantFiled: May 10, 2006Date of Patent: August 26, 2008Assignee: Spatial Photonics, Inc.Inventors: Chii Guang Lee, Shaoher X. Pan, Hung Kwei Hu
-
Patent number: 7413998Abstract: A biased pulse DC reactor for sputtering of oxide films is presented. The biased pulse DC reactor couples pulsed DC at a particular frequency to the target through a filter which filters out the effects of a bias power applied to the substrate, protecting the pulsed DC power supply. Films deposited utilizing the reactor have controllable material properties such as the index of refraction. Optical components such as waveguide amplifiers and multiplexers can be fabricated using processes performed on a reactor according to the present invention.Type: GrantFiled: September 16, 2005Date of Patent: August 19, 2008Assignee: SpringWorks, LLCInventors: Hongmei Zhang, Mukundan Narasimhan, Ravi B. Mullapudi, Richard E. Demaray
-
Patent number: 7408215Abstract: A DRAM structure on a silicon substrate has an active area, gate conductors, deep trench capacitors, and vertical transistors. The deep trench capacitors are formed at intersections of the active area and the gate conductors, and each deep trench capacitor is coupled electrically to the corresponding vertical transistor to form a memory cell. The transistor includes a gate, a source in a lateral side of the gate, and a drain in another lateral side of the gate The depth of the drain is different from the depth of the source.Type: GrantFiled: April 3, 2007Date of Patent: August 5, 2008Assignee: Nanya Technology Corp.Inventors: Ming-Cheng Chang, Neng-Tai Shih
-
Patent number: 7397074Abstract: An exemplary array of thermally-assisted magnetic memory structures includes a plurality of magnetic memory elements, each magnetic memory element being near a diode. A diode near a selected magnetic memory element can be heated by absorbing energy from a radio frequency electromagnetic field. The heated diode can be used to elevate the temperature of the selected magnetic memory element to thermally assist in switching the magnetic state of the magnetic memory element upon application of a write current.Type: GrantFiled: January 12, 2005Date of Patent: July 8, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Janice H. Nickel
-
Patent number: 7393736Abstract: The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO2), hafnium oxide (HfO2) and tin oxide (SnO2) acting as a single dielectric layer with a formula of ZrXHfYSn1-X-YO2, and a method of fabricating such a dielectric layer is described that produces a reliable structure with a high dielectric constant (high k). The dielectric structure is formed by depositing zirconium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing hafnium oxide onto the substrate using precursor chemicals, followed by depositing tin oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure. Such a dielectric may be used as a gate insulator, a capacitor dielectric, or as a tunnel insulator in non-volatile memories, because the high dielectric constant (high k) provides the functionality of a much thinner silicon dioxide film.Type: GrantFiled: August 29, 2005Date of Patent: July 1, 2008Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
-
Patent number: 7374964Abstract: The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric layer is described. The described arrangement produces a reliable structure with a high dielectric constant (high-k) for use in a variety of electronic devices. The dielectric structure is formed by depositing cerium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing aluminum oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure.Type: GrantFiled: February 10, 2005Date of Patent: May 20, 2008Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
-
Patent number: 7368359Abstract: A semiconductor substrate (100) is acquired by forming a mask with a target thickness on a major surface of a single-crystal silicon substrate, implanting oxygen ions to the major surface at a high temperature, forming a surface protection layer for blocking oxygen on the major surface, performing annealing, and then stripping off the mask and the surface protection layer. A silicon dioxide layer (102) has a first tip surface (102a) corresponding to an area where the mask has not existed and having a relatively long distance from the major surface (100a), and a second top surface (102b) corresponding to an area where the mask has existed and having a relatively short distance from the major surface (100a). As this major surface (100a) is polished by a predetermined quantity, a semiconductor substrate is provided in which only a part of a single-crystal silicon substrate is a SOI substrate.Type: GrantFiled: October 25, 2004Date of Patent: May 6, 2008Assignees: Sony Corporation, Regents of the University of CaliforniaInventors: Koichiro Kishima, Prakash Koonath
-
Patent number: 7348204Abstract: A method for fabricating a solid state imaging device comprising photoelectric conversion sections and charge transfer sections having single-layered charge transfer electrodes for transferring charges generated in the photoelectric conversion sections, the method including formation of the charge transfer electrodes, wherein the formation of the charge transfer electrodes comprises the steps of: forming a conductive film on a surface of a semiconductor substrate having formed thereon a gate oxide film; forming a mask pattern on the conductive film; forming interelectrode spacings in the conductive film using the mask pattern as a mask to make a patterned conductive film; and forming an insulating film to fill in the interelectrode spacings by vacuum chemical vapor deposition.Type: GrantFiled: April 8, 2005Date of Patent: March 25, 2008Assignee: Fujifilm CorporationInventor: Hiroaki Takao
-
Publication number: 20080009143Abstract: Disclosed is a method of forming a silicon oxide layer comprising: supplying at least a gas containing Si as a raw gas to a semiconductor substrate having a recess formed on its surface to form a primary reactant on the surface, then performing dehydration condensation to form a silicon oxide layer above the semiconductor substrate; removing a part of the silicon oxide layer until a portion of the silicon oxide layer formed in the recess that has a lower density than the silicon oxide layer formed in a vicinity of the surface is at least partially exposed; and supplying a gas containing Si to the silicon oxide layer having a lower density.Type: ApplicationFiled: June 26, 2007Publication date: January 10, 2008Inventors: Nobuhide Yamada, Rempei Nakata, Yukio Nishiyama
-
Publication number: 20070279562Abstract: An alignment layer for an LCD includes a thin layer of silicon oxide SiOx. The silicon oxide layer horizontally aligns liquid crystals thereon when the value of x is in the range from about 1.0 to about 1.5, but vertically aligns the liquid crystals when the value of x is in a range from about 1.5 to about 2.0. The alignment layer is readily formed on a large area of the substrate through chemical vapor deposition or evaporation deposition. Because the alignment layer is thermally and physically stable, the operational characteristics of the liquid crystal display employing this alignment layer are improved. In addition, the alignment layer has a thickness of about 500 to about 3000 angstroms thereby improving light transmittance of the LCD having the alignment layer.Type: ApplicationFiled: April 12, 2007Publication date: December 6, 2007Inventors: Soon-Joon Rho, Baek-Kyun Jeon, Kyoong-Ok Park, Hee-Keun Lee, Hong-Koo Baik, Kyung-Chan Kim, Jong-Bok Kim, Byoung-Har Hwang, Dong-Choon Hyun, Han-Jin Ahn
-
Publication number: 20070207627Abstract: In-situ steam generation (ISSG) is used to reduce the nitrogen concentration in silicon and silicon oxide areas.Type: ApplicationFiled: March 1, 2006Publication date: September 6, 2007Inventors: Zhong Dong, Chiliang Chen, Ching-Hwa Chen
-
Patent number: 7259111Abstract: A method of depositing a organosilicate dielectric layer exhibiting high adhesion strength to an underlying substrate disposed within a single processing chamber without plasma arcing. The method includes positioning a substrate within a processing chamber having a powered electrode, flowing an interface gas mixture into the processing chamber, the interface gas mixture comprising one or more organosilicon compounds and one or more oxidizing gases, depositing a silicon oxide layer on the substrate by varying process conditions, wherein DC bias of the powered electrode varies less than 60 volts.Type: GrantFiled: June 1, 2005Date of Patent: August 21, 2007Assignee: Applied Materials, Inc.Inventors: Deenesh Padhi, Ganesh Balasubramanian, Annamalai Lakshmanan, Zhenjiang Cui, Juan Carlos Rocha-Alvarez, Bok Hoen Kim, Hichem M'Saad, Steven Reiter, Francimar Schmitt
-
Patent number: 7259112Abstract: The invention concerns a method for minimizing “corner” effects in shallow silicon oxide trenches, by densifying the silicon oxide layer after it has been deposited in the trenches. Said densification is preferably carried out by irradiating the layer under luminous radiation with weak wavelength.Type: GrantFiled: July 8, 1998Date of Patent: August 21, 2007Assignee: Fahrenheit Thermoscope, LLCInventors: Patrick Schiavone, Frédéric Gaillard
-
Patent number: 7253036Abstract: A method of forming a gate insulation film of a crystallized thin film transistor, is provided, which can enhance an interfacial feature which exists between a gate oxide film and a silicon thin film substrate and which is fatal to performance of the thin film transistor, in the case that crystallization of amorphous silicon is performed by metal induced lateral crystallization (MILC). The gate insulation film formation method includes the steps of: forming an amorphous silicon film on an insulation substrate, and then patterning the amorphous silicon film, to thereby form a semiconductor layer; processing the semiconductor layer made of the amorphous silicon film by an oxygen plasma method, and oxidizing the silicon surface, to thereby form a first silicon oxide film; and mixing gas with silicon and depositing a second silicon oxide film on the first silicon oxide film by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.Type: GrantFiled: May 3, 2005Date of Patent: August 7, 2007Inventor: Woon Suh Paik
-
Publication number: 20070148958Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: ApplicationFiled: August 4, 2006Publication date: June 28, 2007Inventors: Lawrence Clevenger, Stefanie Chiras, Timothy Dalton, James Demarest, Derren Dunn, Chester Dziobkowski, Philip Flaitz, Michael Lane, James Lloyd, Darryl Restaino, Thomas Shaw, Yun-Yu Wang, Chih-Chao Yang
-
Patent number: 7235502Abstract: A gate dielectric structure (201) fabrication process includes forming a transitional dielectric film (205) overlying a silicon oxide film (204). A high dielectric constant film (206) is then formed overlying an upper surface of the transitional dielectric film (205). The composition of the transitional dielectric film (205) at the silicon oxide film (204) interface primarily comprises silicon and oxygen. The high K dielectric (206) and the composition of the transitional dielectric film (205) near the upper surface primarily comprise a metal element and oxygen. Forming the transitional dielectric film (205) may include forming a plurality of transitional dielectric layers (207) where the composition of each successive transitional dielectric layer (207) has a higher concentration of the metal element and a lower concentration of silicon.Type: GrantFiled: March 31, 2005Date of Patent: June 26, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Sriram S. Kalpat, Voon-Yew Thean, Hsing H. Tseng, Olubunmi O. Adetutu
-
Patent number: 7235449Abstract: A method of forming a gate oxide film for high voltage region of semiconductor devices includes forming patterns on a semiconductor substrate having a high voltage region, thereby exposing only a gate oxide film formation region for high voltage, forming a metal oxidization layer on the entire surface, and performing a process of removing the patterns, thereby forming the metal oxidization layer only in the gate oxide film formation region for high voltage.Type: GrantFiled: June 28, 2005Date of Patent: June 26, 2007Assignee: Hynix Semiconductor Inc.Inventor: Eun Soo Kim
-
Publication number: 20070120230Abstract: In a layer structure, a method of forming the layer structure, a method of manufacturing a capacitor having the layer structure and a method of manufacturing a semiconductor device having the capacitor, a structure may be formed on a substrate. A first insulation layer including at least one kind of impurities may be formed on the structure. A flatness of the first insulation layer may fluctuate according to the type and concentration of the impurities. The first insulation layer may include silicate glass doped with first impurities including an element in Group III and/or second impurities including an element in Group V. The flatness of the first insulation layer may improve in proportion to the concentration of the first impurities whereas in inverse proportion to the concentration of the second impurities. Accordingly, the flatness of the first insulation layer may be determined by adjusting the type and concentration of the impurities.Type: ApplicationFiled: October 24, 2006Publication date: May 31, 2007Inventors: Shin-Hye Kim, Ju-Bum Lee, Do-Hyung Kim
-
Publication number: 20070072412Abstract: Prevention of damage to an interlevel dielectric (ILD) is provided by forming an opening (e.g., trench) in the ILD, and sputtering a dielectric film onto a sidewall of the opening by overetching into a layer of the dielectric below or within the ILD during forming of the opening. The re-sputtered film protects the sidewall of the opening from subsequent plasma/ash processes and seals the porous dielectric surface along the sidewall and bottom without impacting overall process throughput. A semiconductor structure resulting from the above process is also disclosed.Type: ApplicationFiled: September 27, 2005Publication date: March 29, 2007Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES, INC. (AMD)Inventors: Derren Dunn, Nicholas Fuller, Catherine Labelle, Vincent McGahay, Sanjay Mehta, Henry Nye III
-
Patent number: 7192888Abstract: A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the nucleation layer, and forming a layer of a second substance at least one monolayer thick chemisorbed on the first substance. The chemisorption product of the first and second substance may include silicon and nitrogen. The nucleation layer may comprise silicon nitride. Further, a deposition method may include forming a first part of a nucleation layer on a first surface of a substrate and forming a second part of a nucleation layer on a second surface of the substrate. A deposition layer may be formed on the first and second parts of the nucleation layer substantially non-selectively on the first part of the nucleation layer compared to the second part. The first surface may be a surface of a borophosphosilicate glass layer. The second surface may be a surface of a rugged polysilicon layer.Type: GrantFiled: August 21, 2000Date of Patent: March 20, 2007Assignee: Micron Technology, Inc.Inventor: Garry A. Mercaldi
-
Patent number: 7192893Abstract: A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. The ozone delivery is pulsed on and off. Optionally, the delivery of the ozone and the delivery of the TEOS are pulsed on and off alternately.Type: GrantFiled: August 5, 2003Date of Patent: March 20, 2007Assignee: Micron Technology Inc.Inventors: William Budge, Gurtej S. Sandhu, Christopher W. Hill
-
Publication number: 20070059896Abstract: A method of filling a gap defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate and providing a flow of an oxidizing gas to the chamber. The method also includes varying over time a ratio of the (silicon-containing processing gas):(oxidizing gas). The method also includes exposing the substrate to nitrous oxide at a temperature less than about 900° C. to anneal the deposited film.Type: ApplicationFiled: October 16, 2006Publication date: March 15, 2007Applicant: Applied Materials, Inc.Inventors: Zheng Yuan, Reza Arghavani, Shankar Venkataraman
-
Publication number: 20070026653Abstract: A method for capping over a doped dielectric. The method comprises providing a substrate and depositing a doped dielectric layer on the substrate from a gas mixture. The gas mixture comprises a silicon source gas, a dopant gas and an oxygen source gas. A cap layer is in-situ deposited on the doped dielectric layer from the gas mixture substantially in absence of the dopant gas.Type: ApplicationFiled: July 26, 2005Publication date: February 1, 2007Inventors: Po-Hsiung Leu, Shu-Tine Yang, Ying-Hsiu Tsai, Shin-Yeu Tsai, Tsang-Yu Liu, Ming-Te Chen, Szu-An Wu, Harry Chuang
-
Patent number: 7071126Abstract: An interlayer dielectric may be exposed to a gas cluster ion beam to densify an upper layer of the interlayer dielectric. As a result, the upper layer of the interlayer dielectric may be densified without separate deposition steps and without the need for etch stops that may adversely affect the capacitance of the overall structure.Type: GrantFiled: April 8, 2005Date of Patent: July 4, 2006Assignee: Intel CorporationInventors: Steven W. Johnston, Kevin P. O'Brien