Abstract: Methods for forming a gate using quantum dots are disclosed. More particularly, the present invention relates to a method for forming quantum dots for fabrication of an ultrafine semiconductor device includes a gate with quantum dots. The present invention is capable of forming quantum dots in uniform sizes and at uniform intervals so as to achieve an electrically stable device.

Abstract: A method for dividing a wafer into a plurality of chips is provided. The method includes providing recesses in a surface of the wafer at positions along boundaries between regions to become the individual chips, providing fragile portions having a predetermined width inside the wafer at positions along the boundaries by irradiation of the other surface of the wafer with a laser beam whose condensing point is placed inside the wafer, the fragile portions including connected portions at least at one of the surfaces of the wafer, and dividing the wafer at the fragile portions into the individual chips by applying an external force to the wafer.

Abstract: A semiconductor device includes a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.

Abstract: A semiconductor structure which includes a trench gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD.

Abstract: After forming a stack of layers (130, 140, 310) for a transistor or a charge-trapping memory over an active area (110), and before etching isolation trenches (160) in the semiconductor substrate (120) with the stack as a mask, spacers (610) are formed on the stack's sidewalls. The trench etch may include a lateral component, so the top edges of the trenches may be laterally recessed to a position under the spacers or the stack. After the etch, the spacers are removed to facilitate filling the trenches with the dielectric (to eliminate voids at the recessed top edges of the trenches). Other embodiments are also provided.

Abstract: Described herein are methods of forming dielectric films comprising silicon, such as, but not limited to, silicon oxide, silicon oxycarbide, silicon carbide, and combinations thereof, that exhibit at least one of the following characteristics: low wet etch resistance, a dielectric constant of 6.0 or below, and/or can withstand a high temperature rapid thermal anneal process. Also disclosed herein are the methods to form dielectric films or coatings on an object to be processed, such as, for example, a semiconductor wafer.

Abstract: A method for forming a through-silicon via bandpass filter includes forming a substrate comprising a silicon layer and providing a metal layer on a bottom side of the silicon layer. Additionally, the method includes providing a dielectric layer on a top side of the silicon layer and forming a top-side interconnect of the through-silicon via bandpass filter on a surface of the dielectric layer. Further, the method includes forming a plurality of contacts in the dielectric layer in contact with the top-side interconnect and forming a plurality through-silicon vias through the substrate and in contact with the plurality of contacts, respectively, and the metal layer.

Abstract: An interconnection structure includes an inter-level insulation layer disposed on a semiconductor substrate. First contact structures are formed in the inter-level insulation layer. Second contact structures are formed in the inter-level insulation layer and are spaced apart from the first contact structures. First spacers are disposed between the first contact structures and the inter-level insulation layer. Second spacers are disposed between the second contact structures and the inter-level insulation layer. Metal interconnections are disposed on the inter-level insulation layer and connected to the first and second contact structures. The first contact structures include first and second plugs stacked in sequence, the second contact structures include the second plugs, and the first spacers include an upper spacer disposed between the second plug and the inter-level insulation layer.

Abstract: An oxide film forming equipment is provided with a reactor 10 in which a heater unit 14 holding a substrate 100 is stored, a piping 11 provided with a material gas introducing valve V1 for introducing a material gas containing organic silicon or organic metal into the reactor, a piping 12 provided with an ozone containing gas introducing valve V2 for introducing an ozone containing gas into the reactor 10, and a piping 13 provided with an exhaustion valve 13 for exhausting a gas in the reactor 10. When the material gas introducing valve V1, the ozone containing gas introducing valve V2, and the exhaustion valve V3 perform open-and-closure operations to alternately supply the material gas and the ozone containing gas into the reactor 10, the ozone containing gas introducing valve V2 operates to fall an ozone concentration of the ozone containing gas in a range from 0.1 vol % to 100 vol % and the heater unit adjusts a temperature of the substrate from a room temperature to 400° C.

Abstract: A dielectric layer including cerium oxide and aluminum oxide acting as a single dielectric layer, and a method of fabricating such a dielectric layer, produces a reliable structure with a high dielectric constant (high-k) for use in a variety of electronic devices. Such a dielectric layer including cerium oxide and aluminum oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memory, or as a dielectric in an NROM device, among others, because the high dielectric constant (high-k) of the film provides the functionality of a much thinner silicon dioxide film.

Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

Abstract: Disclosed is a producing method of a semiconductor device, including: loading at least one substrate formed on a surface thereof with a tungsten film into a processing chamber; and forming a silicon oxide film on the surface of the substrate which includes the tungsten film by alternately repeating following steps a plurality of times: supplying the processing chamber with a first reaction material including a silicon atom while heating the substrate at 400° C.; and supplying the processing chamber with hydrogen and water which is a second reaction material while heating the substrate at 400° C. at a ratio of the water with respect to the hydrogen of 2×10?1 or lower.

Abstract: A substrate processing apparatus is provided to enable to efficiently remove an oxide layer and an organic material layer. A third process unit (36) of a substrate processing apparatus (10) includes a box-shaped process vessel (chamber) (50), a nitrogen gas supply system (190) and an ozone gas supply system (191). The ozone gas supply system (191) includes an ozone gas supply unit (195) and an ozone gas supply pipe (196) connected to the ozone gas supply unit (195). The ozone gas supply pipe (196) has an ozone gas supply hole (197) having an opening arranged opposite to a wafer (W). The ozone gas supply unit (195) supplies an ozone (O3) gas into the chamber (50) through the ozone gas supply hole (197) via the ozone gas supply pipe (196).

Abstract: A method for forming an oxide film includes a first in-situ steam generation (ISSG) process using a 1%-H2 concentration in the ambient gas and a subsequent second ISSG process using a 5%-H2 concentration in the ambient gas, wherein the second ISSG process compensates an in-plane thickness distribution of the film formed by the first ISSG process. The time length for the first and second ISSG steps is determined based on a desired film thickness, a time length dependency of a film formed by the second ISSG process, and the oxidation rate of the first and second ISSG processes.

Abstract: Provided is a silicon nitride film which has an excellent charge storage capacity and thus is useful as a charge storage layer of a semiconductor memory device. The silicon nitride film having substantially uniform trap density in the film thickness direction has high charge storage performance. The silicon nitride film is formed by plasma CVD by using a plasma processing apparatus (100), wherein microwaves are introduced into a chamber (1) by a plane antenna having a plurality of holes, plasma is generated by the microwaves while a source gas including nitrogen-containing compound and silicon-containing compound is introduced into the chamber (1), and the silicon nitride film is deposited on the surface of a processing object by the plasma.

Abstract: In the method of fabricating an optical semiconductor device, a semiconductor layer is formed on an InP region, and includes semiconductor films. A first etching mask is formed on the semiconductor layer. The semiconductor layer is etched through the first etching mask to form a semiconductor mesa and a first marking mesa, each mesa includes an active layer and an InP cladding layer, the InP cladding layer being provided on the active layer. The active layer is made of semiconductor material different from InP. An InP burying region is grown through the first etching mask on a side of the semiconductor mesa and a side of the first marking mesa to bury the semiconductor mesa and the first marking mesa. A second etching mask is formed on the InP burying region after removing the first etching mask, and has an opening located above the first marking mesa. InP in the InP burying region and the first marking mesa is etched through the second etching mask to form a second marking mesa.

Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.

Abstract: The present invention relates, in general, to a method for three-dimensional (3D) microfabrication of complex, high aspect ratio structures with arbitrary surface height profiles in metallic materials, and to devices fabricated in accordance with this process. The method builds upon anisotropic deep etching methods for metallic materials previously developed by the inventors by enabling simplified realization of complex, non-prismatic structural geometries composed of multiple height levels and sloping and/or non-planar surface profiles. The utility of this approach is demonstrated in the fabrication of a sloping electrode structure intended for application in bulk micromachined titanium micromirror devices, however such a method could find use in the fabrication of any number of other microactuator, microsensor, microtransducer, or microstructure devices as well.

Abstract: A method for forming spacers of different sizes includes the following steps. First a substrate is provided, which has a first element, a second element, a first material layer and a second material layer thereon. A first dry etching is performed to remove part of the second material layer to form a first spacer by the first element and to form a second side wall by the second element, so that the first material layer between the first spacer and the second side wall is exposed to become a damaged first material layer. A trimming procedure is performed to trim the damaged first material layer. A mask is used to cover the first element, the first spacer and part of the first material layer then a wet etching is performed to remove the second side wall.

Abstract: A method of filling a gap defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate and providing a flow of an oxidizing gas to the chamber. The method also includes varying over time a ratio of the (silicon-containing processing gas):(oxidizing gas). The method also includes exposing the substrate to nitrous oxide at a temperature less than about 900° C. to anneal the deposited film.

Abstract: A method of forming an insulating layer of a semiconductor device, the method including preparing a semiconductor substrate having a plurality of structures and gaps between adjacent structures, forming an insulating layer for oxygen supply on the semiconductor substrate, forming an SOG (spin-on-glass) layer on the insulating layer for oxygen supply to fill the gaps, and curing the SOG layer, wherein the insulating layer for oxygen supply supplies oxygen to the SOG layer during curing of the SOG layer.

Abstract: Provided is a method of manufacturing a semiconductor device including at least two processes. Under an atmosphere comprising hydrogen and oxygen, a sacrificial oxide film is formed on a silicon substrate that is provided with at least one nitride region. Then, the sacrificial oxide film and the nitride region are removed from the silicon substrate.

Abstract: One or more embodiments relate to a method of making a heterojunction bipolar transistor (HBT) structure. The method includes: forming a partially completed heterojunction bipolar transistor (HBT) structure where the partially completed heterojunction bipolar transistor (HBT) structure includes a silicon layer having an exposed surface and a nitride layer having an exposed surface. The method includes growing a first oxide on the silicon layer and etching the nitride layer using an etchant.

Abstract: According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a conductive layer on the first insulating film; exposing the first insulating film by removing a portion of the conductive layer; forming a second insulating film on the exposed surface of the first insulating film in a first processing chamber isolated from an outside; performing a modification process on the second insulating film in the first processing chamber, and then unloading the semiconductor substrate from the first processing chamber to the outside; and annealing the second insulating film in a second processing chamber.

Abstract: According to various embodiments, there are eSiGe CMOS devices and methods of making them. The method of making a substrate for a CMOS device can include providing a DSB silicon substrate including a first bonded to a second layer, wherein each layer has a (100) oriented surface and a first direction and a second direction and the first direction of the first layer is approximately aligned with the second direction of the second layer. The method can also include performing amorphization on a selected region of the first layer to form a localized amorphous silicon region and recrystallizing the localized amorphous silicon region across the interface using the second layer as a template, such that the first direction of the first layer in the selected region is approximately aligned with the first direction of the second layer.

Abstract: A method of sealing a microelectromechanical system (MEMS) device from ambient conditions is described, wherein the MEMS device is formed on a substrate and a substantially hermetic seal is formed as part of the MEMS device manufacturing process. The method comprises forming a metal seal on the substrate proximate a perimeter of the MEMS device using a method such as photolithography. The metal seal is formed on the substrate while the MEMS device retains a sacrificial layer between conductive members of MEMS elements, and the sacrificial layer is removed after formation of the seal and prior to attachment of a backplane.

Abstract: In an embodiment, a method of forming a lower electrode of a capacitor in a semiconductor memory device includes etching a mold oxide layer to have at a cylindrical structure, resulting in an electrode with increased surface area. The cylindrical structure may have more than one radius. This increased surface area results in an increased capacitance. An excessive etch phenomenon, which occurs because a sacrificial oxide layer is etched at a higher rate than the mold oxide layer, is avoided.

Abstract: Fabrication methods for making thin film devices on transparent substrates are described. Gate, source, and drain electrodes of a transistor are formed on a transparent substrate. The widths of the drain electrode and source electrodes are greater than a width of the gate electrode. A dielectric layer is formed on the gate electrode. A semiconductor layer is deposited proximate to the gate, source and drain electrodes. Photoresist is deposited on the semiconductor. The photoresist is exposed to light directed through the transparent substrate so that the gate electrode masks the photoresist from the light. The semiconductor layer is removed in regions exposed to the light.

Abstract: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate. The horizontal member of the first gate overlaps the horizontal member of the second gate.

Abstract: Methods for reducing and inhibiting defect formation on silicon dioxide formed by atomic layer deposition (ALD) are disclosed. Defect reduction is accomplished by performing processing on the silicon dioxide subsequent to deposition by ALD. The post-deposition processing may include at least one of a pump/purge cycle and a water exposure cycle performed after formation of the silicon dioxide on a substrate.

Abstract: Provided are a silicon structure having an opening which has a high aspect ratio and an etching mask for forming the silicon structure. A step of performing hole etching or trench etching of silicon so as to substantially expose a portion of at least a bottom surface of etched silicon and a step of forming a silicon oxide film by a CVD method on the silicon structure formed by the step of performing the hole etching or the trench etching are conducted. Thereafter, a step of exposing the formed silicon oxide film to a gas containing a hydrogen fluoride vapor is conducted. Further, the above-mentioned step of performing the hole etching or the trench etching is conducted again.

Abstract: Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 ?m without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.

Abstract: A heat processing method for a semiconductor process includes placing a plurality of target substrates stacked at intervals in a vertical direction within a process field of a process container. Each of the target substrates includes a process object layer on its surface. Then, the method includes supplying an oxidizing gas and a deoxidizing gas to the process field while heating the process field, thereby causing the oxidizing gas and the deoxidizing gas to react with each other to generate oxygen radicals and hydroxyl group radicals, and performing oxidation on the process object layer of the target substrates by use of the oxygen radicals and the hydroxyl group radicals. Then, the method includes heating the process object layer processed by the oxidation, within an atmosphere of an annealing gas containing ozone or oxidizing radicals, thereby performing annealing on the process object layer.

Abstract: A method for manufacturing a semiconductor device which includes: alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate, wherein the silicon source is supplied under a supply condition where an adsorption amount of molecules of the silicon source on the semiconductor substrate is increased without causing an adsorption saturation of the molecules of the silicon source on the semiconductor substrate, and wherein the oxidant is supplied under a supply condition where impurities remain in the molecules of the silicon source adsorbed on the semiconductor substrate.

Abstract: A semiconductor device with a WLP structure that enables the improvement of heat resistance. A dam layer which spreads over a PI film and an Si substrate for a chip is formed between the Si substrate and a sealing resin so as to surround the chip on all sides. A material for the dam layer is selected so that good adhesion will be obtained between the dam layer and the Si substrate, between the dam layer and the PI film, and between the dam layer and the sealing resin. As a result, even if a crack appears at a portion on a side of the semiconductor device where the Si substrate and the sealed resin are joined in a heating environment, the crack does not run inside the dam layer. This prevents the peeling of the sealing resin or peeling inside the chip and the performance of the semiconductor device is maintained.

Abstract: An object is to provide a method for manufacturing, with high yield, a semiconductor device having a crystalline semiconductor layer even if a substrate with low upper temperature limit. A groove is formed in a part of a semiconductor substrate to form a semiconductor substrate that has a projecting portion, and a bonding layer is formed to cover the projecting portion. In addition, before the bonding layer is formed, a portion of the semiconductor substrate to be the projecting portion is irradiated with accelerated ions to form a brittle layer. After the bonding layer and the supporting substrate are bonded together, heat treatment for separation of the semiconductor substrate is performed to provide a semiconductor layer over the supporting substrate. The semiconductor layer is selectively etched, and a semiconductor element is formed and a semiconductor device is manufactured.

Abstract: A method for using a film formation apparatus includes, in order to inhibit metal contamination: performing a cleaning process using a cleaning gas on an inner wall of a process container and a surface of a holder with no productive target objects held thereon; and then, performing a coating process of forming a silicon nitride film by alternately supplying a silicon source gas and a nitriding gas to cover with the silicon nitride film the inner wall of the process container and the surface of the holder with no productive target objects held thereon.

Abstract: A method is provided for forming a rare earth element-doped silicon oxide (SiO2) precursor with nanocrystalline (nc) Si particles. In one aspect the method comprises: mixing Si particles into a first organic solvent, forming a first solution with a first boiling point; filtering the first solution to remove large Si particles; mixing a second organic solvent having a second boiling point, higher than the first boiling point, to the filtered first solution; and, fractionally distilling, forming a second solution of nc Si particles. The Si particles are formed by immersing a Si wafer into a third solution including hydrofluoric (HF) acid and alcohol, applying an electric bias, and forming a porous Si layer overlying the Si wafer. Then, the Si particles are mixed into the organic solvent by depositing the Si wafer into the first organic solvent, and ultrasonically removing the porous Si layer from the Si wafer.

Abstract: A spin-on glass (SOG) composition and a method of forming a silicon oxide layer utilizing the SOG composition are disclosed. The method includes coating on a semiconductor substrate having a surface discontinuity, an SOG composition containing polysilazane having a compound of the formula —(SiH2NH)n— wherein n represents a positive integer, a weight average molecular weight within the range of about 3,300 to 3,700 to form a planar SOG layer. The SOG layer is converted to a silicon oxide layer with a planar surface by curing the SOG layer. Also disclosed is a semiconductor device made by the method.

Abstract: A method for forming an insulation film on a semiconductor substrate by plasma reaction includes: vaporizing a silicon-containing hydrocarbon having a Si—O bond compound to provide a source gas; introducing the source gas and a carrier gas without an oxidizing gas into a reaction space for plasma CVD processing; and forming an insulation film constituted by Si, C, O, and H on a substrate by plasma reaction using a combination of low-frequency RF power and high-frequency RF power in the reaction space. The plasma reaction is activated while controlling the flow of the reaction gas to lengthen a residence time, Rt, of the reaction gas in the reaction space.

Abstract: A fabrication method of a semiconductor device is disclosed by which damage to another film or exfoliation of a film is prevented and an insulating film having a dielectric constant of 2.5 or less can be formed while a film strength is maintained without deteriorating a wiring line characteristic. According to an embodiment, an insulating film is formed on a substrate by a plasma process, which uses film-forming gas having a ring structure of Si—O bonds, such that it maintains the ring structure of the Si—O bonds. According to another embodiment, an insulating film is formed on a substrate by a plasma process, which uses film-forming gas which contains silane-containing gas and oxygen gas or film-forming gas which contains Si—O bond-containing gas, such that it has a ring structure of the Si—O bonds.

Abstract: Methods are provided for depositing silicon dioxide containing thin films on a substrate by atomic layer deposition ALD. By using disilane compounds as the silicon source, good deposition rates and uniformity are obtained.

Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.

Abstract: (1) A metal oxide dispersion for a dye-sensitized solar cell, which contains metal oxide fine particles, a binder composed of a polymer compound having an action to bind to the fine particles and a solvent; (2) a method for producing a photoactive electrode for a dye-sensitized solar cell by coating a dispersion containing the above-mentioned binder and metal oxide fine particles on a sheet-shaped electrode; (3) a photoactive electrode for a dye-sensitized solar cell, obtained by the method, which electrode has metal oxide containing the above-mentioned binder and metal oxide fine particles; and (4) a dye-sensitized solar cell with the above-mentioned photoactive electrode.

Abstract: A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed and composed to yield a select stress amount and type. A gate layer, such as a polysilicon layer, is formed over the metal stress inducing layer. The gate layer and the metal stress inducing layer are patterned to define gate structures.

Abstract: The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer with a ratio of approximately two to one between the cerium oxide and the aluminum oxide, and a method of fabricating such a dielectric layer is described. The described arrangement produces a reliable structure with a high dielectric constant (high-k) for use in a variety of electronic devices. The dielectric structure is formed by depositing cerium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing aluminum oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure.

Abstract: A process for depositing a thin film material on a substrate is disclosed, comprising simultaneously directing a series of gas flows from the output face of a delivery head of a thin film deposition system toward the surface of a substrate, and wherein the series of gas flows comprises at least a first reactive gaseous material, an inert purge gas, and a second reactive gaseous material, wherein the first reactive gaseous material is capable of reacting with a substrate surface treated with the second reactive gaseous material. A system capable of carrying out such a process is also disclosed.

Abstract: A method and apparatus for depositing a material layer onto a substrate is described. The method includes delivering a mixture of precursors for the material layer into a process chamber and depositing the material layer on the substrate at low temperature. The material layer can be used as an encapsulating layer for various display applications which require low temperature deposition process due to thermal instability of underlying materials used. In one aspect, the encapsulating layer includes one or more material layers (multilayer) having one or more barrier layer materials and one or more low-dielectric constant materials. The encapsulating layer thus deposited provides reduced surface roughness, improved water-barrier performance, reduce thermal stress, good step coverage, and can be applied to many substrate types and many substrate sizes. Accordingly, the encapsulating layer thus deposited provides good device lifetime for various display devices, such as OLED devices.

Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

Abstract: Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer.