Using Plasma (epo) Patents (Class 257/E21.311)
  • Patent number: 11276767
    Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in an first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: March 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Kisup Chung, Andrew M. Greene, Sivananda K. Kanakasabapathy, David L. Rath, Indira P. V. Seshadri, Rajasekhar Venigalla
  • Patent number: 11205589
    Abstract: Methods and apparatus for lowering resistivity of a metal line, including: depositing a first metal layer atop a second metal layer to under conditions sufficient to increase a grain size of a metal of the first metal layer; etching the first metal layer to form a metal line with a first line edge roughness and to expose a portion of the second metal layer; removing impurities from the metal line by a hydrogen treatment process; and annealing the metal line at a pressure between 760 Torr and 76,000 Torr to reduce the first line edge roughness.
    Type: Grant
    Filed: October 6, 2019
    Date of Patent: December 21, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: He Ren, Hao Jiang, Mehul Naik, Srinivas D Nemani, Ellie Yieh
  • Patent number: 11158518
    Abstract: A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai, Chung-Ju Lee
  • Patent number: 11054707
    Abstract: A method of manufacturing a via hole, a method of manufacturing an array substrate and an array substrate are provided. The method of manufacturing an via hole includes: providing a base substrate; forming an insulation layer on the base substrate; etching the insulation layer by using a first etching process to forma groove in the insulation layer; performing an ion implantation process with ions on a portion of the insulation layer exposed by the groove to form an ion implantation region; and etching a portion of the insulation layer in the ion implantation region by using a second etching process to form a via hole penetrating the insulation layer.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: July 6, 2021
    Assignees: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Co., Ltd.
    Inventors: Xianxue Duan, Kui Gong
  • Patent number: 10930511
    Abstract: In one example, an electroplating system comprises a first bath reservoir, a second bath reservoir, a clamp, a first anode in the first bath reservoir, a second anode in the second bath reservoir, and a direct current power supply. The first bath reservoir contains a first electrolyte solution that includes an alkaline copper-complexed solution. The second bath reservoir contains a second electrolyte solution that includes an acidic copper plating solution. The direct current power supply generates a first direct current between the clamp and the first anode to electroplate a first copper layer on the cobalt layer of the wafer submerged in the first electrolyte solution. The direct current power supply then generates a second direct current between the clamp and the second anode to electroplate a second copper layer on the first copper layer of the wafer submerged in the second electrolyte solution.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 23, 2021
    Assignee: Lam Research Corporation
    Inventors: Jeyavel Velmurugan, Bryan Buckalew, Thomas Ponnuswamy
  • Patent number: 10707091
    Abstract: A plasma etching method for plasma-etching an object including an etching target film and a patterned mask. The plasma etching method includes a first step of plasma-etching the etching target film using the mask, and a second step of depositing a silicon-containing film using plasma of a silicon-containing gas on at least a part of a side wall of the etching target film etched by the first step.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: July 7, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Keiji Kitagaito, Fumiya Kobayashi, Maju Tomura
  • Patent number: 10658241
    Abstract: A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern, wherein the first pattern includes a first feature and a first jog part protruding from and orthogonal to the first feature. A second reticle is used to form a second pattern, wherein the second pattern includes a second feature, and the first feature is between the second feature and the first jog part. A third reticle is used to form a third pattern, wherein the third pattern includes a third-one feature overlapping the first jog part and a third-two feature overlapping the second feature.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: May 19, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin
  • Patent number: 10648097
    Abstract: In one example, an electroplating system comprises a bath reservoir, a holding device, an anode, a direct current power supply, and a controller. The bath reservoir contains an electrolyte solution. The holding device holds a wafer submerged in the electrolyte solution. The wafer comprises features covered by a cobalt layer. The anode is opposite to the wafer and submerged in the electrolyte solution. The direct current power supply generates a direct current between the holding device and the anode. A combination of forward and reverse pulses is applied between the holding device and the anode to electroplate a copper layer on the cobalt layer of the wafer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 12, 2020
    Assignee: Lam Research Corporation
    Inventors: Jeyavel Velmurugan, Bryan L. Buckalew, Thomas A. Ponnuswamy
  • Patent number: 10580789
    Abstract: A semiconductor device and method of fabricating the same are provided. The semiconductor device includes a substrate having a trench and an etching stop layer. The etching stop layer is disposed in the substrate and surrounds the bottom surface and a portion of a sidewall of the trench.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: March 3, 2020
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chi-Hao Huang, Chin-Cheng Yang
  • Patent number: 10388796
    Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a first conductor over a substrate; a first insulator over the first conductor; an oxide over the first insulator; a second insulator over the oxide; a second conductor over the second insulator; a third insulator over the second conductor; a fourth insulator in contact with a side surface of the second insulator, a side surface of the second conductor, and a side surface of the third insulator; and a fifth insulator in contact with the oxide, the first insulator, and the fourth insulator. The first insulator and the fifth insulator are in contact with each other in a region on the periphery of the side of the oxide. The oxide includes a first region where a channel is formed; a second region adjacent to the first region; a third region adjacent to the second region; and a fourth region adjacent to the third region.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuta Endo, Yoshiaki Oikawa
  • Patent number: 10347712
    Abstract: A method for fabricating semiconductor device includes: forming a metal-oxide semiconductor (MOS) transistor on a substrate; forming a first interlayer dielectric (ILD) layer on the MOS transistor; removing part of the first ILD layer to form a trench adjacent to the MOS transistor; forming a trap rich structure in the trench; forming a second ILD layer on the MOS transistor and the trap rich structure; forming a contact plug in the first ILD layer and the second ILD layer and electrically connected to the MOS transistor; and forming a metal interconnection on the second ILD layer and electrically connected to the contact plug.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: July 9, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Chia-Huei Lin, Kuo-Yuh Yang
  • Patent number: 10332906
    Abstract: A dry etching method includes a process of, while continuously applying bias power using an ion species to a material to be processed including a first conductive member, a first insulating film provided on the first conductive member, a second conductive member provided on the first insulating film, and a second insulating film provided on the second conductive member, dry etching the second insulating film to expose the second conductive member. A time for which the bias power is continuously applied is set to 50 microseconds or less and a duty ratio of the bias power is set to 50% or less.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kaori Narumiya, Hisataka Hayashi, Keisuke Kikutani, Akio Ui, Yosuke Sato
  • Patent number: 10192759
    Abstract: Methods and apparatuses for multiple patterning using image reversal are provided. The methods may include depositing gap-fill ashable hardmasks using a deposition-etch-ash method to fill gaps in a pattern of a semiconductor substrate and eliminating spacer etching steps using a single-etch planarization method. Such methods may be performed for double patterning, multiple patterning, and two dimensional patterning techniques in semiconductor fabrication.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: January 29, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Nader Shamma, Bart J. van Schravendijk, Sirish K. Reddy, Chunhai Ji
  • Patent number: 10012769
    Abstract: An optical element comprising: synthetic diamond material; and an anti-reflective surface pattern formed directly in at least one surface of the synthetic diamond material, wherein the optical element has an absorption coefficient measured at room temperature of ?0.5 cm?1 at a wavelength of 10.6 ?m, wherein the optical element has a reflectance at said at least one surface of no more than 2% at an operating wavelength of the optical element, and wherein the optical element has a laser induced damage threshold meeting one or both of the following characteristics: the laser induced damage threshold is at least 30 Jcm?2 measured using a pulsed laser at a wavelength of 10.6 ?m with a pulse duration of 100 ns and a pulse repetition frequency in a range 1 to 10 Hz; and the laser induced damage threshold is at least 1 MW/cm2 measured using a continuous wave laser at a wavelength of 10.6 ?m.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: July 3, 2018
    Inventors: Daniel Twitchen, Andrew Michael Bennett, Yevgeny Vasilievich Anoikin, Hendrikus Gerardus Maria DeWit
  • Patent number: 9947709
    Abstract: A method to form a stacked CMOS image sensor includes forming a signal processing layer including a plurality of discrete signal processing circuit, an image sensor layer including a plurality of discrete image sensing units, and an intermediate capacitor layer including a dielectric layer and a plurality of capacitors. Each capacitor includes a first electrode, a V-shaped or U-shaped first electrode material layer electrically connecting to the first electrode, a second electrode material layer on the first electrode material layer having the dielectric layer there-between, and a second electrode electrically connecting to the second electrode material layer. The method further includes bonding the signal processing layer to the intermediate capacitor layer with each second electrode electrically connected to a signal processing circuit, and bonding the image sensor layer to the intermediate capacitor layer with each first electrode electrically connected to an image sensing unit.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: April 17, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Herb He Huang, Clifford Ian Drowley, Guan Qie Gao, De Jun Bao
  • Patent number: 9939710
    Abstract: A method includes placing a device having a titanium nitride layer into a chamber. The device also has a mask that includes a photoresist material and an aluminum copper hardmask. The method also includes performing an ashing process on the mask using the chamber. The method further includes, after the ashing process, performing an etching process using the chamber to etch through portions of the titanium nitride layer. Performing the etching process includes flowing a gas mixture containing tetrafluoromethane (CF4) and oxygen gas (O2) into the chamber at a temperature of at least about 200° C.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 10, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Neng Jiang, Joel Soman, Thomas Warren Lassiter, Mary Alyssa Drummond Roby, Nayeemuddin Mohammed, YungShan Chang
  • Patent number: 9809886
    Abstract: A method of machining a nickel containing alloy gas turbine engine component (34) comprises applying a material removal gas comprising gaseous carbon monoxide at a nickel carbonyl gas forming temperature such as 50 to 60° C. to a surface of the component to form a nickel carbonyl gas, and thereby remove a surface layer from at least part of the component.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: November 7, 2017
    Assignee: ROLLS-ROYCE plc
    Inventors: Daniel Clark, Andrew Robert Walpole
  • Patent number: 9799531
    Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: October 24, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Swaminathan T. Srinivasan, Fareen Adeni Khaja, Errol Antonio C. Sanchez, Patrick M. Martin
  • Patent number: 9715192
    Abstract: A semiconductive roller and a method of making the same, wherein the roller includes a conductive support and a semiconductive elastic layer disposed on a circumferential surface of the conductive support, the semiconductive elastic layer containing at least an epichlorohydrin rubber, an acrylonitrile-butadiene rubber and a conducting agent and having a foam structure, wherein, when the semiconductive roller is left to stand in pure water for 30 minutes, the chlorine ion content derived from the semiconductive elastic layer per unit area of the semiconductive elastic layer is approximately not more than 0.06 0.06 ?mol/cm2, wherein a mixing ratio of the epichlorohydrin rubber to the acrylonitrile-butadiene rubber ranges from 80/20 to 20/80 by mass and wherein no electricity has been run through the semiconductive roller prior to being immersed in the pure water.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: July 25, 2017
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Daisuke Tanemura, Toru Ogawa
  • Patent number: 9691807
    Abstract: A semiconductor device includes a substrate, a logic gate structure, a photosensitive gate structure, a hard mask layer, a first spacer, a first source, a first drain, a second spacer, a second source and a second drain. The logic gate structure and the photosensitive gate structure are disposed on a surface of the substrate. The hard mask layer covers the logic gate structure, the photosensitive gate structure and the surface of the substrate. The first spacer overlies the hard mask layer conformal to a sidewall of the logic gate structure. The first source and drain are respectively disposed in the substrate at two opposite sides of the logic gate structure. The second spacer overlies the hard mask layer conformal to a sidewall of the photosensitive gate structure. The second source and drain are respectively disposed in the substrate at two opposite sides of the photosensitive gate structure.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: June 27, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chiao-Chi Wang, Chung-Chuan Tseng, Li-Hsin Chu, Chia-Wei Liu
  • Patent number: 9660181
    Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Kevin J. Lee, Tahir Ghani, Joseph M. Steigerwald, John H. Epple, Yih Wang
  • Patent number: 9620531
    Abstract: A TFT array substrate is disclosed. The TFT array substrate includes a base, a display region disposed on the base, and a gate drive circuit region disposed on the base. The display region includes a plurality of data lines extending along a first direction, and a plurality of scan lines extending along a second direction, the scan lines intersecting and electrically insulated from the data lines. In addition, the gate drive circuit region includes at least one first capacitor, and a plurality of TFTs which are separated from each other to form a margin region between the TFTs, where the first capacitor is disposed in the margin region.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: April 11, 2017
    Assignees: SHANGHAI AVIC OPTOELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Huijun Jin, Yansong Li, Miaomiao Wang
  • Patent number: 9583357
    Abstract: Systems and methods for reverse pulsing are described. One of the methods includes receiving a digital signal having a first state and a second state. The method further includes generating a transformer coupled plasma (TCP) radio frequency (RF) pulsed signal having a high state when the digital signal is in the first state and having a low state when the digital signal is in the second state. The method includes providing the TCP RF pulsed signal to one or more coils of a plasma chamber, generating a bias RF pulsed signal having a low state when the digital signal is in the first state and having a high state when the digital signal is in the second state, and providing the bias RF pulsed signal to a chuck of the plasma chamber.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: February 28, 2017
    Assignee: Lam Research Corporation
    Inventors: Maolin Long, Zhongkui Tan, Ying Wu, Qian Fu, Alex Paterson, John Drewery
  • Patent number: 9570320
    Abstract: A method of opening a barrier film below copper structures in a stack is provided. A pulsed gas is provided into a plasma processing chamber, wherein the providing the pulsed gas comprises providing a pulsed H2 containing gas and providing a pulsed halogen containing gas, wherein the pulsed H2 containing gas and the pulsed halogen containing gas are pulsed out of phase, and wherein the pulsed H2 containing gas has an H2 high flow period and the pulsed halogen containing gas has a halogen containing gas high flow period, wherein the H2 high flow period is greater than the halogen containing gas high flow period. The pulsed gas is formed into a plasma. The copper structures and the barrier film are exposed to the plasma, which etches the barrier film. In another embodiment, a wet and dry cyclical process may be used.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: February 14, 2017
    Assignee: Lam Research Corporation
    Inventors: Meihua Shen, Ji Zhu, Shuogang Huang, Baosuo Zhou, John Hoang, Prithu Sharma, Thorsten Lill
  • Patent number: 9558937
    Abstract: A method of manufacturing a semiconductor device includes: (a) forming a first film containing a metal element on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a first precursor gas being a fluorine-free inorganic gas containing the metal element to the substrate; and (a-2) supplying a first reactant gas having reducibility to the substrate; (b) forming a second film containing the metal element on the first film by performing a cycle a predetermined number of times, the cycle including: (b-1) supplying a second precursor gas containing the metal element and fluorine to the substrate; and (b-2) supplying a second reactant gas having reducibility to the substrate; and (c) forming a film containing the metal element and obtained by the first film and the second film being laminated on the substrate by performing the (a) and (b).
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 31, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kimihiko Nakatani, Kazuhiro Harada, Hiroshi Ashihara, Ryuji Yamamoto
  • Patent number: 9405089
    Abstract: A method includes placing a device having a titanium nitride layer into a chamber. The device also has a mask that includes a photoresist material and an aluminum copper hardmask. The method also includes performing an ashing process on the mask using the chamber. The method further includes, after the ashing process, performing an etching process using the chamber to etch through portions of the titanium nitride layer. Performing the etching process includes flowing a gas mixture containing tetrafluoromethane (CF4) and oxygen gas (O2) into the chamber at a temperature of at least about 200° C.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: August 2, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Neng Jiang, Joel Soman, Thomas Warren Lassiter, Mary Alyssa Drummond Roby, Nayeemuddin Mohammed, YungShan Chang
  • Patent number: 9029228
    Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: May 12, 2015
    Assignees: SunEdision Semiconductor Limited (UEN201334164H), Kansas State University Research Foundation
    Inventors: Michael R. Seacrist, Vikas Berry, Phong Tuan Nguyen
  • Patent number: 9018102
    Abstract: When performing plasma assisted etch processes for patterning complex metallization systems of microstructure devices, the probability of creating plasma-induced damage, such as arcing, may be reduced or substantially eliminated by using a superior ramp-up system for the high frequency power and the low frequency power. To this end, the high frequency power may be increased at a higher rate compared to the low frequency power component, wherein, additionally, a time delay may be applied so that, at any rate, the high frequency component reaches its target power level prior to the low frequency component.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: April 28, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mohammed Radwan, Matthias Zinke
  • Patent number: 8999811
    Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda, Mizuho Sato
  • Patent number: 8993411
    Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, filling one or more metals in the vias and the defined space for the pad, and removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.
    Type: Grant
    Filed: February 23, 2013
    Date of Patent: March 31, 2015
    Assignee: Siliconfile Technologies Inc.
    Inventors: Heui-Gyun Ahn, Se-Jung Oh, In-Gyun Jeon, Jun-Ho Won
  • Patent number: 8927433
    Abstract: Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: January 6, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Jin-Yeong Kang
  • Patent number: 8895446
    Abstract: A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Hao-Ming Lien
  • Patent number: 8884377
    Abstract: In one embodiment, first and second pattern structures respectively include first and second conductive line patterns and first and second hard masks sequentially stacked, and at least portions thereof extends in a first direction. The insulation layer patterns contact end portions of the first and second pattern structures. The first pattern structure and a first insulation layer pattern of the insulation layer patterns form a first closed curve shape in plan view, and the second pattern structure and a second insulation layer pattern of the insulation layer patterns form a second closed curve shape in plan view. The insulating interlayer covers upper portions of the first and second pattern structures and the insulation layer patterns, a first air gap between the first and second pattern structures, and a second air gap between the insulation layer patterns.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sok-Won Lee, Joon-Hee Lee, Jung-Dal Choi, Seong-Min Jo
  • Patent number: 8884407
    Abstract: A device includes a tube extending in a longitudinal direction and a hollow channel arranged in the tube. An end part of the tube is formed such that first electromagnetic radiation paths extending in the tube and outside of the hollow channel in the longitudinal direction are focused in a first focus.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies AG
    Inventors: Michael Sternad, Rainer Pelzer
  • Patent number: 8859331
    Abstract: Methods of forming an oxide material layer are provided. The method includes mixing a precursor material with a peroxide material to form a precursor solution, coating the precursor solution on a substrate, and baking the coated precursor solution.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: October 14, 2014
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyun Jae Kim, Dong Lim Kim, Joohye Jung, You Seung Rim
  • Patent number: 8853757
    Abstract: Embodiments of an apparatus and methods for forming thick metal interconnect structures for integrated structures are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: October 7, 2014
    Assignee: Intel Corporation
    Inventor: Kevin Lee
  • Patent number: 8835247
    Abstract: A sensor array for detecting particles, the sensor array comprising a substrate having a plurality of holes, a plurality of electronic sensor chips each having a sensor active region being sensitive to the presence of particles to be detected, and an electric contacting structure adapted for electrically contacting the plurality of electronic sensor chips, wherein the plurality of electronic sensor chips and/or the electric contacting structure are connected to the substrate in such a manner that the plurality of holes in combination with the plurality of electronic sensor chips and/or the electric contacting structure form a plurality of wells with integrated particle sensors.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: September 16, 2014
    Assignee: NXP, B.V.
    Inventors: Michel De Langen, Ger Reuvers, Frans Meeuwsen
  • Patent number: 8809132
    Abstract: A capping layer may be deposited over the active channel of a thin film transistor (TFT) in order to protect the active channel from contamination. The capping layer may affect the performance of the TFT. If the capping layer contains too much hydrogen, nitrogen, or oxygen, the threshold voltage, sub threshold slope, and mobility of the TFT may be negatively impacted. By controlling the ratio of the flow rates of the nitrogen, oxygen, and hydrogen containing gases, the performance of the TFT may be optimized. Additionally, the power density, capping layer deposition pressure, and the temperature may also be controlled to optimize the TFT performance.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: August 19, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Patent number: 8796131
    Abstract: An ion implantation system and method, providing cooling of dopant gas in the dopant gas feed line, to combat heating and decomposition of the dopant gas by arc chamber heat generation, e.g., using boron source materials such as B2F4 or other alternatives to BF3. Various arc chamber thermal management arrangements are described, as well as modification of plasma properties, specific flow arrangements, cleaning processes, power management, eqillibrium shifting, optimization of extraction optics, detection of deposits in flow passages, and source life optimization, to achieve efficient operation of the ion implantation system.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: August 5, 2014
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Edward E. Jones, Sharad N. Yedave, Ying Tang, Barry Lewis Chambers, Robert Kaim, Joseph D. Sweeney, Oleg Byl, Peng Zou
  • Patent number: 8779479
    Abstract: An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode. The second source electrode and the second drain electrode include an oxide region formed by oxidizing a side surface thereof, and at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8772173
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a gate structure, a source region, and a drain region formed thereon, and the gate structure includes a gate insulating layer and a gate electrode. The method also includes forming a first stress layer on the substrate, removing the first stress layer, and forming a second stress layer on the substrate.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-kwan Yu, Dong-suk Shin, Pan-kwi Park, Ki-eun Kim
  • Patent number: 8772826
    Abstract: It is an object to provide a photoelectric conversion device with high photoelectric conversion efficiency. The photoelectric conversion device includes an electrode layer, and a light absorbing layer located on the electrode layer. The light absorbing layer is comprised of a plurality of stacked semiconductor layers containing a chalcopyrite-based compound semiconductor. The semiconductor layers contain oxygen. A molar concentration of the oxygen in surfaces and their vicinities of the semiconductor layers where the semiconductor layers are stacked on each other is higher than average molar concentrations of the oxygen in the semiconductor layers.
    Type: Grant
    Filed: May 30, 2011
    Date of Patent: July 8, 2014
    Assignee: KYOCERA Corporation
    Inventors: Hideaki Asao, Rui Kamada, Shuichi Kasai, Seiji Oguri, Isamu Tanaka, Nobuyuki Horiuchi, Kazumasa Umesato
  • Patent number: 8765608
    Abstract: Methods for making a semiconductor device are disclosed. The method includes forming a plurality of gate stacks on a substrate, forming an etch buffer layer on the substrate, forming a dielectric material layer on the etch buffer layer, forming a hard mask layer on the substrate, wherein the hard mask layer includes one opening, and etching the dielectric material layer to form a plurality of trenches using the hard mask layer and the etch buffer layer as an etch mask.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ya Hui Chang
  • Patent number: 8753985
    Abstract: Molecular layer deposition of silicon carbide is described. A deposition precursor includes a precursor molecule which contains silicon, carbon and hydrogen. Exposure of a surface to the precursor molecule results in self-limited growth of a single layer. Though the growth is self-limited, the thickness deposited during each cycle of molecular layer deposition involves multiple “atomic” layers and so each cycle may deposit thicknesses greater than typically found during atomic layer depositions. Precursor effluents are removed from the substrate processing region and then the surface is irradiated before exposing the layer to the deposition precursor again.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 17, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Brian Underwood, Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 8741702
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by dry etching in which an etching gas is used, and a second etching step is performed by wet etching in which an etchant is used.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunichi Ito, Miyuki Hosoba, Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka
  • Patent number: 8742544
    Abstract: A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8735302
    Abstract: Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: May 27, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Amol Joshi, John Foster, Zhendong Hong, Olov Karlsson, Bei Li, Usha Raghuram
  • Patent number: 8722547
    Abstract: Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: May 13, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Radhika Mani, Nicolas Gani, Wei Liu, Meihua Shen, Shashank C. Deshmukh
  • Patent number: 8723340
    Abstract: The present invention relates to a process for the production of solar cells comprising a selective emitter using an improved etching-paste composition which has significantly improved selectivity for silicon layers.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: May 13, 2014
    Assignee: Merck Patent GmbH
    Inventors: Werner Stockum, Oliver Doll, Ingo Koehler
  • Patent number: 8716149
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: May 6, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Fabian Koehler, Sergej Mutas, Dina Triyoso, Itasham Hussain