Abstract: A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In another embodiment, the probe region (14) extends over a passivation layer (18). In an application requiring very fine pitch between bond pads, the probe regions (14) and wire bond regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.

Abstract: A chip mounting substrate for bonding a semiconductor chip to a substrate, comprises a solder layer on the substrate, the solder layer being connectable to a semiconductor chip, wherein the solder layer comprises a layer including ?-phase crystal grains of an Au—Sn alloy at a surface of the solder layer. The solder layer comprising a layer including ?-phase crystal grains of an Au—Sn alloy is formed at a surface of the solder layer. On mounting a semiconductor chip on the substrate, the substrate and the solder layer are heated and an image of the solder layer is shot to perform an image evaluation to detect the timing of mounting the semiconductor chip on the solder layer of the substrate and a position of the chip.

Abstract: A method and apparatus for processing a semiconductor wafer is provided for reducing dimensional variation by feeding forward information relating to photoresist mask CD and profile and underlying layer thickness measured at several points on the wafer to adjust the next process the inspected wafer will undergo (e.g., the etch process). After the processing step, dimensions of a structure formed by the process, such as the CD and depth of a trench formed by the process, are measured at several points on the wafer, and this information is fed back to the process tool to adjust the process for the next wafer to further reduce dimensional variation. In certain embodiments, the CD, profile, thickness and depth measurements, etch processing and post-etch cleaning are performed at a single module in a controlled environment.

Abstract: A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a component of an integrated circuit device, the resistance defect assessment device including test patterns capable of measuring a resistance variation component to be the resistance variation defect in each chip area or each shot area of the wafer, wherein the number of test patterns included in one chip area or one shot area is set so that it is possible to estimate the yield of the integrated circuit device.

Abstract: It is an object of the present invention to provide a doping apparatus, a doping method, and a method for fabricating a thin film transistor that can carry out doping to the carrier concentration which is optimum for obtaining the desired electric characteristic non-destructively and in an easy manner. In accordance with the present invention, an electric characteristic of a semiconductor element (threshold voltage in a transistor and the like) is correctly and precisely monitored by using a contact angle, and is controlled by controlling a doping method. In addition, the present invention can be momentarily acquired information by in-situ monitoring the characteristic and can be fed back without a time lag.

Abstract: A semiconductor element and a circuit substrate each having electrodes disposed at narrow pitch are electrically connected with high reliability by conductive paste. A semiconductor device with a semiconductor section and a circuit substrate electrically connected and a method for manufacturing such semiconductor device are provided. The manufacturing method includes processes of: forming semiconductor electrodes at the semiconductor section; forming substrate electrodes at the circuit substrate; firstly affixing one part of the semiconductor section and circuit substrate to an intermediate connector made of insulating material; forming via holes at intermediate connector according to positions of the semiconductor electrodes and positions of the substrate electrodes; electrically connecting each semiconductor electrode and each substrate electrode via each via hole; and secondly affixing the other part of the semiconductor section and circuit substrate to the intermediate connector.

Abstract: An apparatus includes semiconductor processing equipment. A particle detecting integrated circuit is positioned in a vacuum environment, the particle detecting integrated circuit containing a device having a pair of conductive lines exposed to the vacuum environment. The pair of conductive lines is spaced at a critical pitch corresponding to diameters of particles of interest. A computer system is linked to the particle detecting integrated circuit to detect a change in an electrical property of the conductive lines when a particle becomes lodged between or on the lines.

Abstract: In a method of manufacturing a semiconductor device, a semiconductor wafer is prepared that includes a plurality of IC chips, each having a circuit including a terminal for applying an electrical quantity to the circuit, and a switch electrically connected to the terminal. A wire is formed between adjacent IC chips to provide a parallel or series electrical connection between the terminals of the IC chips via the switch. A test is performed to determine the operability (defective or non-defective) of each of the IC chips. The switch is then operated to provide an electrical connection between the terminals of only those IC chips that were determined to not be defective and the wire. A conduction test is performed on the circuits of the IC chips through the wire.

Abstract: The invention relates to a method for enabling repair of a defect in a substrate, particularly the invention provides a method and apparatus for enabling repair of a pattern shape in a semiconductor device, which has not been able to be practiced because of lack of a suitable method, and further provides a method for manufacturing the semiconductor device using those. A method for repairing the pattern shape of a substrate having an imperfect pattern is used, which includes (a) a step for inspecting the substrate and thus detecting the imperfect pattern, and (b) a step for repairing the pattern shape by performing etching or deposition to the detected imperfect-pattern using radiation rays. Moreover, apparatus for repairing a pattern shape of a via-hole in a wafer having an imperfect via-hole is used, which has a defect inspection section for detecting the imperfect via-hole, and an etching section for etching the imperfect via-hole using a fast atom beam.

Abstract: A method for marking a semiconductor wafer 302 includes the steps of: providing a reticle 300 including liquid crystal pixels; positioning the semiconductor wafer in proximity to the reticle; directing radiation through a first plurality of the pixels onto a first location on the wafer; changing the relative positions of the semiconductor wafer and the reticle; and directing radiation through a second plurality of the pixels onto a second location on the wafer. The first plurality of pixels can be used to form a first mark and the second plurality of pixels can be used to form a second mark, wherein the second mark is different from the first mark. The marks can be made of a pattern of dots in order to save space. The pixels can be selected to form certain marks by using a computer 304 to turn on or off a transistor that may be associated with each pixel. Also described is a system for marking a semiconductor wafer.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: A method for forming a multi-level semiconductor device to eliminate conductive interconnect protrusions following a WAT test, the method including forming a first metallization layer; carrying out a wafer acceptance testing (WAT) process; and, then carrying out a chemical mechanical polish (CMP) on the metallization layer.

Abstract: Dice on a wafer are selected to be tested using a yield map. The yield map incorporates yield information of different products produced by the same fabrication process. A die placement for a product to be produced by the same process is determined based on the yield map. An expected yield for a die in the die placement is also determined based on the yield map. The expected yield for the die is then used to determine whether to test the die.

Abstract: A correcting device that properly maintains the flatness of a mask, an exposure apparatus in which overlay accuracy is increased by making use of the correcting device, and a device production method. The correcting device includes a gas flow path including a first area and a second area. The first area is formed above a reticle having formed thereon a pattern that is projected onto a material to be processed in order to form an image of the pattern on the material to be processed. The second area is connected to the first area, has a cross-sectional area that is different from that of the first area, and is not disposed in line with the reticle. The correcting device also includes a blowing section that blows gas to the gas flow path.

Abstract: A wall film monitoring system includes first and second microwave mirrors in a plasma processing chamber each having a concave surface. The concave surface of the second mirror is oriented opposite the concave surface of the first mirror. A power source is coupled to the first mirror and configured to produce a microwave signal. A detector is coupled to at least one of the first mirror and the second mirror and configured to measure a vacuum resonance voltage of the microwave signal. A control system is connected to the detector that compares a first measured voltage and a second measured voltage and determines whether the second voltage exceeds a threshold value. A method of monitoring wall film in a plasma chamber includes loading a wafer in the chamber, setting a frequency of a microwave signal output to a resonance frequency, and measuring a first vacuum resonance voltage of the microwave signal.

Abstract: A method and system are provided for identifying systematic yield losses. The method comprising testing produced products using a test sequence, the testing sequence producing yield data, the yield data related to a wafer. For each zone of each wafer size calculating and storing a first data series R1, wherein each element of said first series is the yield of a said zone. Further calculating and storing for each element of R1 a second data series R2, wherein each element of the second series is a p consecutive element moving average of R1. Calculating and storing for each element of R1 a third data series R3 wherein each element of the third data series a p consecutive element moving standard deviation of data series R1. Calculating for each element of R1 a trigger point, wherein the trigger point is calculated as the respective R2 element less an adjusted respective R3 value. A notification is triggered when the trigger point calculated for each element of R1 is greater than the respective element of R1.

Abstract: A method for identifying faults in a semiconductor fabrication process includes storing measurements for a plurality of parameters of a wafer in the semiconductor fabrication process. A first subset of the parameters is selected. The subset is associated with a feature formed on the wafer. A principal component analysis model is applied to the first subset to generate a performance metric. A fault condition with the wafer is identified based on the performance metric. A system includes a data store and a fault monitor. The data store is adapted to store measurements for a plurality of parameters of a wafer in a semiconductor fabrication process. The fault monitor is adapted to select a first subset of the parameters, the subset being associated with a feature formed on the wafer, apply a principal component analysis model to the first subset to generate a performance metric, and identify a fault condition with the wafer based on the performance metric.

Abstract: A stackable neo-layer comprising one or more embedded discrete electrical components is provided. A plurality of conductive traces, some of which terminate at a peripheral edge of the layer, are formed on sacrificial substrate in a series of process steps and discrete electrical components such as thick film components or wire bonded components are attached thereto. An under-bump metal process step is disclosed and provides for solder attachment at desired contact pad locations. The layer is encapsulated in a potting material and thinned to provide a thin, stackable layer. When assembled into a stack of layers, the electrically conductive traces terminating at the edge of the layer can be electrically connected by means of electroplating using a T-connect.

Abstract: A cleaning method for use in an apparatus for manufacturing a semiconductor device includes: measuring components and concentration of each component of gas in a process chamber of an apparatus for manufacturing a semiconductor device, or selected from a group including gas in the chamber, a process gas in a gas inlet pipe, and gas in a gas outlet pipe; performing a prescribed process on a substrate in the chamber, while adjusting the components and the concentration of each component of the process gas, and of an atmosphere in the chamber, on the basis of the values measured, and taking the substrate from the chamber after the process is subjected; and generating and applying a cleaning gas on the basis of the values measured, the cleaning gas having such components and such concentration as to remove residues.

Abstract: A method of inspecting a leakage current of a dielectric layer on a substrate including a cell array region having a plurality of cell blocks including a patterned structure, the dielectric layer formed on the patterned structure, and a peripheral circuit region includes depositing a corona ion charge on a cell block selected from the plurality of cell blocks and measuring a variance of a surface voltage caused by a leakage current through the dielectric layer on the selected cell block. The variance of the surface voltage is compared with reference data to determine a leakage current characteristic of the dielectric layer.

Abstract: Nano-machining for circuit edits through the front side or backside of an integrated circuit may be performed using a scanning probe system. The system may create access holes with smaller dimensions and facilitate nano-machining endpoint detection in some embodiments.

Abstract: A domed plasma reactor chamber uses an antenna driven by RF energy which is inductively coupled inside the reactor dome. The antenna generates a high density, low energy plasma inside the chamber for etching metals, dielectrics and semiconductor materials. Auxiliary RF bias energy applied to the wafer support cathode controls the cathode sheath voltage and controls the ion energy independent of density. The RF energy inductively coupled to the dome creates a heat that must be moderated. The invention herein utilizes a temperature-controlled airflow to supply a continuously variable air temperature over a wide range of process conditions including idling.

Abstract: A method of testing a test wafer includes shielding test centers on a test wafer using shielding tabs during the deposition of a layer. The test wafer has the same size and shape of product wafers. The shielding tabs are then removed from the test wafer. A plurality of predetermined points which are separated from each test center by a critical interval are checked, and whether each point is covered by the layer is determined through an interferometer or a microprobe. The test wafer is processed after adjustments to or maintenance on equipment, or after a fixed number of product wafers have been processed.

Abstract: The present invention discloses novel methods to transfer data between a plurality of integrated circuit dice on a semiconductor wafer. Each individual die contains internal circuits to control data transfer to nearby dice. Wafer level data transfer is achieved by a series of inter-dice data transfers. It is therefore possible to use a small number of small area metal lines to support wafer level parallel processing activities. External connections are provided by a small number of bonding pads on each wafer. The load on each external bounding pad is by far lower than that of prior art wafer level connections. These inter-dice data transfer mechanism also can be programmed to avoid defective circuitry. This invention has been used to support wafer level functional tests and wafer level burn-in tests. A Testing system of the present invention can test thousands of dice in parallel using simple testing equipment. Testing costs for integrated circuits are therefore reduced dramatically.

Abstract: In fabricating a semiconductor laser producing light with a wavelength of 770 to 810 nm, impurities are introduced into an MQW active layer near a light emitting facet of the laser to form a disordered region constituting a window layer. Pump light is applied to the window layer to generate photoluminescence whose wavelength ? dpl (nm) is measured. A blue shift amount ? bl (nm) is defined as the difference between the wavelength ? apl (nm) 0f photoluminescence generated by application of pump light to the active layer on the one hand, and the wavelength ? dpl (nm) of photoluminescence from the window layer under pump light irradiation on the other hand. The blue shift amount ? bl is referenced during the fabrication process in order to predict catastrophic optical damage levels of semiconductor lasers.

Abstract: A semiconductor wafer test system for carrying out a burn-in test on a semiconductor wafer including multiple semiconductor devices thereon. A metal interconnect is connected to the gate electrode of each of those devices. A power supply applies an ac voltage of predetermined amplitude to a conductive plate, which creates an ac electric field to be placed on the devices. The ac field should have an intensity at least equal to a minimum value required for the burn-in test and less than a critical value, below which no break-down occurs in the gate oxide film of each device. By changing the amount of time for which the devices are exposed to the ac field, the burn-in period can be changed freely. In addition, forward and reverse fields are both placed on the gate oxide film of each device. Thus, failures can be screened out very effectively.

Abstract: A process for manufacturing a plurality of leadless semiconductor packages includes an electrically testing step to test encapsulated chips in a matrix of a leadless leadframe. Firstly, a leadless leadframe having at least a packaging matrix is provided. The packaging matrix defines a plurality of units and a plurality of cutting streets between the units. The leadless leadframe has a plurality of leads in the units and a plurality of connecting bars connecting the leads along the cutting streets. A plated metal layer is formed on the upper surfaces of the leads and the upper surfaces of the connecting bars. After die-attaching, wire-bonding connection, and encapsulation, the leadless leadframe is etched to remove the connecting bars, then two sawing steps are performed. During the first sawing step, the plated metal layer on the upper surface of the connecting bars is cut out to electrically isolate the leads.

Abstract: A test point on a printed circuit board includes at least one connection to the power plane having first and second interconnected pads disposed on opposing sides of the power plane, and at least one connection to the ground plane having third and fourth interconnected pads disposed on opposing sides of the ground plane. The first and second interconnected pads provide parallel paths to the power plane, thereby reducing the impedance presented to test equipment. Similarly, The third and fourth interconnected pads provide parallel paths to the ground plane. The test point may be implemented with multiple ground plane connections disposed symmetrically around a power plane connection. For example, first and second ground plane connections may be disposed on opposing sides of a power plane connection to provide shielding to the power plane connection, thereby reducing the inductive loop associated with probe parasitics.

Abstract: A method of protecting a bond pad during die-sawing comprising the following steps. A substrate having a bond pad formed thereover is provided. A bond pad protection layer is formed over the bond pad. The substrate is die-sawed and the bond pad protection layer is removed by heating.

Abstract: A test key formed on a semiconductor substrate has a plurality of electronic components, a plurality of conductors, a plurality of vias for connecting the electronic components and the conductors, a first pad, a second pad, a third pad, and a fourth pad. The first pad, the electronic components, the vias, the conductors, and the second pad connects in series to form a chain circuit, and the first pad and the second pad are positioned at two ends of the chain circuit. A Kelvin structure is composed of the third pad, the fourth pad, one of the conductors, one of the vias, and one of the electronic components.

Abstract: A semiconductor package (101) has a die (1), a leadframe (4), a bond pad (6), an encapsulation (3) and a wire bond ball (2). The wire bond ball is formed on the bond pad by bonding one end of a bond wire (7), and remainder of the bond wire is removed. Locations (23) for attaching the wire bond ball are recorded with reference to fiducials (5) on the lead frame. The encapsulation covers the die, deposits and die attach flag (24) of the lead frame. The wire bond ball is exposed where the encapsulation is removed. The locations for making openings (17) for exposing the wire bond ball is determined by recorded coordinates when the wire bond ball is formed. Exposed wire bond ball is plated, forming a lead to electrically connect to the die.

Abstract: In a method of and apparatus for controlling probe tip sanding in semiconductor device testing equipment, resistance values of pads of a probed chip are measured and stored. If a maximum resistance value among the stored resistance values is greater than a contact resistance reference value, a consecutive fail counting value and an accumulated fail counting value are increased. An automatic sanding command is generated to activate automatic sanding of a probe tip, when at least one of the consecutive fail counting value and the accumulated fail counting value is greater than a respective counting reference value. In this manner, false negative readings in the testing of semiconductor devices as the result of increased contact resistance between a probe tip and a pad in an EDS test are reduced and therefore device yield is improved.

Abstract: An inspection pattern, an inspection method, and an inspection system for detection of a latent defect of a multi-layer wiring structure formed on the semiconductor wafer. The inspection pattern includes lower-layer wiring portions, upper-layer wiring portions, an insulating layer provided between them, contact units connecting them to form a contact chain, and electrode terminals. The inspection method includes the steps of acquiring an applied-voltage versus measured-current characteristic or an elapsed-time versus measured-voltage characteristic of the inspection pattern, and judging presence or absence of a latent defect of the inspection pattern on the basis of the acquired characteristic. The inspection system includes a voltage-applying/current-measuring device or a constant-current-feeding/voltage-measuring device, and a judging device for judging presence or absence of a latent defect of the inspection pattern.

Abstract: A method of defect review. First, a wafer with a plurality of defects is provided. A defect inspection is performed to detect the defects. An automatic defect classification is then performed to divide the defects into different defect types according to a predetermined database. A defect review is performed to review different defect types of defects which are sampled in different weights according to yield killing ratios of each defect types.

Abstract: An apparatus for measuring a gate oxide thickness comprises a first active area, first to fifth wordlines, first and second bar-shaped trench capacitors, and first and second gate structures. The first active area with a width of at least 2F is disposed on a substrate. The first to fifth wordline is disposed on the substrate in a first direction, with a first predetermined space between each two wordlines, and first ends of the first to fifth wordlines are electrically connected. The first and second bar-shaped trench capacitors are disposed under the second and the fourth wordlines respectively with a second predetermined space between the first and second bar-shaped trench capacitors, and F is a minimum line width of the wordlines. The first and second gate structure are respectively disposed between the first bar-shaped trench capacitor and the second wordline and between the second bar-shaped trench capacitor and the fourth wordline.

Abstract: A method of testing ion implantation equipment verifies the level of ion implantation energy. The method includes implanting first conductive ions in an implantation region in a semiconductor substrate, implanting second conductive ions, having valence different from that of the first conductive ions, in the implantation region so as to produce a second well, and subsequently measuring a sheet resistance of the semiconductor substrate. The implanting of the second conductive ions may be carried out while varying the level of the ion implantation energy. By forming a twin well in this way, and then measuring the sheet resistance, the value of the sheet resistance can be precisely correlated to the amount of energy used to form a well.

Abstract: A device for seating a semiconductor device in a semiconductor test handler is provided. The device includes a plate having a plurality of device seating members each for seating the semiconductor device. The device also includes a latch rotatably mounted to one side of the device seating member for pressing down or freeing the semiconductor device seated on the device seating member. A latch operating means for causing the latch to press down the semiconductor device when the semiconductor device is seated on the device seating member is also included. The provided device also releases the pressing down action when the semiconductor device is seated on the device seating member and when the semiconductor device is taken away from the device seating member, thereby seating the semiconductor device on the device seating device accurately and positively.

Abstract: A semiconductor automation system for a daily check is provided. The semiconductor automation system includes a database for storing testing items, testing specifications, and testing frequencies for each semiconductor equipment; a processor for selecting a corresponding testing specification from the database to perform real time calculation on newly added testing data, thus getting a testing result; and a message server for alarming engineers associated with the daily check when the testing result is abnormal.

Abstract: Backgate-characteristics determination method and device that make for curtailing the fabrication of semiconductor circuit elements having defective backgate-characteristics. Initially a first C-V curve 30 representing the relation between a voltage applied to the obverse face of a wafer 20 serving as a substrate for semiconductor circuit elements, and its capacitance, is found. Next, a second C-V curve 32 is found through applying a voltage to the reverse face of the wafer 20. The backgate characteristics for the semiconductor circuit elements are determined based on a voltage-shift amount 34 for the wafer 20, found from the first C-V curve 30 and the second C-V curve 32.