Abstract: Techniques for testing a semiconductor wafer are disclosed. One technique includes measuring a parameter for each of the semiconductor dies in a region of the wafer and determining an adaptive threshold for the region based on the measured parameters. The parameter measured for each die in the region is then compared to the adaptive threshold to determine a qualification status for each die. Accordingly, the semiconductor dies of the wafer are qualified based on an adaptive threshold that varies according to the wafer region under test. This allows for detection of dies whose parameters vary significantly from other dies in a region, providing for detection of potentially faulty dies whose parameter measurements otherwise meet a fixed threshold set for the entire wafer, such as a Single Threshold Test Limit (STL) expectation for the wafer.

Abstract: A semiconductor package is disclosed having a single CE signal during electrical test and a plurality of CE signals during normal operation thereafter. After electrical testing of the memory die during fabrication, the electrical traces carrying the single CE signal from the memory test pad matrix to each of the memory die may be severed. Severing the electrical traces from the memory test pad matrix electrically isolates the multiple electrical traces between the controller die and memory die, and allows separate and individual CE signals between the controller die and memory die during normal usage of the memory die.

Abstract: During the patterning of stressed layers having different types of intrinsic stress, the effects of the deposition of a silicon dioxide based etch indicator material between the first and second dielectric layers may be significantly reduced by a controlled etch on the basis of optical measurement data indicating the etch rate and, thus, the performance of the respective etch process. In other cases, highly efficient etch indicator species may be incorporated into the stressed dielectric layers or may be formed on a surface portion thereof with reduced layer thickness, thereby providing an enhanced endpoint detection signal without creating the negative effects of silicon dioxide based indicator layers. In one illustrative embodiment, a stressed silicon, nitrogen and carbon-containing layer may be combined with a stressed silicon and nitrogen-containing layer, wherein the carbon species provides a prominent endpoint detection signal.

Abstract: Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line, a stress line disposed proximate the feed line, and a conductive feature disposed between the stress line and the feed line. The test structure includes a temperature adjuster proximate at least the conductive feature, and at least one feedback device coupled to the temperature adjuster and at least the conductive feature.

Abstract: A substrate is disposed within a processing chamber. A nitrogen precursor and a group-III precursor are flowed into the processing chamber. A layer is deposited over the substrate with a thermal chemical-vapor-deposition process at an elevated temperature within the processing chamber using the nitrogen precursor and the group-III precursor. Light beams are directed to a surface of the layer and light spots corresponding to reflections of the light beams are received from the surface at a position-sensitive detector. Positions of the light spots on the position-sensitive detector are determined from photocurrent induced in a photodiode in the position-sensitive detector. A curvature of the layer is determined from the positions of the light spots.

Abstract: A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.

Abstract: An integrated circuit arrangement has a signal input 20 and a signal output 60, a signal processing unit 100 which is connected to the signal input 20 and to the signal output 60, a noise source 50 for generating a noise signal, and a noise line 55 which connects the noise source 50 to the signal input 20.

Abstract: The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first transistor having its source connected to a first terminal, wherein the first terminal connects a supply voltage to the source of the first transistor; a register connected to the drain of the first transistor; and a second transistor in parallel with a resistor, the gate of the second transistor is connected to an output of the register and a source of the second transistor is connected to the first terminal. In various embodiments, the drain of the second transistor is connected to a second terminal and the state of the second transistor depends on whether the register is loaded.

Abstract: According to one exemplary embodiment, a method for determining a power spectral density of an edge of at least one patterned feature situated over a semiconductor wafer includes measuring the edge of the at least one patterned feature at a number of points on the edge. The method further includes determining an autoregressive estimation of the edge of the at least one patterned feature using measured data corresponding to a number of points on the edge. The method further includes determining a power spectral density of the edge using autoregressive coefficients from the autoregressive estimation. The method further includes utilizing the power spectral density to characterize line edge roughness of the at least one patterned feature in a frequency domain.

Abstract: Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line yet spaced apart from the feed line. The stress line is coupled to the feed line by a conductive feature disposed in at least one second conductive material layer proximate the first conductive material layer.

Abstract: A flexible printed circuit (FPC) having testing pads thereon is provided. The FPC comprises a plurality of bonding pads and a plurality of testing pads, wherein each of the testing pads is disposed corresponding to each of the bonding pads, and the testing pads are electrically isolated from the bonding pads. After the bonding pads of the FPC are bonded to pins of a display, the testing pads are electrically connected to the bonding pads on the FPC via the pins of the display. Therefore, the FPC bonding yield can be determined by measuring the electrical property of the testing pads.

Abstract: The invention provides an inspection apparatus and an inspection method for detecting defects, a punching apparatus, and a method for controlling a punching apparatus, for the purpose of immediate detection of debris from being lifted toward the surface of an insulating film for film carrier tape, which debris tends to occur during punching of the insulating film for film carrier tape by use of a punching mold, whereby the number of pieces having defects on the film surface caused by attachment of debris from being lifted or foreign matter is reduced to a minimum possible number.

Abstract: A method of in-line characterization of ion implant process, during the SOI bond and cleave manufacturing or engineered silicon layer fabrication. In one embodiment, the method includes the steps of illuminating the engineered donor wafer using a modulated light source; performing a non-contact SPV measurement on the silicon wafer; measuring a dynamic charge (Qd) in response to implant induced crystal damage; and determining the accuracy and uniformity of the value of an implant parameter in response to the dynamic charge. In another embodiment, In another embodiment, the step of determining utilizes the equation VPV?kT?/?Qnet where VPV is photo voltage generated in the implanted wafer, ? is a light flux of the modulated light source, T is temperature of the wafer, and ? is a light modulation frequency of the modulated light source.

Abstract: A method and system determines deformations in a substrate in the manufacturing of semiconductor devices. At least one property of vertical deformations of the substrate is measured at a plurality of locations on the substrate. Afterward, an automatic computation of horizontal deformations is determined based on the measured properties of vertical deformations with a model for the deformation behavior of the substrate.

Abstract: In order to measure a surface profile of a sample, an imprint of the surface profile to be examined is produced in a transfer material. The sample contains processed semiconductor material and is in particular a patterned semiconductor wafer or part of a patterned semiconductor wafer. The transfer material is deformable and curable under suitable ambient conditions. The transfer material may be a thermoplastic material or a material which is deformable as desired after application on a substrate and cures in one case by means of irradiation with photons having a suitable wavelength or alternatively heating. The transfer material may be configured in such a way that the imprint produced is the same size as or alternatively of smaller size than the surface profile. The imprint produced is subsequently measured by known methods.

Abstract: The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

Abstract: A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.

Abstract: A method for thinning a semiconductor wafer, the method includes selecting a semiconductor wafer having a buried stop layer; and planarizing the semiconductor wafer to the buried stop layer to produce a thin semiconductor wafer.

Abstract: A method of manufacturing a semiconductor device using a wafer emissivity calculated from a wafer reflectivity to calculate a wafer temperature and to calculate target values for heat source optical intensities provided to a plurality of heat sources which heat the wafer and a substrate peripheral structure.

Abstract: A method of providing a family of integrated circuits (ICs) includes applying a first product selection code (PSC) to a first IC die, applying a second PSC to a second IC die, and providing a third packaged IC die. The first IC die includes first and second portions, both of which are operational based on the first PSC. The second IC die is a duplicate of the first die, but the second portion is rendered non-operational by the second PSC. The third IC die is substantially similar to the first portion of the first die. The second and third packages can be the same and the packaged dies can be interchangeable in a system. When the dies are programmable logic device (PLD) dies, the second and third dies use the same configuration bit stream, which may be smaller than the configuration bit stream for the first IC die.

Abstract: Detection of a profile drift of a polysilicon line is enhanced by a test structure that (1) measures a bottom width and an average width of a cross sectional area of the same polysilicon line (2) correlates the two measurements, and (3) compares such correlation with a previous correlation of bottom width to average width of cross sectional area of the same polysilicon line.

Abstract: Disclosed herein are systems and methods for stacking passive component devices on a substrate. A conductive material is printed onto a first substrate using a fluid ejection device to form a printed passive device according to a predetermined design. The first substrate is attached to a second substrate, such as a die, to form a component for performing a predetermined function. The component may then be tested to determine whether the component formed according to the predetermined design performs the predetermined function. The design may be adjusted in response to the test to improve the performance of the component in performing the predetermined function. Multiple substrates having printed passive devices may be stacked and electrically connected to the die or other substrate in order to increase the number of devices formed on a particular area of that die or other substrate.

Abstract: By evaluating a status signal on the basis of a fault detection classification mechanism in an electrochemical etch tool, a corresponding failure status of the tool may be obtained for each single substrate, thereby significantly reducing the risk of significant yield loss compared to conventional strategies. The fault detection and classification mechanism may be advantageously applied to the electrochemical removal of underbump metallization layers during the formation of solder bump structures.

Abstract: A method comprises providing a semiconductor structure. The semiconductor structure comprises a feature comprising a first material and a layer of a second material formed over the feature. The semiconductor structure is exposed to an etchant. The etchant is adapted to selectively remove the first material, leaving the second material substantially intact. After exposing the semiconductor structure to the etchant, it is detected whether the feature has been affected by the etchant.

Abstract: The present invention provides for a system and method of characterizing the integrity of a barrier structure. The barrier structure is an interconnect comprising a porous dielectric layer sandwiched between at least one barrier layer and at least one conducting layer. The method of characterizing the integrity of such an interconnect includes providing an interconnect, infiltrating the interconnect with a solution comprising electrolytes, applying an external bias to the infiltrated interconnect, and characterizing the integrity of the interconnect after application of the external bias.

Abstract: The invention provides a method for manufacturing an integrated circuit. The method, in one embodiment, includes inspecting a semiconductor wafer including a plurality of die for a defect, the inspecting providing an image of the semiconductor wafer including the defect. The method further includes identifying an area of the semiconductor wafer from the image, wherein the identified area encompasses at least those die including any portion of the defect, and dicing the semiconductor wafer into individual die. The die defined by the identified area, in this embodiment, are then discarded.

Abstract: A test methodology is provided for testing metal-insulator-metal (MIM) capacitor structures under high temperatures at the wafer level. A resistor is formed on a region of dielectric isolation material formed in a semiconductor substrate. The MIM capacitor is formed over the resistor and separated therefrom by dielectric material. A metal thermometer, formed from the same material as the plates of the MIM capacitor, is placed above the resistor and in close proximity to the capacitor. High current is forced through the resistor, causing both the metal thermometer and the MIM capacitor to heat up along with the resistor. The change in resistance of the metal thermometer is monitored. Using the known temperature coefficient of resistance (TCR) for the metal used to form both the capacitor and the thermometer, changes in the measured resistance of the metal thermometer are converted to temperature.

Abstract: A wafer transferring robot in semiconductor device fabricating equipment and a method of detecting wafer warpage by using the wafer transferring robot are provided. In the realizing the wafer transferring robot to transfer a wafer, vacuum lines are formed to adsorb a plurality of regions of the wafer. Whether the wafer is warped or not and the extent of warpage are determined in real time, depending on whether the wafer is adsorbed by the vacuum lines. When no warpage occurs on the wafer or when the extent of warpage is slight, the wafer is allowed to be normally processed. When the extent of warpage is too serious to perform a normal process on the wafer, the wafer is previously processed as an error, thereby preventing the waste of time, cost and manpower caused by performing an unnecessary process.

Abstract: A pattern shape evaluation method comprising detecting an edge of an evaluation target pattern from an image of the evaluation target pattern to output the edge as a first edge, detecting an edge of a reference pattern from an image of the reference pattern to output the edge as a second edge, performing a relative scan of the first edge and the second edge to superpose the first edge onto the second edge, and outputting a resulting edge as a third edge, calculating a characteristic amount indicating characteristics of the third edge from the third edge, and deriving a characteristic amount function which provides the characteristic amount against relative coordinates in the relative scan and comparing the characteristic amount function with a preset value to judge whether or not the evaluation target pattern is good.

Abstract: Excitation light is irradiated onto a GaN layer on a silicon carbide substrate constituting a layered product that is set on a stage. Then light is emitted from a defective part caused by a structural defect of the silicon carbide substrate out of the GaN layer. By using this light luminescence phenomena, a position of a defective part of the silicon carbide substrate can be detected.

Abstract: In the resin film evaluation method and method for manufacturing a semiconductor device applying the resin film evaluation method of the present invention, first, a substrate having a resin film formed on an insulating film with an opening in which the surface of the insulating film is exposed is irradiated with charged energetic particles. Then, the surface potentials of the substrate surface irradiated with charged energetic particles are measured. Based on the measurements, the difference in surface potential between the resin film and the insulating film exposed in the opening is obtained. Based on the difference in surface potential, a physical quantity such as the resin film residue count obtained after a given treatment is predicted. In this way, the degenerated layer formed on the surface of a resin film due to charged energetic particles such as implantation ions can be evaluated in a simple and highly accurate manner.

Abstract: A method for fabricating and testing a wafer includes forming metal traces with metal pads, wherein forming the metal traces include forming a TiW layer on a passivation layer and on pads, next forming a seed layer on the TiW layer, next forming a photoresist layer on the seed layer, next forming a metal layer on the seed layer exposed by openings in the photoresist layer, next removing the photoresist layer, next removing the seed layer not under the metal layer, and then etching the TiW layer not under the metal layer with an etchant containing H2O2 at a temperature of between 35 and 50° C., or with an etchant containing H2O2 and with ultrasonic waves applied to the etchant, next contacting probe tips of a probe card with some of the metal pads, next cleaning the probe tips until repeating the step of contacting the probe tips with some of the metal pads at greater than 100 times, and then after cleaning the probe tips, repeating the step of contacting the probe tips with some of the metal pads.

Abstract: A method and apparatus for identifying defective partially manufactured semiconductor wafers in a manufacturing line is described, wherein defects caused by silicon erosion created by over-etching the wafer can be detected. The method described herein is based on an in-line test of selected structures, such as FETs, located in the kerfs that surround the integrated circuit chips. Leakage current between the gate and the source-drain region is measured at FETs in each kerf. Based on the measurement, a leakage current map is created and compared to a standard map. In accordance with this comparison and to the distribution of patterns of leakage currents, it is determined whether or not the wafer is defective. This determination is performed in the kerfs after formation of the gate and source-drain regions, and prior to the wafer being completed. By detecting defective wafers at an early stage, considerable manufacturing resources are saved.

Abstract: Systems and methods are disclosed for producing vertical LED array on a metal substrate; evaluating said array of LEDs for defects; destroying one or more defective LEDs; forming good LEDs only LED array suitable for wafer level package.

Abstract: An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.

Abstract: There is obtained a silicon wafer which has a large diameter, where no slip generated therein in a wide range of a density of oxygen precipitates even though a heat treatment such as SLA or FLA is applied thereto, and which has high strength. First, by inputting as input parameters combinations of a plurality of types of oxygen concentrations and thermal histories set for manufacture of a silicon wafer a Fokker-Planck equation is solved to calculate each of a diagonal length L and a density D of oxygen precipitates in the wafer after a heat treatment step to form the oxygen precipitates (11) and immediately before a heat treatment step of a device manufacturing process is calculated.

Abstract: A method of chip manufacturing, comprises of a design stage; a simulation stage; a foundry stage; a testing/packaging stage; a cutting stage; and a final coating stage. The present invention provides a method of chip testing comprises of disposing a substrate layer on a wafer having a plurality of chips; exposing a plurality of pads on the chips of the wafer; forming bumps on the pads of the chips of the wafer; performing tests from the bumps on the chips of the wafer. Alternatively, the present invention provides a method of chip testing comprises of disposing a substrate layer on a wafer having a plurality of chips; connecting a plurality of pads on the chips of the wafer to a plurality of corresponding pads on the substrate layer; planting bumps on the pads on the opposite side of the substrate layer; performing tests from the bumps on the substrate layer.

Abstract: A method for increasing an electrical resistance of a resistor that is within a semiconductor structure. A fraction of a surface layer of the resistor is oxidized with oxygen particles. In an embodiment, the fraction of the surface layer is heated by a beam of particles, such that the semiconductor structure is within a chamber that includes the oxygen particles as gaseous oxygen-comprising molecules. In an embodiment, the semiconductor structure is immersed in a chemical solution which includes the oxygen particles, wherein the oxygen particles includes oxygen-comprising liquid molecules, oxygen ions, or an oxygen-comprising gas dissolved in the chemical solution under pressurization. In an embodiment, the resistor is tested to determine whether the electrical resistance of the resistor after being oxidized with the oxygen particles is within a tolerance of a predetermined target resistance.

Abstract: OPC results may be efficiently evaluated on the basis of a test structure containing a plurality of line features with opposing end portions. Thus, for different line parameters, the effect of OPC may be determined for a given critical tip-to-tip distance by determining the leakage behavior of the test assemblies, each having different design parameter values for line width and lateral distance between adjacent lines.

Abstract: A manufacturing device of a semiconductor package includes: a holding element for holding a substrate; a bonding element for holding the package and bonding a first metal bump of the package to a second metal bump of the substrate; a monitoring element for irradiating an infrared light toward the substrate and monitoring an electrode pad under the second metal bump based on a reflected light reflected on the pad; and a determination element for determining a state of a bonding surface between the first and second metal bumps based on monitoring information of the pad. The monitoring element faces the bonding element through the holding element, the substrate and the package.

Abstract: Methods may be provided to determine an alignment of a laser with respect to an integrated circuit device including a fuse pattern and a monitoring pattern adjacent the fuse pattern. More particularly, the fuse pattern may be cut with radiation from the laser. After cutting the fuse pattern, an electrical signal through the monitoring pattern may be measured to determine an alignment of radiation from the laser with respect to the fuse pattern. Related structures, devices, and circuits are also discussed.

Abstract: A test structure includes first and second combs, at least a first pair of base nodes, and a second pair of finger nodes. The first comb includes a first base and a first plurality of fingers extending from the first base. The second comb includes a second base and a second plurality of fingers extending from the second base. At least a portion of the first and second pluralities of fingers are interleaved. The first pair of base nodes extend from the first base. The second pair of finger nodes extend from a first finger of the first plurality of fingers.

Abstract: A semiconductor device in accordance with one embodiment of the present invention includes: a strained semiconductor layer formed on a substrate; and a strain measuring region, provided on the substrate, for measuring a strain of the semiconductor layer. The semiconductor device may further include: a reference information measuring region, provided on the substrate, for measuring reference information for evaluating the strain of the semiconductor layer.

Abstract: A semiconductor device fabrication method is disclosed. The method comprises an insulating film forming step of forming an insulating film on a semiconductor substrate; a trench forming step of forming a trench for device isolation in a predetermined part of the semiconductor substrate; a trench filling step of forming a buried oxide film filling the trench; a polishing step of polishing the buried oxide film on the semiconductor substrate until the insulating film is exposed; a thickness measuring step of measuring the thickness of the insulating film remaining after the polishing; an etching amount determining step of determining an etching amount of etching the polished buried oxide film based on the measured thickness of the remaining insulating film; and a buried oxide film etching step of etching the polished buried oxide film based on the determined etching amount.

Abstract: Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.

Abstract: Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a pre-existing semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes.

Abstract: A stacked semiconductor package may include a wiring substrate. A first semiconductor chip may be disposed on the wiring substrate and wire-bonded to the wiring substrate. An interposer chip may be disposed on the wiring substrate and sire bonded to the wiring substrate. The interposer chip may include a circuit element and a bonding pad being electrically connected. A second semiconductor chip may be disposed on the interposer chip and wire-bonded to the interposer chip. The second semiconductor chip may be electrically connected to the wiring substrate through the interposer chip.

Abstract: A multi-layered circuit board a built-in component including multiple terminals, at least one signal pad formed on a top surface of the multi-layered circuit board for signal transmission, each of the at least one signal pad corresponding to one of the multiple terminals, and at least one test pad formed on the top surface of the multi-layered circuit board, each of the at least one test pad corresponding to one of the at least one signal pad for testing an electric path extending from the one signal pad through the one terminal to the each of the at least one test pad.

Abstract: This SOI substrate includes a base substrate which includes a single-crystal semiconductor and an active layer which includes a single-crystal semiconductor and is bonded to the base substrate with an oxide film therebetween. The oxide film is formed only in the active layer. The active layer is formed with a thickness of 10 to 200 nm and a thickness variation throughout the active layer of 1.5 nm or less by etching a surface of the active layer while selectively using only the reactive radicals generated by a plasma etching process.

Abstract: A manufacturing method of a semiconductor device, comprises; a process of heat-treating a semiconductor substrate under the ordinary pressure and in an oxidizing atmosphere; and a process of heat-treating the semiconductor substrate under the ordinary pressure and in an inert atmosphere, wherein heat-treating time or heat-treating temperature in heat treatment in the oxidizing atmosphere is changed based on the fluctuation of atmospheric pressure, and the heat-treating time in the inert atmosphere is determined based on the heat-treating time or the heat-treating temperature in the oxidizing atmosphere.