Abstract: A method according to the present invention for producing a semiconductor-chip-mounting circuit 1 includes mainly three steps. In a first step, contacts 2 each in the form of a conical helix are formed by solder-plating the surface of connecting terminals 12 on a mounting circuit 10. In a second step, a continuity test is performed by pressing bumps 21 against the contacts 2. In a final third step, the contacts 2 pressed are melted to connect the connecting terminals 12 to the bumps 21. That is, the semiconductor chip 20 is connected to the mounting circuit 10 while maintaining a state in which they pass the continuity test, thereby significantly reducing the occurrence of defective continuity in the semiconductor-chip-mounting circuit 1.

Abstract: A charged particle beam irradiation method includes setting an observation region on a sample, the sample including an object pattern to be observed, and the observation region including the object pattern, setting an irradiation region on the sample, the irradiation region being to be irradiated with a charged particle beam, the irradiation region including the observation region and being larger than the observation region, setting a non-irradiation region in the irradiation region, the non-irradiation region failing to be irradiated with the charged particle beam, irradiating the irradiation region except the non-irradiation region with the charged particle beam, and irradiating the observation region with a charged particle beam after the irradiating the irradiation region except the non-irradiation region with the charged particle beam.

Abstract: The present invention provides a semiconductor device, including: a first semiconductor chip, and a second semiconductor chip connected to the first semiconductor chip through a plurality of bumps having not only a number of main bumps necessary for operation between the chips but also a predetermined number of measurement and control input bumps. Each of the first and second chips includes a plurality of measurement path switches individually connected to the main bumps, a plurality of current path switches connected to connecting points between the main bumps and the measurement path switches, and a control circuit for the measurement path switches, the first semiconductor chip further including a plurality of measurement and control terminals for inputting a control signal of the control circuit and supplying fixed current to be supplied to the current path switches and then measuring the voltage at the connecting points.

Abstract: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.

Abstract: A method for monitoring a nitridation process, including: (a) providing a semiconductor substrate; (b) forming a first dielectric layer on a top surface of the substrate; (c) introducing a quantity of interfacial species into the substrate; (d) removing the first dielectric layer; (e) forming a second dielectric layer on the top surface of the substrate; (f) measuring the density of interface traps between the substrate and the second dielectric layer; (g) providing a predetermined relationship between the quantity of the interfacial species and the density of the interface traps; and (h) determining the quantity of the interfacial species introduced based on the relationship.

Abstract: Techniques for inspecting semiconductor devices. An inspection condition using chip matrix data and chip size data is set. The intricate circuit patterns of at least one semiconductor device is inspected with the inspection condition. In an embodiment of the present invention, inspection uses images formed by the irradiation of white light, a laser light, or an electron beam. Data obtained from the inspection is used to generate a revised inspection condition. Semiconductor devices are inspected using the revised inspection condition.

Abstract: The present invention generally provides an apparatus and a method for inspecting a substrate in a substrate processing system. In one aspect, a voltage or current source is used in conjunction with a power density receiving device, such as a spectrometer, to inspect a substrate for various noise spectrum signatures. In one embodiment, spectral data collected from a given substrate is used to generate a current or voltage spectral signature. This spectral signature may then be compared to a reference spectral density signature to predict reliability of a feature structure of a substrate in processing and feedback to the substrate processing system for substrate processing control. Embodiments of the invention further include computer-readable media containing instructions for controlling the substrate processing system, and computer program products having computer-readable program code embodied therein for controlling the substrate processing system and inspecting defects on semiconductor features.

Abstract: An apparatus for fabricating semiconductor packages may include a thickness measurer configured to measure the thickness of a printed circuit board (PCB); mold dies, clamped to the top and the bottom of the PCB, through which a molding compound may be injected; and a pressure controller configured to control a clamp pressure of the mold die in response to the thickness of the PCB. The thickness of the PCB may be measured before molding the PCB, and a clamp pressure corresponding to the measured thickness may be decided. Therefore, it is possible to adjust the thickness variation of a PCB in real time, as they are being produced, to decrease the number of bad packages.

Abstract: A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed.

Abstract: An increased area of an element transistor to be evaluated causes an increased leakage current due to a tunnel effect, leading to a reduced accuracy in predicting a TDDB lifetime. A test element group (TEG) 1 is a pattern for evaluating electric characteristics, comprising a plurality of unit transistors T11, T12, T13, T21, T22, T23, T31, T32, T33, which are arranged so as to form a lattice-shaped pattern. Each of the unit transistors comprises a gate dielectric serving as an object to be evaluated, and source region and drain region, which are a short-circuited.

Abstract: A probe sheet or a connecting sheet with good transmission characteristics and flexibility comprising contact terminals capable of contacting at a plurality of points and in high density, without applying damages on an electrode pad which is a contact subject is provided. Further, a high-speed transmission circuit capable of designing signal wirings with aligned impedance to have wide width even with a thin insulating film is achieved to provide a probe sheet or a connecting sheet with reduced loss of high-speed transmission signals. Moreover, the transmission circuit is applied to a probe card using a probe sheet, an inspecting method of (a method of manufacturing) a semiconductor device using the same, and a connecting sheet having an excellent high-frequency characteristic.

Abstract: A test module for measuring electrical characteristics of a semiconductor device includes a plurality of shallow trench isolation (STI) layers formed over a semiconductor substrate. An active area includes not only an extended part enclosing the STI layers but also a plurality of minute line-width parts isolated by the STI layers. A gate oxide layer is formed over the STI layers and the active area. A gate electrode is formed over the STI layers and the minute line-width parts of the active area with interposing the gate oxide layer. An interlayer insulating layer, a metal wiring layer, a contact plug, and test pads allow non-destructive testing of the semiconductor device.

Abstract: By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.

Abstract: The reliability of a GOLD structure TFT depends on an impurity concentration in its gate-overlapped region. Thus, it is an object of the present invention to obtain a resistance distribution corresponding to a tapered shape of a gate electrode in a gate-overlapped region. According to the present invention, plural TEGs are manufactured as Lov resistance monitors in which mask alignment is misaligned with several ?m interval to perform a resistance measurement on each of the TEGs. Consequently, a resistance distribution corresponding to a tapered shape can be obtained in a channel forming region, a gate-overlapped region and a source/drain region.

Abstract: At least three pads 10A, 10B, 10C are provided on a scribe line 8 located adjacent to a chip region 2. The three pads are a power pad 10A connected to a power potential portion 5 in the chip region 2, a grounding pad 10B connected to a ground potential portion 6 in the chip region 2, and a switchover pad 10C that is connected to a semiconductor device 7 in the chip region 2 and switches the operating state of the semiconductor device 7 between a normal operating state and a standby state. During a wafer test, contact pins 9A, 9B, 9C of a probe card are brought in contact with the three pads 10A, 10B, 10C, respectively.

Abstract: Provided are the methods of evaluating thermal treatment. In the methods, a wafer comprising a silicon substrate having an oxygen concentration of approximately equal to or less than 1.0×1018 atoms/cm3 and a silicon epitaxial layer on at least one surface of the substrate is employed.

Abstract: Methods for evaluating a quality of a semiconductor substrate. In one aspect, etching a surface of the semiconductor substrate by dry-etching, detecting bright points on the surface of the etched surface with a foreign matter inspection device, and evaluating the quality of the semiconductor substrate based on the number and/or distribution pattern of the detected bright points are included. In another aspect, etching a surface of the semiconductor substrate by dry-etching, detecting bright points on the surface of the etched surface with a foreign matter inspection device, and evaluating the quality of the semiconductor substrate are included, and the evaluated quality is a type of metal contaminant contained in the substrate, and the type of metal contaminant is identified by conducting elemental analysis of the detected bright points.

Abstract: A display substrate includes a pixel, a signal transmission line, a first insulating layer and a test signal input part. The pixel is on an insulating substrate. The signal transmission line is on the insulating substrate to transmit an image signal. The first insulating layer is on the signal transmission line. The first insulating layer has a contact hole through which the signal transmission line is partially exposed. The test signal input part is on the first insulating layer, and includes an extended portion and a test signal pad. The extended portion is electrically connected to the signal transmission line through the contact hole, and is extended toward a side of the insulating substrate. The test signal pad is electrically connected to the extended portion. Therefore, the number of defects is decreased.

Abstract: A semiconductor substrate inspection method includes: generating a charged particle beam, and irradiating the charged particle beam to a semiconductor substrate in which contact wiring lines are formed on a surface thereof, the contact wiring lines of the semiconductor substrate being designed to alternately repeat in a plane view so that one of the adjacent contact wiring lines is grounded to the semiconductor substrate and the other of the adjacent contact wiring lines is insulated from the semiconductor substrate; detecting at least one of a secondary charged particle, a reflected charged particle and a back scattering charged particle generated from the surface of the semiconductor substrate to acquire a signal; generating an inspection image with the signal, the inspection image showing a state of the surface of the semiconductor substrate; and judging whether the semiconductor substrate is good or bad from a difference of brightness in the inspection image obtained from the surfaces of the adjacent cont

Abstract: A p impurity region (3) defines a RESURF isolation region in an n? semiconductor layer (2). A trench isolation structure (8a) and the p impurity region (3) together define a trench isolation region in the n? semiconductor layer (2) in the RESURF isolation region. An nMOS transistor (103) is provided in the trench isolation region. A control circuit is provided in the RESURF isolation region excluding the trench isolation region. An n+ buried impurity region (4) is provided at the interface between the n? semiconductor layer (2) and a p? semiconductor substrate (1), and under an n+ impurity region 7 connected to a drain electrode (14) of the nMOS transistor (103).

Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.

Abstract: A decapsulation apparatus 100 has a laser 8 that removes plastic encapsulant from a device 24. Chamber 20 is sealed. Exhaust port 9 removes debris and fumes. The device 24 is positioned and scanned using an X, Y table 2. A hinged end 4 rotates the device to an acute angle of incidence with respect to a laser 8. Endpoint detector 10 senses the exposed integrated circuit and moves or shuts down the laser 8.

Abstract: A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.

Abstract: A 3-dimensional PCM structure and method for using the same for carrying out 3-dimensional integrated circuit wiring electrical testing and failure analysis in an integrated circuit manufacturing process, the method including forming a first metallization layer; carrying out a first wafer acceptance testing (WAT) process to test the electrical continuity of the first metallization layer; forming first metal vias on the first metallization layer conductive portions and a second metallization layer comprising metal islands on the first metal vias wherein the metal islands electrically communicate with the first metallization layer to form a process control monitor (PCM) structure; and, carrying out a second WAT process to test the electrical continuity of the first metallization layer.

Abstract: In a metal-oxide semiconductor device including first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, an insulating layer formed on at least a portion of the upper surface of the semiconductor layer, and a gate formed on the insulating layer and at least partially between the first and second source/drain regions, a method for controlling an amount of hot carrier injection degradation in the device includes the steps of: forming a shielding structure on the insulating layer above at least a portion of the drift region and substantially between the gate and the second source/drain region; and adjusting an amount of coverage of the shielding structure over an upper surface of the drift region so as to minimiz

Abstract: An electron beam drawing apparatus includes an acquisition unit which acquires a position data of an Nth drawing area, an acquisition unit which acquires a stage position and speed, a prediction unit which predicts a stage position when drawing on the Nth area is carried out, a determination unit which determines whether a distance from the stage position to the Nth area position is less than a deflection distance, a decision unit which, when the distance is less than the deflection distance, corrects a deflection distortion in accordance with the determined distance and decides a deflection voltage, a detection unit which detects a drawing end of an (N-1)th drawing area when drawing on the (N-1)th area is ended, and a drawing unit which, when the drawing end is detected, deflects an electron beam in accordance with the deflection voltage to draw a pattern on the Nth area.

Abstract: The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.

Abstract: Various embodiments include a method for providing instructions to a process tool. The method includes emitting an incident light beam at a substrate, receiving a reflected light beam from the substrate and determining a spectrum of the reflected light beam. The method further includes determining a first property of a first layer of the substrate and a second property of a second layer of the substrate, based on the spectrum determination. The method further includes comparing the first property of the first layer to a first reference property and comparing the second property of the second layer to a second reference property. The method further includes determining the instructions based on the first property comparison and the second property comparison; and providing the instructions to the process tool.

Abstract: A positioning apparatus for positioning a substrate. The positioning apparatus includes a setting system which selectively sets one of a center of the substrate and a specific portion of an edge of the substrate as a positioning reference in accordance with information inputted to the positioning apparatus, and a positioning system which positions the substrate based on a position of the positioning reference set by the setting system.

Abstract: A burn-in process for a semiconductor integrated circuit device includes a first process of positioning bump electrodes of the semiconductor integrated circuit device with respect to pads of a socket having detachment mechanisms, a second process of pressing the bump electrodes against the pads by weighting the semiconductor integrated circuit device, and a third process of detaching the bump electrodes from the pads by exerting force on the semiconductor integrated circuit device in a direction opposite to a weighting direction of the second process. Automatic insertion and detachment of a semiconductor integrated circuit chip in a burn-in test is facilitated by detaching the bump electrodes from the pads by pushing up the semiconductor integrated circuit device.

Abstract: A method of measuring a diffusion length of a minority carrier in a silicon wafer by a surface photovoltage method including irradiating the surface-treated silicon wafer with ultraviolet radiation in an oxygen-containing atmosphere, and measuring a diffusion length of a minority carrier in a silicon wafer by a surface photovoltage method.

Abstract: A full wafer inspection apparatus and a manufacturing method of a semiconductor device capable of collectively and precisely inspecting semiconductor elements formed on a wafer, while securing the positional accuracy of tip portions of contact terminals are provided.

Abstract: A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

Abstract: A sensor on a semiconductor wafer is used as a process monitor and a capacitor is employed as a power supply for the sensor. The capacitor can be formed by stacking a poly-silicon layer and a silicon nitride layer on the wafer. A timer can be used to specify an operation time or an operation timing, etc. Furthermore, unauthorized use is prevented by storing a keyword in an ROM of the process monitor.

Abstract: A semiconductor device having a semiconductor chip stack on a rewiring plate is disclosed. In one embodiment, the device includes an external contact area having a plurality of external contact area regions which are physically separate from one another is arranged on the underside. The individual external contact area regions are assigned to the individual semiconductor chips in the semiconductor chip stack. The external contact regions of an individual external contact area have a common external contact which electrically connects the external contact area regions.

Abstract: An interconnect structure including a substrate, an interconnect device formed on the substrate, and a test device formed on the substrate.

Abstract: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.

Abstract: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.

Abstract: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.

Abstract: A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.

Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

Abstract: A semiconductor wafer design and process having test pads (36) reducing cracks generated during the wafer saw process from extending into and damaging adjacent die. The present invention provides a plurality of circular test pads (36) in a wafer scribe street (34) such that any cracks generated in the test pad during wafer saw self terminate in the periphery of the circular test pad. By providing a curved test pad periphery, cracks will tend to propagate along the edges of the test pads and self terminate therein. The circular test pads avoid any sharp corners as is conventional in rectangular test pads which tend to facilitate the extension of cracks from corners to extend into the adjacent wafer die (32). The present invention utilizes existing semiconductor fab processing and utilizes new reticle sets to define the curved test pads.

Abstract: A conductive member having a first face adapted to be mounted on a board on which an inspection circuit is arranged, and a second face adapted to be opposed to a device to be inspected is prepared. The conductive member is formed with a first through hole having a first diameter and communicating the first face with the second face. A contact probe including a tubular body having a second diameter which is smaller than the first diameter, and a plunger retractably projected from one end portion of the tubular body is prepared and disposed in the first through hole. A conductive plate having a second through hole is prepared. Molten resin is injected into the second through hole such that at least a part of inner face of the second through hole is covered with solidified resin, thereby forming a third through hole. The conductive plate is disposed so as to oppose to the second face of the conductive member and to communicate the third through hole with the first through hole.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: A method and an apparatus for self-heating burn-in have been disclosed. In one embodiment, a semiconductor device includes a plurality of gates, a multiplexer to select a clock signal out of a plurality of clock signals to toggle the plurality of gates in response to the selected clock signal to generate heat internally for burn-in, and a thermal sensing circuitry to monitor an internal temperature.

Abstract: To prevent breakage of a membrane probe during a probe test using a probe card having the membrane probe, appearance of a main surface of a wafer as a test object is tested by an appearance tester 51, and results of bad appearance such as adhesion of a foreign substance to the main surface of the wafer and abnormality in shape of bump electrodes over the main surface of the wafer are collected as wafer map data according to arrangement of respective chips in a plane of the wafer, then the wafer map data are transmitted to a probe tester 53 via a server 52, and the probe tester 53 omits the probe test for chips in which bad appearance was detected, and concurrently performs the probe test to other chips in which bad appearance was not detected, based on the wafer map data.

Abstract: Methods and systems for authenticating the operation of electronic devices, such as RFID tags are provided. In accordance with the method, a web of substrates having a plurality of devices attached thereto are received. The operation of a first set of the plurality of devices is authenticated. If it is determined that one or more devices is not operating properly, the location of each device is determined. The web of substrates is then moved incrementally to expose a second set of the plurality of devices. Each device that does not operate properly is indicated by applying ink to the substrate containing the device or by removing the device.

Abstract: A lithographic pattern includes a first scribe along an edge of a die region, and a second scribe along an opposing edge of the die region. The first scribe includes at least a first translucent box and a second translucent box. The second scribe includes at least a first opaque box and a second opaque box defined respectively by a first translucent frame and a second translucent frame. When the lithographic pattern is stepped between fields on a wafer, the first translucent box is placed at least partially within the first opaque box, and the second translucent box is placed at least partially within the second opaque box. If a continuous ring is formed from a pair of a translucent box and an opaque box, the fields are aligned at least within an amount equal to the difference between the dimensions of that translucent box and that opaque box divided by 2.

Abstract: A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.

Abstract: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.