Abstract: An instrument for measuring a parameter comprises a substrate, a plurality of sensors carried by and distributed across a surface of the substrate that individually measure the parameter at different positions, an electronic processing component carried by the substrate surface, electrical conductors extending across the surface connected to the sensors and the electronic processing component, and a cover disposed over the sensors, electronic processing component and conductors. The cover and substrate have similar material properties to a production substrate processed by a substrate processing cell. The instrument has approximately the same thickness and/or flatness as the production substrate. The instrument may be subjected a substrate process and one or more parameters may be measured with the instrument during the process. The behavior of a production wafer in the substrate process may be characterized based on measurements of the parameters made with the one or more sensors.

Abstract: A chip on film (COF) package comprising a test pad for testing the electrical function of a semiconductor chip and a method for manufacturing same are provided. The COF package comprises a semiconductor chip mounted on a base film, a signal-input portion for receiving data and control signals and transmitting the data and control signals to the semiconductor chip, a plurality of passive elements connected to terminals of the semiconductor chip, and a plurality of test pads for testing one or more terminals of the semiconductor chip that are not connected to the signal-input portion. The test pads of the COF package are capable of testing a plurality of internal terminals which are integrated into one terminal and do not connected to the signal-input portion, thereby easily testing the electrical function of the chip.

Abstract: In accordance with one embodiment of the invention, a method and apparatus are provided for testing a wafer while the wafer is disposed in a wafer carrier. The test results can be utilized to adjust the manufacturing process and thereby increase processing yield.

Abstract: According to one exemplary embodiment, a method for monitoring structural integrity of at least one fuse in semiconductor wafer, which includes at least one electrical monitoring structure, includes forming a monitoring window in a dielectric layer overlying the at least one electrical monitoring structure, where the monitoring window and a fuse window overlying the at least one fuse are, in one embodiment, formed in a same etch process. The method further includes performing at least one electrical measurement on the at least one electrical monitoring structure, wherein the at least one electrical measurement is utilized to monitor the structural integrity of the at least one fuse. A change in the at least one electrical measurement is utilized to indicate a change in the structural integrity of the at least one fuse. The at least one electrical monitoring structure can include, for example, a metal serpentine line and one or more metal combs.

Abstract: A substrate supporting apparatus includes first and second shafts spaced by a distance that corresponds to or exceeds a width of a substrate, and at least one wire to support the substrate. The wire has ends coupled to respective ones of the first and second shafts. The wire is raised and lowered to place a substrate onto a lower electrode in a substrate processing chamber and to remove the substrate when processing is completed.

Abstract: A method and system for registering a CAD layout to a Focused Ion Beam image for through-the substrate probing, without using an optical image and without requiring biasing, includes an improved method of trench endpointing during the FIB milling operation with a low beam energy. The method further includes removal of Ga at the trench floor using XeF2, as well as the deposition of an insulating layer onto the trench floor.

Abstract: A burn-in input signal input to a burn-in circuit is delivered to an internal circuit through a selector. In response to a control signal from the burn-in circuit, the selector selects either the burn-in input signal or an input signal for operating the internal circuit. In the burn-in test process, a portion of an output signal is monitored to determine the degree of degradation of the internal circuit.

Abstract: A method of manufacturing a semiconductor device capable of largely increasing the yield and a semiconductor device manufactured by using the method is provided. After a semiconductor layer is formed on a substrate, as one group, a plurality of functional portions with at least one parameter value different from each other is formed in the semiconductor layer for every unit chip area. Then, a subject that is changed depending on the parameter value is measured and evaluated and after that, the substrate is divided for every chip area so that a functional portion corresponding with a given criterion as a result of the evaluation is not broken. Thereby, at least one functional portion corresponding with a given criterion can be formed by every chip area by appropriately adjusting each parameter value.

Abstract: Methods for singulating surface-mountable semiconductor devices and for fitting external contact areas to the devices are described herein. Semiconductor device components are applied to a metallic carrier in rows and columns in corresponding semiconductor device positions of the metallic carrier. Thereafter, a plurality of components, situated in the device positions, is embedded into a plastic housing composition, thereby producing a composite board. The composite board is subsequently separated into individual semiconductor devices by laser ablation, the semiconductor devices being inscribed on their top sides via the laser technique. The top sides with the inscription can then be adhesively bonded to an adhesive film, so that the undersides of the devices can be uncovered while maintaining the semiconductor device positions.

Abstract: A structure and a method for forming the same. The structure includes (a) a substrate having a top substrate surface; (b) an integrated circuit on the top substrate surface, wherein the integrated circuit includes a bond pad electrically connected to a transistor of the integrated circuit; (c) a protection ring on the top substrate surface and on a perimeter of the integrated circuit; (c) a kerf region on the top substrate surface, wherein the protection ring is sandwiched between and physically isolates the integrated circuit and the kerf region, wherein the kerf region includes a probe pad electrically connected to the bond pad, and wherein the kerf region is adapted to be destroyed by chip dicing without damaging the integrated circuit and the protection ring.

Abstract: A method of fabricating a TFT using dual or multiple gates, and a TFT having superior characteristics and uniformity by providing a method of fabricating a TFT using dual or multiple gates by calculating the probability including Nmax, the maximum number of crystal grain boundaries in active channel regions according to the length of the active channels, and adjusting a gap between the active channels capable of synchronizing the number of the crystal grain boundaries in each active channel region of the TFT using the dual or multiple gates in the case where Gs, the size of crystal grains of polycrystalline silicon forming a TFT substrate, ? angle in which “primary” crystal grain boundaries are inclined at a direction perpendicular to an active channel direction of the gates, the width of the active channels and the length of the active channels are determined.

Abstract: A test element group for monitoring leakage current in a semiconductor device and a method of manufacturing the same are disclosed. The test element group for monitoring leakage current in a semiconductor device includes device isolation layers formed over a first conductivity type semiconductor substrate. A second conductivity type well may be formed over the first conductivity type semiconductor substrate. First conductivity type impurity regions may be formed in first active areas between the device isolation layers in the second conductivity type well. Monitoring contacts may be formed within the first active areas to monitor leakage current, using layout data such that a distance from each of the monitoring contacts to a border of each of the first active areas is set to have an allowable minimum value under a predetermined design rule.

Abstract: A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.

Abstract: The present invention provides a method detecting metal silicide defects in a microelectronic device. The method comprises positioning (110) a portion of a semiconductor substrate in a field of view of an inspection tool. The method also comprises producing (120) a voltage contrast image of the portion, wherein the image is obtained using a collection field that is stronger than an incident field. The method further comprises using (130) the voltage contrast image to determine a metal silicide defect in a microelectronic device. Other aspects of the present invention include an inspection system (200) for detecting metal silicide defects and a method of manufacturing an integrated circuit (300).

Abstract: A substrate processing method of the present invention includes the steps of placing a substrate inside a vacuum container containing particles and processing the substrate inside the container while moving the substrate at a predetermined relative velocity of the substrate to the container. In this case, an allowable upper limit of the number or density of defects produced at the substrate due to the particles in the process for the substrate is determined, and the predetermined relative velocity is set at a value equal to or smaller than the relative velocity obtained when the number or density of defects reaches the upper limit.

Abstract: A wafer thinning system and method are disclosed that includes grinding away substrate material from a backside of a semiconductor device. A current change is detected in a grinding device responsive to exposure of a first set of device structures through the substrate material, where the grinding is stopped in response to the detected current change. Polishing repairs the surface and continues to remove an additional amount of the substrate material. Exposure of one or more additional sets of device structures through the substrate material is monitored to determine the additional amount of substrate material to remove, where the additional sets of device structures are located in the semiconductor device at a known depth different than the first set.

Abstract: A change rate prediction method according to which there can be eliminated the need for experimentally determining electron beam intensities for making a change rate of a specification value of a predetermined film on a substrate uniform. The distribution of the shrinkage rate of a low-k film on a wafer upon the low-k film being modified is measured while changing the inputted current value inputted to a central electron beam tube of an electron beam irradiating mechanism, the relationship between the inputted current value and the shrinkage rate measured directly below the electron beam tube is calculated, and a dose distribution calculated through simulation is converted into a low-k film shrinkage rate distribution based on the ratio between the inputted current value and the dose and a power curve giving the relationship between the inputted current value and the measured shrinkage rate.

Abstract: A wafer arrangement in accordance with an embodiment of the invention includes a wafer having a plurality of dice, wherein at least some of the dice have a first connection, and at least one contact pad formed at the wafer edge, wherein a plurality of first connections are coupled by means of a section of a redistribution layer and the contact pad is formed by the section of the redistribution layer.

Abstract: A method is provided for producing a smart card comprising a chip module with at least one contacting area, the chip module arrangeable in a mounting location of a substrate, wherein one contacting loop is formed from a wire connector fed by a wire guiding unit for at least one of the contacting areas, respectively by attaching a first section of the wire conductor to a surface of the substrate outside the mounting location, wherein a second section of the wire conductor proximate to the first section is guided to form the contacting loop along with and protruding from the surface, wherein a subsequent third section of the wire conductor is attached to the surface outside the mounting location, wherein the chip module is inserted into the mounting location and wherein the second section is bent over and electrically contacted to the contacting area.

Abstract: A pixel includes an organic light emitting diode, a first transistor having a source coupled to a first power source, a control gate coupled to a first node, and a drain coupled to a second node, wherein the first transistor includes a floating gate and an insulating layer between the floating gate and the control gate, a second transistor having a source coupled to a data line, a drain coupled to the first node, and a gate coupled to a scan line, a third transistor having a source coupled to the second node, a drain coupled to the organic light emitting diode, and a gate coupled to one of a light emitting control line and the scan line, and a capacitor coupled between the first power source and the second node.

Abstract: In the semiconductor device manufacturing method of the present invention, first, the emissivity of a wafer placed in a chamber is measured. Then, the fluctuation rate of a wafer physical quantity that fluctuates in association with the given thermal energy is calculated based on an estimate expression, which are obtained in advance, presenting the relationship between the thermal energy quantity emitted from the heat source for heating the wafer, wafer emissivity and the wafer physical quantity fluctuation rate and on the measured emissivity. Subsequently, the processing time for the physical quantity to be a specific value is calculated based on the calculated fluctuation rate. Then, the thermal process is conducted for the calculated processing time.

Abstract: A method for monitoring a semiconductor fabrication process creates a wafer of semiconductor chips. Each chip has a one or more diodes. Each diode is addressable as part of an array, corresponds to a physical location of the chip, and is connected in series to a stack. The stack is composed of one ore more vertical interconnects and metal contacts. The diode and associated stack of vertical interconnects is addressed, and the current through each of the stacks of vertical interconnects in an array is measured.

Abstract: The invention relates a substrate for a package for an electronic circuit and methods for packaging an electronic circuit with a substrate. The substrate comprises at least one conduction region and an activation region arranged within the substrate. The activation region is generally in contact with the conduction region and is configured to change its electrical resistance when activation occurs.

Abstract: In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.

Abstract: In a method and structure for semiconductor failure analysis, the structure comprises: a plurality of analytic fields disposed on a predetermined area of a semiconductor device; semiconductor transistors arranged in each of the analytic fields, the semiconductor transistors arranged in an array; wordlines arranged on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a first direction; and bitline structures on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a second direction, wherein the bitline structures are configured in different patterns in each of the plurality of analytic fields.

Abstract: The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.

Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10?18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

Abstract: A wiring structure including a wiring pattern formed in an insulation film on a substrate, a pattern for measurement which is formed in the insulation film on the substrate in a region different from a region where the wiring pattern is formed and is irradiated with measuring light, and a light transmission inhibiting film formed directly below the pattern for measurement, wherein the pattern for measurement is the same pattern as the wiring pattern, and the light transmission inhibiting film is made of a material having light transmissivity that is smaller than light transmissivity of a material of the insulation film forming the pattern for measurement.

Abstract: A sample that is processed to remove a top layer, e.g., using chemical mechanical polishing or etching, is accurately measured using multiple models of the sample. The multiple models may be constrained based on a pre-processing measurement of the sample. By way of example, the multiple models of the sample may be linked in pairs, where one pair includes a model simulating the pre-processed sample and another model simulating the post-processed sample with a portion of the top layer remaining, i.e., under-processing. Another pair of linked models includes a model simulating the pre-processed sample and a model simulating the post-processing sample with the top layer removed, i.e., the correct amount of processing or over-processing. The underlying layers in the linked model pairs are constrained to have the same parameters. The modeling process may use a non-linear regression or libraries.

Abstract: In a method and system for assembling a semiconductor device, a tray is configured to provide an array of bins arranged in m rows and n columns, where m and n are integers. The tray containing defect free singulated substrates is received from a substrate supplier for assembly. Each one of the defect free singulated substrates, which is disposed in a corresponding bin of the tray, is accessible in a concurrent or sequential manner, thereby enabling concurrent or sequential assembly of m*n ones of the defect free singulated substrate. The assembly process for the semiconductor device starting from the defect free singulated substrate includes die attach, wire bonding, mold press, laser marking, solder ball attach, and testing operations. Assembly of the defect free singulated substrates avoids material loss and increases manufacturing efficiency.

Abstract: A method for manufacturing a semiconductor device, includes; measuring a within-wafer distribution of a physical quantity; and etching the wafer so that the physical quantity get close to constant within the wafer. Alternatively, a method for manufacturing a semiconductor device, includes, measuring a within-wafer distribution of a physical quantity of at least one of a plurality of semiconductor layers provided in a wafer; determining a within-wafer distribution of etching amount for the at least one of the plurality of semiconductor layers based on the measured within-wafer distribution of the physical quantity; and etching the at least one of the plurality of semiconductor layers based on the determined within-wafer distribution of the etching amount so that the etching amount is locally varied within the wafer.

Abstract: Test structures for detecting defects arising from hybrid orientation technology (HOT) through detection of device leakage (gate leakage, junction leakage, and sub-threshold leakage), having at least one active region disposed in a re-grown region of a substrate: a layer of oxide; a layer of poly. Some test structures are dog-bone shaped test structure, tower shaped test structure, and inside-hole shaped. A method for detecting HOT defects involves measuring defect size and location in terms of device leakage, such as gate leakage, junction leakage, and sub-threshold leakage. HOT edge defect density and edge defect size distribution may be calculated, and the resulting defect information may be used to calibrate a defect yield model.

Abstract: A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.

Abstract: A wafer-level test module is disclosed to include a base layer having multiple first apertures spaced from one another at a pitch corresponding to the pitch of the image sensor chips of an integrated circuit wafer, a cover layer having second apertures respectively axially aimed at the first apertures, and an optical layer sandwiched between the base layer and the cover layer having multiple optical lenses of which the optical axes pass through the first apertures and the second apertures, so that when one image capturing device of the image sensor chips of an integrated circuit wafer is adjusted to the image plane of one of the optical lenses and the wafer-level test module is set in alignment with the integrated circuit wafer horizontally and vertically, then the effective test light can be simultaneously projected onto the image capturing devices of the respective image sensor chips through the wafer-level test module to achieve an effective wafer-level test on multiple image sensor chips of the integrated

Abstract: To provide a semiconductor device capable of being easily subjected to a physical test without deteriorating characteristics. According to a measuring method of a semiconductor device in which an element layer provided with a test element including a terminal portion is sealed with first and second films having flexibility, the first film formed over the terminal portion is removed to form a contact hole reaching the terminal portion; the contact hole is filled with a resin containing a conductive material; heating is carried out after arranging a wiring substrate having flexibility over the resin with which filling has been performed so that the terminal portion and the wiring substrate having flexibility are electrically connected via the resin containing a conductive material; and a measurement is performed.

Abstract: A coating and developing apparatus having a plurality of cassettes includes at least a step of acquiring, for each of all wafers retained in the cassettes, wafer attribute information associated with a cassette retaining that wafer and a process recipe, a step of acquiring inside-cassette information associated with the retained wafer, a step of acquiring information on a process recipe in an exposure apparatus directly from the exposure apparatus, and a step of determining a processing order for the plurality of wafers based on the attribute information, the inside-cassette information, process recipe information of the coating and developing apparatus which the coating and developing apparatus has, and the process recipe information of the exposure apparatus acquired from the exposure apparatus.

Abstract: The present invention provides a method and apparatus for dynamic adjustment of a sampling plan. The method includes accessing wafer electrical test data associated with at least one workpiece that has been processed by at least one processing tool. The method also includes determining, based on the wafer electrical test data, at least one sampling plan for at least one measurement device configured to measure at least one parameter associated with workpieces processed by the at least one processing tool.

Abstract: Disclosed is a system and method for providing an effective means for making it easy to identify which holes in an interface plate are to be populated with probes and which are to be left empty. This identification of holes or apertures in a plate is used most commonly an electrical probe testing plates where a probe array is set up and inserted though the plate. The problem is that it is very difficult to double check to see if all probes are installed. With a two-tone color identifier (or other techniques disclosed herein) it is easy to visually or machine read the probe plate for probe installation errors. The method employs coating the plate with a colorant and ablating colorant adjacent holes, which are either populated or empty, the difference being easy to spot.

Abstract: The present invention provides a surface inspection method and apparatus for inspecting a surface of a sample, in which a resistive film is coated on the surface, and a beam is irradiated to the surface having the resistive film coated thereon, to thereby conduct inspection of the surface of the sample. In the surface inspection method of the present invention, a resistive film having an arbitrarily determined thickness t1 is first coated on a surface of a sample. Thereafter, a part of the resistive film having the arbitrarily determined thickness t1 is dissolved in a solvent, to thereby reduce the thickness of the resistive film to a desired level. This enables precise control of a value of resistance of the resistive film and suppresses distortion of an image to be detected.

Abstract: A micromechanical sensor and a method for manufacturing same are described. A secure diaphragm restraint, independent of fluctuations in the cavern etching process due to the process technology, and a free design of the diaphragm are made possible by designing a suitable connection of the diaphragm in an oxide layer created by local oxidation. The micromechanical sensor includes, for example, a substrate, an external oxide layer formed in a laterally external area in the substrate, a diaphragm having multiple perforation holes formed in a laterally internal diaphragm area, a cavern etched in the substrate beneath the diaphragm, whereby the diaphragm is suspended in a suspension area of the external oxide layer which tapers toward connecting points of the diaphragm and the diaphragm is situated in its vertical height between a top side and a bottom side of the external oxide layer.

Abstract: Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.

Abstract: By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of electrical characteristics of the test metal region. Consequently, by means of the electrical characteristics, respective variations of the etch process may be identified.

Abstract: To generate a simulated diffraction signal, one or more values of one or more photoresist parameters, which characterize behavior of photoresist when the photoresist undergoes processing steps in a wafer application, are obtained. One or more values of one or more profile parameters are derived using the one or more values, of the one or more photoresist parameters. The one or more profile parameters characterize one or more geometric features of the structure. A simulated diffraction signal is generated using the one or more values of the one or more profile parameters. The simulated diffraction signal characterizes behavior of light diffracted from the structure. The generated simulated diffraction signal is associated with the one or more values of the one or more photoresist parameters.

Abstract: Targets or test structures used for measurements in semiconductor devices having long lines exceeding design rule limitations are divided into segments. In one embodiment, the segments have periodicity in a direction parallel to the length of the lines. In another embodiment, the segments of test structures in adjacent lines do not have periodicity in a direction parallel to the length of the lines. The lack of periodicity is achieved by staggering segments of substantially equal lengths in adjacent lines, or by dividing the lines into segments having unequal lengths. The test structures may be formed in scribe line regions or die regions of a semiconductor wafer.

Abstract: Selectable capacitors are used to modify performance characteristics of functional circuit elements of an integrated circuit (IC). In an embodiment, the decoupling capacitors are implemented as additional or alternative mounting pads on a surface of the IC. At least one selectable capacitor is provided for each IC circuit element, such as a logic network, whose operational characteristic(s) is predicted to be and is actually identified as sub-optimal through IC testing, particularly following a process change, a mask shrink, operation of the IC at higher clock frequency, or the like. Expensive redesign is avoided by selectively coupling capacitors into the IC circuit element as needed, under control of selector logic that is responsive to control signals. Methods of operation, as well as application of the apparatus to an electronic assembly and an electronic system, are also described.

Abstract: Embodiments of the present invention provide a test structure for inspection of integrated circuits. The test structure may be fabricated on a semiconductor wafer together with one or more integrated circuits. The test structure may include a common reference point for voltage reference; a plurality of voltage dropping devices being connected to the common reference point; and a plurality of electron-collecting pads being connected, respectively, to a plurality of contact points of the plurality of voltage dropping devices. A brightness shown by the plurality of electron-collecting pads during an inspection of the integrated circuits may be associated with a pre-determined voltage.

Abstract: In a positional offset measurement pattern unit formed in an insulating layer, a first interconnection is formed in the insulating layer. A via-plug is formed in the insulating layer so as to be electrically connected to the first interconnection. A second interconnection is formed in the insulating layer at substantially the same level as the first interconnection so as to be spaced from the first interconnection by a given distance. A voltage is applied between the first and second interconnections to measure a relative positional offset amount between the via-plug and the second interconnection.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter of the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: A semiconductor wafer includes a plurality of chip areas, a scribe line area, a bonding pad, a probing pad, and a pad connection wiring. The plurality of chip areas are configured to be arranged in a matrix form. The scribe line area is configured to separate the plurality of chip areas from each other. The bonding pad is configured to be connected with an external terminal. The probing pad is configured to be contacted with a probe wire. The pad connection wiring is configured to electrically connect the bonding pad to the probing pad. The bonding pad and the probing pad are located at a predetermined distance from each other in each of the plurality of chip areas. The pad connection wiring has a portion located in the scribe line area.

Abstract: A method for evaluating a semiconductor substrate is provided that can evaluate even a thin semiconductor substrate or a substrate with untreated surfaces, can evaluate a large quantity of semiconductor substrates for solar cells in a short time and can be used as in-line inspection in a production process of solar cells or the like. The method for evaluating a semiconductor substrate comprises a step of immersing a semiconductor substrate in an etching solution filled in a container, a step of irradiating the substrate being immersed in the etching solution with light via the etching solution to cause the substrate to emit photoluminescence, and a step of observing the emitted photoluminescence.