Abstract: A method to extract gate to source/drain and overlap capacitances is disclosed. A first capacitance of a first test key having a reference structure and a second capacitance of a second test key having a novel structure are measured. The second test key may comprise at least a gate formed on an insulation structure, at least a contact formed on the insulation structure aside, and a metal layer formed on the contact. Another embodiment of the second test key may comprise at least a gate formed on the semiconductor substrate, a contact formed aside, and a metal layer formed on the contact. Further another embodiment uses a test key comprising at least an elongated gate and an elongated doping region aside, and only one or a few contacts are formed on an end portion of the elongated doping region.

Abstract: The invention relates to a light emitting device comprising a substrate layer and a light conversion layer located on said substrate layer, whereby the light conversion layer is a polycrystalline ceramic layer, characterized in that the light conversion layer is positioned on the substrate layer by sintering.

Abstract: A method increases a reliability of packaged semiconductor integrated circuit dice by identifying one or more dice on a wafer having failed an electrical test. One or more failed dice are added to a character map. A first tier of buffer dice is added to the initial character map adjacent to each die on the character map. Both the failed dice and the first tier of buffer dice are indicated or marked, such as by inking, thereby indicating dice not requiring packaging. A wafer may include multiple die, with die corresponding to the die in the character map being marked. The marked die thus include die that have failed an electrical test plus die that may be likely to fail in the future due to their proximity to the failed die.

Abstract: A semiconductor-device manufacturing method includes: forming terminals on a wafer and across each of dicing lines along which the wafer is cut into a plurality of semiconductor chips; preparing a plurality of pre-cut substrates each including a substrate body capable of being cut along corresponding one of cutting lines into a pair of same structured substrate pieces, connection pads provided on a top surface of the substrate body, and external terminals formed on a bottom surface of the substrate body and connected to the connection pads; mounting the pre-cut substrates onto the wafer while the cutting lines of the pre-cut substrates match the dicing lines; and simultaneously dicing the wafer and the pre-cut substrates along the dicing lines matching the cutting lines.

Abstract: An SSO noise calculating unit estimates the amount of simultaneously operating signal noise caused by simultaneous operations of input/output pins peripheral to a power supply voltage pin as a center. A PLL jitter calculating unit estimates the amount of jitter occurring at the power supply voltage pin by using as an input the estimated amount of simultaneously operating signal noise, and by referencing a correlation between the amount of simultaneously operating signal noise and the amount of jitter, which indicates a correlation calculated beforehand between the amount of simultaneously operating signal noise and the amount of jitter.

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract: Methods are provided for calibrating a process for growing an epitaxial silicon-comprising film and for growing an epitaxial silicon-comprising film. One method comprises epitaxially growing a first silicon-comprising film on a first silicon substrate that has an adjacent non-crystalline-silicon structure that extends from said first silicon substrate. The step of epitaxially growing uses hydrochloric acid provided at a first hydrochloric acid flow rate for a first time period. A morphology of the first film relevant to the adjacent non-crystalline-silicon structure is analyzed and a thickness of the first film is measured. The first flow rate is adjusted to a second flow rate based on the morphology of the first film. The first time period is adjusted to a second time period based on the second flow rate and the thickness. A second silicon-comprising film on a second silicon substrate is epitaxially grown for the second time period using the second flow rate.

Abstract: An overmolded electronic assembly is provided having a circuit board with electronic devices and a diagnostic connection. The diagnostic connection includes electrical conductors having a distal end projecting above a first side of the circuit board, for example, circuit pads having solder thereon or conductive pins oriented substantially perpendicular to the circuit board. The electrical conductors are overmolded with sealing material along with the other electronic devices and circuit board area. The encapsulation or sealing material overlying the electrical conductors is removed from the outside surface down to at least the distal end of the electrical conductors. The sealing material may be removed, for example, by mechanical cutting, laser cutting, or high pressure jet erosion, for example, by a high pressure water or liquid nitrogen stream.

Abstract: An embodiment of the present invention is a technique to form stress sensors on a package in situ. A first array of carbon nanotubes (CNTs) aligned in a first orientation is deposited at a first location on a substrate or a die in a wafer. The first array is intercalated with polymer. The first polymer-intercalated array is covered with a protective layer. A second array of CNTs aligned in a second orientation is deposited at a second location on the substrate or the die. The second array is intercalated with polymer.

Abstract: Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.

Abstract: There are provided a semiconductor device having a pattern which allows electric failures to be sensitively detected at high speeds, and a method of testing the same. In one embodiment, the semiconductor device comprises a pair of row wires including a plurality of first wires arranged in a first layer at predetermined intervals in a row direction, where the first wires have ends connected to second wires arranged in a second layer at a predetermined intervals through vias, and the first wire and second wire are at the same potential. In the pair of row wires, a first wire positioned at a right end of one row wire is connected to a first conductor, and a first wire positioned at a left end in the other row wire is connected to a second conductor. By sequentially scanning the first conductor and second conductor using an electron beam, a change in the amount of emitted secondary electrons due to a difference in potential between these conductors is detected to detect electric anomalies.

Abstract: A deposition apparatus includes: a first electrode for placing a processing object; a second electrode for generating plasma with the first electrode, the second electrode being opposed to the first electrode; and a heat flow control heat transfer part for drawing heat from the processing object to generate a heat flow from a central area to a peripheral area of the processing object.

Abstract: A hi-fix board, a test tray, a test handler, and a packaged chip manufacturing method are provided. The hi-fix board includes: test sockets to which packaged chips to be tested are connected; and a main frame in which the test sockets are disposed in at least one first area to form an a×b matrix (where a and b are integers greater than 0) and the test sockets are disposed in at least one second area to form a c×d matrix (where c is an integer greater than a and d is an integer greater than 0). By allowing the test tray to contain more packaged chips at a time and minimizing a difference in length between a horizontal direction and a vertical direction, it is possible to reduce the index time. By allowing all the packaged chips contained in a test tray to be subjected to a testing process at the same time, it is possible to reduce the time for the testing process and to enhance the stability.

Abstract: Test methods and components are disclosed for testing the quality of lift-off processes in wafer fabrication. A wafer is populated with one or more test components along with the functional components. These test components are fabricated with holes in an insulation layer that is deposited between conductive layers, where the holes were created by the same or similar lift-off process that is used to fabricate the functional components on the wafer. The test components may then be measured in order to determine the quality of the holes created by the lift-off process. The quality of the lift-off process used to fabricate the functional components may then be determined based on the quality of the holes in the test components.

Abstract: A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The dielectric layer includes a grating pattern and a resistivity test line inset in a transparent region. Radiation is then directed onto the dielectric layer so that some of the radiation is transmitted through the transparent region to the reflective layer. A radiation pattern is then detected from the radiation reflected and scattered by the metal grating pattern. The radiation pattern is analyzed to determine a first dimensional information. Then the resistance of the resistivity test line is measured, and that resistance is analyzed to determine a second dimensional information. The first and second dimensional informations are then compared.

Abstract: A method for making a testable sensor assembly is provided. The method includes forming a first sensor array on a first substrate having a first side and a second side, wherein the first sensor array is formed on the first side of the first substrate, coupling a first semiconductor wafer having a first side and a second side to the first sensor array, wherein the first side of the first semiconductor wafer is coupled to the first sensor array, thinning one of the second side of the first substrate or the second side of the first semiconductor wafer, and testing the first sensor array to identify operational and non-operational units in the testable sensor assembly before integration of the sensor assembly with interface electronics.

Abstract: A system in package (10) has a, preferably wireless, test controller (20) for testing each die (30) after it has bee mounted onto the substrate of the system in package (10), and a faulty die (30) is repaired before a next die (30) is mounted onto the substrate (15). This way, the system in package (10) can be tested during the intermediate stages of its manufacturing, thus ensuring that all dies (30) function correctly before sealing the dies in the single package. Consequently, a method for manufacturing a system in package (10) is obtained that has an improved yield compared to known manufacturing methods.

Abstract: A processing condition inspection method of a damage recovery process for reforming a film having OH groups generated by damages from a predetermined process by using a processing gas includes preparing a substrate having an OH group containing resin film, measuring an initial film thickness of the OH group containing resin film, performing a damage recovery process on the substrate after measuring the initial film thickness, measuring a film thickness of the OH group containing resin film after the damage recovery process, calculating a film thickness difference of the OH group containing resin film before and after the damage recovery process, and determining whether processing conditions of the damage recovery process are appropriate or inappropriate based on the film thickness difference.

Abstract: A method for the fabrication of a semiconductor structure that includes areas that have different crystalline orientation and semiconductor structure formed thereby. The disclosed method allows fabrication of a semiconductor structure that has areas of different semiconducting materials. The method employs templated crystal growth using a Vapor-Liquid-Solid (VLS) growth process. A silicon semiconductor substrate having a first crystal orientation direction is etched to have an array of holes into its surface. A separation layer is formed on the inner surface of the hole for appropriate applications. A growth catalyst is placed at the bottom of the hole and a VLS crystal growth process is initiated to form a nanowire. The resultant nanowire crystal has a second different crystal orientation which is templated by the geometry of the hole.

Abstract: Methods for processing a substrate in a processing chamber using dual RF frequencies are provided herein. In some embodiments, a method of processing a substrate includes forming a plasma of a polymer forming chemistry to etch a feature into a substrate disposed on a substrate support in a process chamber while depositing a polymer on at least portions of the feature being etched. A low frequency and a high frequency RF signal are applied to an electrode disposed in the substrate support. The method further includes controlling the level of polymer formation on the substrate, wherein controlling the level of polymer formation comprises adjusting a power ratio of the high frequency to the low frequency RF signal.

Abstract: Disclosed are methods of manufacturing a flash memory device. The method can include performing a first test on memory banks of chips on a wafer to record an availability of the banks; performing an inking process on each of the chips according to a number of available banks in the chip; performing a sawing process to divide the chips mounted on the wafer; packaging the divided chips according to the number of available banks in the chip; and performing a verification test on the packaged chips.

Abstract: The present invention relates to a process for preparing a thinned silicon wafer for electrical testing, the thinned silicon wafer comprising at least one circuit design and at least one through-silicon via or hole; the process comprising temporarily attaching the thinned silicon wafer to a mechanical handler by means of an electrically conductive polymeric adhesive material.

Abstract: A device is described, including a first diffusion region having a first terminal, a second diffusion region having a second terminal, and a channel region disposed between the first diffusion region and the second diffusion region. Further, the first terminal and the second terminal are offset to enable a non-Manhattan current flow. A system is also described, including the previously described device and a second transistor. The pathway for the flow of the majority of the current carriers in the device defines a first direction. The second transistor also has at least two terminals, and a pathway for a majority of current carriers between the two terminals defines a second direction. The angle between the first direction and the second direction is nonzero and acute.

Abstract: A manufacturing method makes memory modules from partially-good DRAM chips soldered to its substrate. The partially-good DRAM chips have a number of defective memory cells that is below a test threshold, such as 10%. Packaged DRAM chips are optionally pre-screened and considered to pass when the number of defects found is less than the test threshold. A defect table is created during testing and written to a serial-presence-detect electrically-erasable read-only memory (SPD-EEPROM) on the memory module. The memory module is finally tested on a target-system tester that reads the defect table during booting, and redirects memory access to defective memory locations identified by the defect table. The memory modules may be burned in or tested at various temperatures and voltages to increase reliability.

Abstract: A chip packaging process integrates a burn-in test or a high temperature test to simplify overall packaging and testing process flow. One or more chips are disposed on one or more units of a substrate strip where the substrate strip has a plurality of electrical open sections at the plating lines to electrically isolate the external pads between different units. After electrical connection and encapsulation, a burn-in test is executed at the same time of a post mold curing step, with a high-temperature testing if necessary. Therefore, the chips on the substrate strip has been gone through the burn-in test during the encapsulant is completely cured at the post mold curing step and the burn-in test is finished before the singulation step to reduce the overall testing time.

Abstract: A method for wafer manufacturing process abnormalities detection, the method includes: generating a classifier in response to compression based similarities between relevant wafer manufacturing process information of pairs of wafers; and utilizing the classifier to detect wafer manufacturing process abnormalities.

Abstract: Embodiments of the invention provide a method, structure, service, etc. for variable overlap of dummy shapes for improved rapid thermal anneal uniformity. A method of providing uniform temperatures across a limited region of a wafer during a rapid thermal anneal process comprises determining a first reflectivity in a first portion of the limited region by measuring a density of first structures in the first portion. Next, the method determines a second reflectivity in a second portion of the limited region by measuring a density of second structures in the second portion. Specifically, the first structures comprise diffusion fill shapes and polysilicon conductor fill shapes (non-active dummy structures); and, the second structures comprise active circuit structures.

Abstract: A semiconductor device includes: n transistor elements; n resistive elements; and n capacitive elements, each kind of elements coupled in series between the first and second terminals. The gate of each transistor element has a gate pad, and each transistor element includes transistor pads disposed on both sides. Each resistive element includes resistive pads disposed on both sides. Each capacitive element includes capacitive pads disposed on both sides. The gate pad other than the first stage transistor element, a corresponding resistive pad, and a corresponding capacitive pad are electrically coupled. One transistor pad, one resistive pad, and one capacitive pad in the first stage are electrically coupled. One transistor pad, one resistive pad, and one capacitive pad in the n-th stage are electrically coupled.

Abstract: An imaging device and method of a bonding apparatus in which the imaging device includes: a high-magnification optical system having first and second high-magnification optical paths that extend to multiple imaging planes through a high-magnification lens and have different optical path lengths from the high-magnification lens to the respective imaging planes correspondingly to multiple subject imaging ranges which are at different distances from the high-magnification lens; and a low-magnification optical system having a low-magnification optical path that extends to an imaging plane through a low-magnification lens and having a field of view wider than those of the high-magnification optical paths. The imaging elements on the respective imaging planes in the high-magnification optical system are adapted to image semiconductor chips, while the imaging element on the imaging plane in the low-magnification optical system is adapted to image a lead frame.

Abstract: A measuring device measures a gate length of a plurality of gate electrodes formed on a wafer. A calculation device calculates data of an ion implantation dosage for making uniform a threshold voltage in a wafer surface on the basis of distribution of the gate length in a wafer surface measured by the measuring device. The ion implantation device implants ions into the wafer on the basis of the data of the ion implantation dosage calculated by the calculation device.

Abstract: A process (300) is disclosed to measure predetermined wavelength reflectance spectra of a photo resist coated wafer (305,310,315,320) at a nominal thickness. After coating, the predetermined wavelength reflectance (325,330) is measured and the peak heights and valleys in the vicinity of the predetermined wavelength are tabulated. The relative swing ratio is computed (335) as the average peak height of the spectra at the exposure wavelength. This relative swing ratio is then compared to similar computations on other processes to determine which provides the best critical dimension (CD) control.

Abstract: A method of fabricating a light emitting device having a specific target color, CIE xy, of emitted light is described. The device comprises a light emitting diode that is operable to emit light of a first wavelength range and at least one phosphor material which converts at least a part of the light into light of a second wavelength range wherein light emitted by the device comprises the combined light of the first and second wavelength ranges. The method comprises: depositing a pre-selected quantity of the at least one phosphor material on a light emitting surface of the light emitting diode; operating the light emitting diode; measuring the color of light emitted by the device; comparing the measured color with the specific target color; and depositing and/or removing phosphor material to attain the desired target color.

Abstract: According to one embodiment of the present invention, a method of testing a memory device including a memory cell array is provided, the method including: dividing the memory cell array into a plurality of memory cell array subunits, each memory cell array subunit including a plurality of resistivity changing memory cells; simultaneously testing all resistivity changing memory cells of a memory cell array subunit using a common testing signal; and repeating the testing for all further memory cell array subunits.

Abstract: A method of in-situ monitoring of a plasma doping process includes generating a plasma comprising dopant ions in a chamber proximate to a platen supporting a substrate. A platen is biased with a bias voltage waveform having a negative potential that attracts ions in the plasma to the substrate for plasma doping. A dose of ions attracted to the substrate is measured. At least one sensor measurement is performed to determine the condition of the plasma chamber. In addition, at least one plasma process parameter is modified in response to the measured dose and in response to the at least one sensor measurement.

Abstract: Measuring surface profiles of structures on integrated circuits is difficult when feature sizes are less than 100 nanometers. Atomic force microscopy provides surface profile measurement capability on flat horizontal surfaces, but has difficulty with three-dimensional structures such as MOS transistor gates, contact and via holes, interconnect trenches and photoresist patterns. An atomic force microscopy probe with two atomically sharp tips configured to facilitate measurements of three-dimensional structures is disclosed. A method of making such measurements using the disclosed probe and a method of fabricating an IC encompassing the method are also claimed.

Abstract: In a method for measuring an amount of strain of a bonded strained wafer, at least one strained layer is formed on a single crystal substrate. The bonded strained wafer is measured with respect to two asymmetric diffraction planes with diffraction plane indices (XYZ) and (?X?YZ) by an X-ray diffraction method, a reciprocal lattice space map is created from the measured data, and the amount of strain of the strained layer is calculated from the peak positions for the respective diffraction planes of the single crystal substrate and the strained layer appearing on the reciprocal lattice space map. Thereby, amounts of strain in the horizontal direction and in the vertical direction of the strained layer can be measured in a shorter time and more simply.

Abstract: A diagnostic method of and computer system for root-cause analysis of performance variations of FETs in integrated circuits and a method and computer system for monitoring a field effect transistor manufacturing process. The diagnostic method includes measuring source currents in the linear and saturated regions of two FETs, calculating ratios of the source currents in the linear and saturated regions for the and two FETs and comparing the ratios of the two FETs to determine a probable root cause for a performance variation between the two FETs. One of the FETs has a known good performance.

Abstract: Methods of assembling a chip package are disclosed that employ heat from test pattern operation of the chip to cure a thermal interface material. The methods may also simultaneously verify thermal performance of the package using the heat from test pattern operation. Further, the heat may be used to cure the sealing material and/or underfill material, where they are used.

Abstract: A semiconductor wafer is manufactured in such a way that a main surface of a semiconductor substrate is partitioned into a plurality of semiconductor element forming regions defined by scribing regions, wherein at least one pattern for measuring a width of a cut region and its positional shift is formed in proximity to a peripheral portion of the semiconductor substrate on a scribing line. The pattern is constituted by a plurality of micro patterns that are aligned in a reverse V-shape to traverse the scribing line and a pair of elongated patterns that partially overlap seal rings formed in both sides of the scribing line. It is possible to form a channel whose width is larger than the width of the cut region on the backside of the semiconductor substrate in correspondence with the scribing region in order to avoid the formation of chipping, cracks, and burrs during cutting.

Abstract: A test key for checking an interconnect structure is described, including a contiguous metal line and multiple conductive plugs on the contiguous metal line, wherein one end of each plug contacts with the contiguous metal line. The other end of at least one plug is not connected to any conductor. In addition, the two ends of the contiguous metal line are connected to different voltages.

Abstract: A method for profiling a bead of encapsulant extending along an edge of a die mounted to a supporting structure, by depositing a bead of encapsulant onto wire bonds along the edge of the die, positioning a profiling surface over the die at a predetermined spacing from the die, moving the profiling surface across the bead before the bead of encapsulant has cured to reshape the bead profile and, curing the bead of encapsulant. The invention has found that the encapsulant can be effectively shaped by a profiling surface without stripping the encapsulant from the wire bonds. The normally convex-shaped upper surface of the encapsulant bead can be pushed to one side of the bead with the profiling surface. With a lower encapsulant bead, the active surface can be brought into closer proximity with another surface without making contact. For example, the nozzle array on a printhead IC can be 300 microns to 400 microns from the paper path.

Abstract: A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.

Abstract: A substrate processing apparatus has a fluid supply means 20 for supplying fluid to a substrate W and a fluid collection means 21 for collecting the fluid in the vicinity of the substrate W, the fluid supply means 20 having a fluid spurt section 20a, the fluid collection means 21 having a fluid suction section 21a opening in the vicinity of the fluid spurt section 20a. Since the fluid collection means 21 suctions and collects the fluid floating around the substrate W as a result of the liquid having been supplied from the fluid spurt section 20a to the substrate W, it is possible to prevent the substrate W from being contaminated after the substrate W being processed with the fluid supplied from the fluid supply means 20.

Abstract: A method for manufacturing an MEMS device is provided. The method includes steps of a) providing a first substrate having a concavity located thereon, b) providing a second substrate having a connecting area and an actuating area respectively located thereon, c) forming plural microstructures in the actuating area, d) mounting a conducting element in the connecting area and the actuating area, e) forming an insulating layer on the conducting element and f) connecting the first substrate to the connecting area to form the MEMS device. The concavity contains the plural microstructures.

Abstract: A bonding agent sticking inspection apparatus includes a photographing section, a movement section, and a control section. The photographing section photographs an image of a substrate. The image includes a sticking expected range indicating a range in which a bonding agent should be positioned. The control section controls the photographing section and the movement section, sets an inspection region having a width equal to the pitch between electrodes in an entire edge part in a direction in which the electrodes are arranged in a peripheral edge part of the sticking expected range in the image, detects a ratio of a nicked part of the bonding agent to the inspection region, and judges whether or not an abnormality is present in the bonding agent on the basis of a comparison between the ratio of the nicked part and a threshold set in advance.

Abstract: A liquid crystal display (LCD) panel simplifying its testing and manufacturing. The LCD panel includes (formed on a substrate) gate lines, data lines, and pixels including pixel transistors. The LCD panel further includes a plurality test transistors (e.g., data test transistors for driving the odd and even data lines) formed in a package region of a driving IC (integrated circuit) configured to drive the data lines. The plurality of test transistors may be selectively activated (turned ON) during testing before the driving integrated circuit (Driver IC package) is attached (e.g., fixed) to the driving IC package region. The LCD panel may further include a plurality of gate test transistors configured to drive the odd and even gate lines.

Abstract: The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.

Abstract: An electro chemical deposition system is described for forming a feature on a semiconductor wafer. The electro chemical deposition is performed by powering electrodes that includes a cathode, an anode and a plurality of electrically independent auxiliary electrodes.

Abstract: A semiconductor device includes a plurality of wiring layers, a plurality of via layers, and a plurality of electrode pads. The electrode pads are circularly connected to each other through the wiring layers and the via layers.

Abstract: A testing structure, and method of using the testing structure, where the testing structure comprised of at least one of eight test structures that exhibits a discernable defect characteristic upon voltage contrast scanning when it has at least one predetermined structural defect. The eight test structures being: 1) having an Active Area (AA)/P-N junction leakage; 2) having an isolation region to ground; 3) having an AA/P-N junction and isolation region; 4) having a gate dielectric leakage and gate to isolation region to ground; 5) having a gate dielectric leakage through AA/P-N junction to ground leakage; 6) having a gate dielectric to ground and gate/ one side isolation region leakage to ground; 7) having an oversized gate dielectric through AA/P-N junction to ground leakage; and 8) having an AA/P-N junction leakage gate dielectric leakage.