Abstract: There is provided a magnetic memory device which has a small switching current for a writing line and which has a small variation therein. A method for producing such a magnetic memory device includes: forming a magnetoresistive effect element; forming a first insulating film so as to cover the magnetoresistive effect element; forming a coating film so as to cover the first insulating film; exposing a top face of the magnetoresistive effect element; forming an upper writing line on the magnetoresistive effect element; exposing the first insulating film on a side portion of the magnetoresistive effect element by removing a part or all of the coating film; and forming a yoke structural member so as to cover at least a side portion of the upper writing line and so as to contact the exposed first insulating film on the side portion of the magnetoresistive effect element.

Abstract: A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate includes a plurality of diffusion regions that are each formed between a pair of planar select gates. In a vertical embodiment, the diffusion regions are formed at the bottom of the trenches and the tops of the mesas formed by the trenches. An enriched region is formed in the substrate adjacent to and substantially surrounding each diffusion region in the substrate. Each enriched region has a matching conductivity type with the substrate. A gate insulator stack is formed over the substrate and each of the plurality of select gates. A word line is formed over the gate insulator stack.

Abstract: A magnetic memory is composed of: a magnetoresistance element including a free magnetic layer; a first interconnection extending in a first direction obliquely to an easy axis of the free magnetic layer; a second interconnection extending in a second direction substantially orthogonal to the first direction; and a write circuit writing data into the free magnetic layer through developing a first write current on the first interconnection, and then developing a second write current on the second interconnection with the first write current turned on. The free magnetic layer includes: first to N-th ferromagnetic layers and first to (N?1)-th non-magnetic layers with N being equal to or more than 4, the i-th non-magnetic layer being disposed between the i-th and (i+1)-th ferromagnetic layers with i being any of natural numbers equal to or less than N?1.

Abstract: A method for incorporating magnetic materials in a semiconductor manufacturing process includes manufacturing a semiconductor device including interlayers and dielectric layers, depositing a magnetic layer above a semiconductor device and forming metallized contacts for connecting interlayers of the semiconductor device. With the method of the present invention, the deposition of the magnetic material is integrated with the semiconductor manufacturing process.

Abstract: A tunnel barrier in proximity with a layer of a rare earth element-transition metal (RE—TM) alloy forms a device that passes negatively spin-polarized current. The rare earth element includes at least one element selected from the group consisting of Gd, Tb, Dy, Ho, Er, Tm, and Yb. The RE and TM have respective sub-network moments such that the absolute magnitude of the RE sub-network moment is greater than the absolute magnitude of the TM sub-network moment. An additional layer of magnetic material may be used in combination with the tunnel barrier and the RE—TM alloy layer to form a magnetic tunnel junction. Still other layers of tunnel barrier and magnetic material may be used in combination with the foregoing to form a flux-closed double tunnel junction device.

Abstract: A magnetic tunnel junction (MTJ), which is useful in magnetoresistive random access memories (MRAMs), has a free layer which is a synthetic antiferromagnet (SAF) structure. This SAF is composed of two ferromagnetic layers that are separated by a coupling layer. The coupling layer has a base material that is non-magnetic and also other materials that improve thermal endurance, control of the coupling strength of the SAF, and magnetoresistance ratio (MR). The preferred base material is ruthenium and the preferred other material is tantalum. Furthering these benefits, cobalt-iron is added at the interface between the tantalum and one of the ferromagnetic layers. Also the coupling layer can have even more layers and the materials used can vary. Also the coupling layer itself can be an alloy.

Abstract: A scheme for aligning opaque material layers of a semiconductor device. Alignment marks are formed in a via level of the semiconductor device. The alignment marks are formed using a separate lithography mask, and may have about the same length as vias formed in the via layer. The alignment marks comprise trenches that are not filled with material and are not exposed to a CMP process. An opaque material layer is deposited, and depressions are formed in the opaque material layer over the alignment mark trenches. The depressions in the opaque material layer are used to align a lithography process to open the opaque material layer over alignment marks in an underlying metallization layer. The alignment marks in the metallization layer are then used to align the lithography process used to pattern the opaque material layer.

Abstract: An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) cell is formed on a conducting lead and magnetic keeper layer that is capped by a sputter-etched Ta layer. The Ta capping layer has a smooth surface as a result of the sputter-etching and that smooth surface promotes the subsequent formation of a lower electrode (pinning/pinned layer) with smooth, flat layers and a radical oxidized (ROX) Al tunneling barrier layer which is ultra-thin, smooth, and to has a high breakdown voltage. A seed layer of NiCr is formed on the sputter-etched capping layer of Ta. The resulting device has generally improved performance characteristics in terms of its switching characteristics, GMR ratio and junction resistance.

Abstract: A method of forming a magnetic random access memory (MRAM) using a sacrificial cap layer on top of the memory cells and the structure resulting therefrom are described. A plurality of individual magnetic memory devices with cap layers are fabricated on a substrate. A continuous first insulator layer is deposited over the substrate and the magnetic memory devices. Portions of the first insulator layer are removed at least over the magnetic memory devices and then the cap layers are selectively removed from the magnetic memory devices, thus exposing active top surfaces of the magnetic memory devices. The top surfaces of the magnetic memory devices are recessed below the top surface of the first insulator layer. Top conductors are formed in contact with the active top surfaces of the magnetic memory devices. In an illustrated embodiment, spacers are also formed along the sides of the magnetic memory devices before the first insulator layer is deposited.

Abstract: Methods for patterning a magnetic cell junction and a topography used for and/or resulting from such methods are provided. In particular, a method is provided which includes etching portions of a topography adjacent to a patterned photoresist layer to a level within a cap film of the topography, removing etch residues from the topography and subsequently etching the remaining portions of the cap film to expose an uppermost magnetic layer. Another method is provided which includes patterning a dielectric mask layer above a patterned upper portion of a magnetic cell junction and ion milling a lower portion of the magnetic cell junction in alignment with the mask layer. An exemplary topography which may result and/or may be used for such methods includes a stack of layers having a dual layer cap film arranged above at least two magnetic layers spaced apart by a tunneling layer.

Abstract: In an MRAM and method for fabricating the same, the MRAM includes a semiconductor substrate, a transistor formed on the semiconductor substrate, an interlayer dielectric formed on the semiconductor substrate to cover the transistor, and first and second MTJ cells formed in the interlayer dielectric to be coupled in parallel with a drain region of the transistor, wherein the first MTJ cell is coupled to a first bit line formed in the interlayer dielectric and the second MTJ cell is coupled to a second bit line formed in the interlayer dielectric, and wherein a data line is formed between the first MTJ cell and a gate electrode of the transistor to be perpendicular to the first bit line and the second bit line. The MRAM provides high integration density, sufficient sensing margin, high-speed operation and reduced noise, requires reduced current for recording data and eliminates a voltage offset.

Abstract: An array of conductive lines for MRAM circuits wherein at least one set of mutually parallel conductive traces is tilted with respect to being perpendicular with a corresponding set of mutually parallel conductive traces wherein individual conductive traces within the sets intersect adjacent individual MRAM cells and wherein the tilting of the at least one set of conductive traces acts to induce both a vertical and horizontal component of a magnetic field such that the net vector addition of magnetic fields induced by the sets of conductive traces is greater than the untilted or perpendicular configuration so as to induce a greater net magnetic field to effect more reliable switching of the underlying MRAM cells. The tilted array also enables reducing the current supplied by the conductive traces while maintaining a comparable net magnetic field to the untilted configuration.

Abstract: A magnetoresistive effect device includes a first ferromagnetic layer having a fixed magnetization direction and having magnetic moment ml per unit area. A nonmagnetic layer contacts with the first ferromagnetic layer and has an amplitude hi of roughness of an interface between the nonmagnetic layer and the first ferromagnetic layer. A second ferromagnetic layer contacts with the nonmagnetic layer, has a fixed magnetization direction, has magnetic moment m2 per unit area which is smaller than the magnetic moment m1, and has an amplitude h2 of roughness of an interface between the second ferromagnetic layer and the nonmagnetic layer. A barrier layer contacts with the second ferromagnetic layer, and has an amplitude h3, which is smaller than the amplitudes h1 and h2, of roughness of an interface between the barrier layer and the second ferromagnetic layer. A third ferromagnetic layer contacts with the barrier layer and has a variable magnetization direction.

Abstract: Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the ferromagnetic film. The magnetic dipole aligns with the long axis of each structure. The structures can be formed in a variety of ways. For example, the ferromagnetic film can be applied to a seed layer having a textured surface. Alternatively, the ferromagnetic film can be stressed to generate the textured structure. Chemical mechanical polishing also can be used to generated the structures.

Abstract: A method of fabricating a nonvolatile memory is provided. The method includes forming a bottom dielectric layer, a charge trapping layer, a top dielectric layer and a conductive layer on the substrate sequentially. Portions of conductive layer, top dielectric layer, charge trapping layer and bottom dielectric layer are removed to form several trenches. An insulation layer is formed in the trenches to form a plurality of isolation structures. A plurality of word lines are formed on the conductive layer and the isolation structures. By using the word lines as a mask, portions of bottom dielectric layer, charge trapping layer, top dielectric layer, conductive layer and isolation structures are removed to form a plurality of devices. The bottom oxide layer has different thickness on the substrate so that these devices can be provided with different performance. These devices serve as memory cells with different character or devices in periphery region.

Abstract: A double-decker MRAM cell is provided, including a stacked structure of first and second magnetic tunnel junctions. Each magnetic tunnel junction includes first and second free and fixed magnetic regions made of magnetic material separated by a first and second tunneling barrier layers made of non-magnetic material. The fixed magnetic regions are pinned by at least one pinning layer. The first and second fixed magnetizations are oriented in a same magnetic anisotropy axis and are inclined under an angle relative to at least one of said first and second free magnetizations.

Abstract: Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.

Abstract: The present disclosure provides an improved magnetic memory cell. The magnetic memory cell includes a switching element and two magnetic tunnel junction (MTJ) devices. A conductor connects the first and second MTJ devices in a parallel configuration, and serially connecting the parallel configuration to an electrode of the switching element. The resistance of the first MTJ device is different from the resistance of the second.

Abstract: A method is provided for fabricating a fixed layer for a MRAM device. The method includes providing the fixed layer. The fixed layer includes an antiferromagnetic pinning layer over a substrate and a ferromagnetic pinned layer over the pinning layer, the pinned layer having a first thickness. The fixed layer further includes a spacer layer over the pinned layer, and a ferromagnetic reference layer over the spacer layer, the reference layer having a second thickness. The method further includes annealing the fixed layer using a temporal temperature/magnetic field profile, the profile having a maximum magnetic field magnitude (Hanneal). The profile is selected based on the first thickness of the pinned layer and the second thickness of the reference layer.

Abstract: Magnetoelectronic memory element structures and methods for making such structures using a barrier layer as a material removal stop layer are provided. The methods comprise forming a digit line disposed at least partially within a dielectric layer. The dielectric material layer overlies an interconnect stack. A void space is etched in the dielectric layer to expose the interconnect stack. A conductive-barrier layer having a first portion and a second portion is deposited. The first portion overlies the digit line and the second portion is disposed within the void space and in electrical communication with the interconnect stack. A memory element layer is formed overlying the first portion and an electrode layer is deposited overlying the memory element layer. The electrode layer and the memory element layer are then patterned and etched.

Abstract: A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering layer includes tantalum. A first mask layer is formed over the covering layer followed by a second mask layer. The first mask layer and second mask layer are etchable by the same etching process. The first and second mask layer are etched. Etch residue is removed from the first and second mask layers. The first mask layer is then selectively removed and the second mask layer remains.

Abstract: A method is provided for fabricating a fixed layer for a MRAM device. The method includes providing the fixed layer. The fixed layer includes an antiferromagnetic pinning layer over a substrate and a ferromagnetic pinned layer over the pinning layer, the pinned layer having a first thickness. The fixed layer further includes a spacer layer over the pinned layer, and a ferromagnetic reference layer over the spacer layer, the reference layer having a second thickness. The method further includes annealing the fixed layer using a temporal temperature/magnetic field profile, the profile having a maximum magnetic field magnitude (Hanneal). The profile is selected based on the first thickness of the pinned layer and the second thickness of the reference layer.

Abstract: A magnetic memory device includes first and second magnetoresistance elements. The first and second magnetoresistance elements store information and are provided apart from each other in a first direction. A first wiring to apply a magnetic field to the first and second magnetoresistance elements is provided along the first direction. A first magnetic circuit is formed along a side of the first wiring and has a notch in its portion between the first and second magnetoresistance elements.

Abstract: A method is provided for fabricating a fixed layer for a MRAM device. The method includes providing the fixed layer. The fixed layer includes an antiferromagnetic pinning layer over a substrate and a ferromagnetic pinned layer over the pinning layer, the pinned layer having a first thickness. The fixed layer further includes a spacer layer over the pinned layer, and a ferromagnetic reference layer over the spacer layer, the reference layer having a second thickness. The method further includes annealing the fixed layer using a temporal temperature/magnetic field profile, the profile having a maximum magnetic field magnitude (Hanneal). The profile is selected based on the first thickness of the pinned layer and the second thickness of the reference layer.

Abstract: Magnetoresistive random access memory (MRAM) is used to provide in-pixel memory circuits for display devices. A memory circuit (25) comprises memory elements, for storing a drive setting, and a read-out circuit, for example a flip-flop circuit (64), for reading-out the stored drive setting. The memory elements comprise two MRAMs (60, 62), each coupled to a respective input of the flip-flop circuit (64). A drive circuit (26) is coupled to the read-out circuit and a pixel display electrode (27) for driving the pixel display electrode (27) dependent upon the read-out drive setting with drive current that does not pass through the MRAMs (60, 62). A display device (1) is provided comprising a plurality of pixels (20) each associated with one such memory circuit (25) and drive circuit (26).

Abstract: According to an aspect of the present invention, there is disclosed a magnetic resistive element comprising a first magnetic layer whose magnetized state changes in accordance with data, a nonmagnetic layer disposed on the first magnetic layer, and a second magnetic layer which is disposed on the nonmagnetic layer and whose magnetized state is fixed, wherein the first magnetic layer has a cross shape in which a maximum length of a first direction is L1 and a maximum length of a second direction crossing the first direction at right angles is L2, and the second magnetic layer has a tetragonal shape in which the maximum length of the first direction is L3 (?L1) and the maximum length of the second direction is L4 (<L2).

Abstract: A method is provided for fabricating a fixed layer for a MRAM device. The method includes providing the fixed layer. The fixed layer includes an antiferromagnetic pinning layer over a substrate and a ferromagnetic pinned layer over the pinning layer, the pinned layer having a first thickness. The fixed layer further includes a spacer layer over the pinned layer, and a ferromagnetic reference layer over the spacer layer, the reference layer having a second thickness. The method further includes annealing the fixed layer using a temporal temperature/magnetic field profile, the profile having a maximum magnetic field magnitude (Hanneal). The profile is selected based on the first thickness of the pinned layer and the second thickness of the reference layer.

Abstract: A method of fabricating an MRAM cell including providing a workpiece having at least one magnetic tunnel junction (MTJ) formed thereon, forming an insulating layer made of non-conductive, isolating material over the at least one MTJ, using a damascene process to form at least two adjacent first trenches in the insulating layer, filling the first trenches in the insulating material with a conductive material and polishing the conductive material to form conductive lines, etching of at least a second trench in the insulating layer in between the conductive lines, depositing a ferromagnetic liner material at least over the conductive lines and the second trench; and removing of the ferromagnetic liner material from the bottom surface of said second trench to form ferromagnetic liners of the conductive lines. The second trench has side walls and a bottom surface at a specified aspect ratio.

Abstract: A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells can advantageously be formed such that the domain walls, to the extent they exist, fall between (rather than within) the memory cells, thereby improving the performance of the MRAM device.

Abstract: The present invention provides a magnetic memory device capable of performing stable operation efficiently using a magnetic field generated by write current and formed with high precision while realizing a compact configuration. Since a plating film is used for at least a part of a magnetic yoke, as compared with the case of formation by a dry film forming method, sufficient thickness and higher dimensional precision can be obtained. Consequently, a more stabilized return magnetic field can be generated and high reliability can be assured. Neighboring memory cells can be disposed at narrower intervals, so that the invention is suitable for realizing higher integration and higher packing density.

Abstract: A magnetic memory device includes a magnetoresistance configured to store information. A first wiring is provided along a first direction. The first wiring has a function of applying a magnetic field to the magnetoresistance element. The first wiring has a first surface and a second surface. The second surface faces the magnetoresistance element and the first surface is opposite to it. The second surface is smaller in width than the first surface.

Abstract: A method for forming an MTJ structure suitable for use in a MRAM device having a bottom electrode including a layer of platinum, ruthenium, iridium, rhodium, osmium, palladium or their oxides and having reduced surface roughness to improve the hysteresis loop characteristics of the resulting MTJ structure. The bottom electrode layer may also combine the functions of both the seeding layer and bottom electrode of the conventional two-layer structure, thereby simplifying the manufacturing process.