Abstract: An MRAM structure is disclosed in which the bottom electrode has an amorphous TaN capping layer to consistently provide smooth and dense growth for AFM, pinned, tunnel barrier, and free layers in an overlying MTJ. Unlike a conventional Ta capping layer, TaN is oxidation resistant and has high resistivity to avoid shunting of a sense current caused by redeposition of the capping layer on the sidewalls of the tunnel barrier layer. Alternatively, the ?-TaN layer is the seed layer in the MTJ. Furthermore, the seed layer may be a composite layer comprised of a NiCr, NiFe, or NiFeCr layer on the ?-TaN layer. An ?-TaN capping layer or seed layer can also be used in a TMR read head. An MTJ formed on an ?-TaN capping layer has a high MR ratio, high Vb, and a RA similar to results obtained from MTJs based on an optimized Ta capping layer.

Abstract: An arrangement of magnetic liners for the bit lines or word lines of an MRAM device that reduces or eliminates stray magnetic fields at the ends of the magnetic liners, thereby reducing the occurrence of offset fields over portions of the MRAM device due to the magnetic liners is described. The orientation of magnetization of adjacent magnetic liners is alternated, causing the end poles of the magnetic liners to cancel each other. The shapes of the ends of the magnetic liners are alternated to vary their switching fields. Methods are described that use this ability to vary the switching fields to alternate the orientation of magnetization of the magnetic liners.

Abstract: A spin transfer torque magnetic random access memory (STT-MRAM) device comprises adjacent magnetic tunneling junctions (MTJ), respectively, formed in different layers, thereby preventing interference between the MTJs and securing thermal stability.

Abstract: Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line.

Abstract: An MTJ in an MRAM array or TMR read head is disclosed in which a low magnetization capping layer is a composite having a NiFeHf inner layer formed on a NiFe or CoFeB/NiFe free layer, a Ta middle layer, and a Ru outer layer on the Ta layer. For example, a low magnetization NiFeHf layer is achieved by co-sputtering NiFe and Hf targets with a forward power of 400 W and 200 W, respectively. A higher Hf content increases the oxygen gettering power of the NiFeHf layer and the thickness is modified to change dR/R, RA, and magnetostriction values. A so-called dead layer between the free layer and capping layer is restored by incorporating a NiFeHf layer on the free layer to improve lattice matching. The Fe content in the NiFe target used to make the NiFeHf layer is preferably the same as in the NiFe free layer.

Abstract: Three terminal magnetic sensing devices (TTMs) having base lead layers in-plane with collector substrate materials, and methods of making the same, are disclosed. In one illustrative example, a collector substrate having an elevated region and a recessed region adjacent the elevated region is provided. An insulator layer is formed in full-film over the collector substrate, and a base lead layer is formed in full-film over the insulator layer and in-plane with semiconductor materials of the elevated region. The insulator materials and the base lead materials that are formed over the elevated region are removed. A sensor stack structure having an emitter region and a base region is then formed over the elevated region such that part of the base region is formed over an end of the base lead layer. A base conductive via may be formed to contact base lead materials of the base lead layer at a suitable distance away from the sensor stack structure.

Abstract: Methods and apparatus are provided for magnetoresistive random access memory (MRAM) bits (52, 52?) combined with associated drive or sense transistors (53, 141) to form an integrated MRAM array. The MRAM array has lower electrodes (602, 150, 160, 162) of the MRAM bits (52, 52?) formed substantially directly on a source or drain region (56, 142, 152-2) of associated drive or sense transistors (53, 141), so that the intervening vias (302, 34, 36) and underlying interconnects layers (332, 35) of the prior art (20) can be eliminated. An interconnect layer (65) is provided above the MRAM bit (52, 52?) and transistor (53, 141) combination (50, 125, 129, 133) for coupling upper electrodes (41, 164) of the MRAM bits (52, 52?) and other electrodes (601, 58, 152-1, 152-3, 186-1, 186-3) of the transistors (53, 141) to other elements of the array.

Abstract: Probes are electrically connected to a surface of a tunnel junction film stack comprising a free layer, a tunnel barrier, and a pinned layer. Resistances are determined for a variety of probe spacings and for a number of magnetizations of one of the layers of the stack. The probe spacings are a distance from a length scale, which is related to the Resistance-Area (RA) product of the tunnel junction film stack. Spacings from as small as possible to about 40 times the length scale are used. Beneficially, the smallest spacing between probes used during a resistance measurement is under 100 microns. A measured in-plane MagnetoResistance (MR) curve is determined from the “high” and “low” resistances that occur at the two magnetizations of this layer. The RA product, resistances per square of the free and pinned layers, and perpendicular MR are determined through curve fitting.

Abstract: An integrated circuit package may include a substrate and an integrated circuit. The substrate may include at least one region, and a first magnetic material associated with the at least one region. The integrated circuit may have a second magnetic material associated therewith. The second magnetic material may be attracted to the first magnetic material to coupled the integrated circuit to the at least one region of the substrate. The IC package may be utilized in an RFID tag of an RFID system. An associated method for assembling an integrated circuit to a substrate is also provided.

Abstract: An MRAM structure is disclosed in which the bottom electrode has an amorphous TaN capping layer to consistently provide smooth and dense growth for AFM, pinned, tunnel barrier, and free layers in an overlying MTJ. Unlike a conventional Ta capping layer, TaN is oxidation resistant and has high resistivity to avoid shunting of a sense current caused by redeposition of the capping layer on the sidewalls of the tunnel barrier layer. Alternatively, the ?-TaN layer is the seed layer in the MTJ. Furthermore, the seed layer may be a composite layer comprised of a NiCr, NiFe, or NiFeCr layer on the ?-TaN layer. An ?-TaN capping layer or seed layer can also be used in a TMR read head. An MTJ formed on an ?-TaN capping layer has a high MR ratio, high Vb, and a RA similar to results obtained from MTJs based on an optimized Ta capping layer.

Abstract: The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.

Abstract: A magnetic memory element switchable by current injection includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers (e.g., between two of the magnetic layers). The memory element has the switching threshold current and device impedance suitable for integration with complementary metal oxide semiconductor (CMOS) integrated circuits.

Abstract: A method is provided for fabricating a fixed layer for a MRAM device. The method includes providing the fixed layer. The fixed layer includes an antiferromagnetic pinning layer over a substrate and a ferromagnetic pinned layer over the pinning layer, the pinned layer having a first thickness. The fixed layer further includes a spacer layer over the pinned layer, and a ferromagnetic reference layer over the spacer layer, the reference layer having a second thickness. The method further includes annealing the fixed layer using a temporal temperature/magnetic field profile, the profile having a maximum magnetic field magnitude (Hanneal). The profile is selected based on the first thickness of the pinned layer and the second thickness of the reference layer.

Abstract: A memory includes an array of memory cells, each memory cell including resistive material, a first insulation material laterally surrounding the resistive material of each memory cell, and a heat spreader between the memory cells to thermally isolate each memory cell.

Abstract: A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.

Abstract: A MTJ that minimizes spin-transfer magnetization switching current (Jc) in a Spin-RAM to <1×106 A/cm2 is disclosed. The MTJ has a Co60Fe20B20/MgO/Co60Fe20B20 configuration where the CoFeB AP1 pinned and free layers are amorphous and the crystalline MgO tunnel barrier is formed by a ROX or NOX process. The capping layer preferably is a Hf/Ru composite where the lower Hf layer serves as an excellent oxygen getter material to reduce the magnetic “dead layer” at the free layer/capping layer interface and thereby increase dR/R, and lower He and Jc. The annealing temperature is lowered to about 280° C. to give a smoother CoFeB/MgO interface and a smaller offset field than with a 350° C. annealing. In a second embodiment, the AP1 layer has a CoFeB/CoFe configuration wherein the lower CoFeB layer is amorphous and the upper CoFe layer is crystalline to further improve dR/R and lower RA to ?10 ohm/?m2.

Abstract: A second shield layer, under the master shielding layer, is added to a segmented MRAM array. This additional shielding is patterned so as to provide one shield per bit slice. The placement of longitudinal biasing tabs at the ends of these segmented shields ensures that each segmented shield is a single magnetic domain, making it highly effective as a shield against very small stray fields.

Abstract: Programmable resistive RAM cells have a resistance that depends on the size of the programmable resistive elements. Manufacturing methods and integrated circuits for programmable resistive elements with uniform resistance are disclosed that have a cross-section of reduced size compared to the cross-section of the interlayer contacts.

Abstract: A magnetic memory device comprising, a magneto-resistance effect element that is provided at an intersection between a first write line and a second write line. And the magneto-resistance effect element having, an easy axis that extends in a direction of extension of the first write line, and a first conductive layer for electrical connection to the magneto-resistance effect element, the first conductive layer having sides which are in flush with sides of the magneto-resistance effect element.

Abstract: A process for manufacturing a random access memory cell, that is capable of storing multiple information states in a single physical bit, is described. The basic structure combines a conventional MTJ with a reference stack that is magnetostatically coupled to the MTJ. The MTJ is read in the usual way but data is written and stored in the reference stack. Through use of two bit lines, the direction of magnetization of the free layer can be changed in small increments each unique direction representing a different information state.

Abstract: Provided are magnetic tunnel junction structures having bended tips at both ends thereof, magnetic RAM cells employing the same and photo masks used in formation thereof. The magnetic tunnel junction structures have a pinned layer pattern, a tunneling insulation layer pattern and a free layer pattern, which are stacked on an integrated circuit substrate. At least the free layer pattern has a main body as well as first and second bended tips each protruded from both ends of the main body when viewed from a plan view.

Abstract: The present invention provides a semiconductor storage device having: a first conductivity type region formed in a semiconductor layer; a second conductivity type region formed in the semiconductor layer in contact with the first conductivity type region; a memory functional element disposed on the semiconductor layer across the boundary of the first and second conductivity type regions; and an electrode provided in contact with the memory functional element and on the first conductivity type region via an insulation film, and a portable electronic apparatus comprising the semiconductor storage device. The present invention can fully cope with scale-down and high-integration by constituting a selectable memory cell substantially of one device.

Abstract: A magnetic random access memory includes a semiconductor substrate having a projection projecting from a substrate surface, first and second gate electrodes and a first source diffusion layer formed on first and second side surfaces and an upper surface of the projection, first and second drain diffusion layers formed in the substrate surface at roots on the first and second side surfaces of the first projection, first and second word lines formed above the semiconductor substrate, a bit line formed above the first and second word lines, a first magnetoresistive effect element formed between the bit line and the first word line, a second magnetoresistive effect element formed between the bit line and the second word line, a first contact which connects the first magnetoresistive effect element and the first drain diffusion layer, and a second contact which connects the second magnetoresistive effect element and the second drain diffusion layer.

Abstract: A giant magnetoresistance (GMR) pad on the same level of GMR memory bit layer is used as an intermediate connection for plugs between the GMR pad and an underlying diffusion metal layer. A single large power metal plug is used to connect the GMR pad and the overlying power plane metal.

Abstract: In a particular illustrative embodiment, a method of forming a magnetic tunnel junction (MTJ) device is disclosed that includes forming a trench in a substrate. The method further includes depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The method also includes planarizing the MTJ structure. In a particular example, the MTJ structure is planarized using a Chemical Mechanical Planarization (CMP) process.

Abstract: Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.

Abstract: A magnetoresistive memory cell includes a tunnel barrier region between first and second electrode devices. The first electrode device includes a natural antiferromagnet region. A diffusion barrier region is formed in the first electrode device and serves as a chemical and/or physical transformation region of a surface region or interface region between the tunnel barrier region and the natural antiferromagnet region.

Abstract: A magnetic memory device includes a first write wiring line including a wiring layer formed in a trench in an insulation layer, a barrier metal layer buried in the trench over the wiring layer. And the device includes a magneto-resistance effect element provided on the first write wiring line.

Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a trench is provided in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a dielectric layer is deposited to a thickness slightly greater than the desired final thickness of a sense layer, which is formed later. The dielectric layer is then patterned and etched to form an opening for the cell shapes over the first conductor. Then, a permalloy is electroplated in the cell shapes to form the sense layer. The sense layer and dielectric layer are flattened and then a nonmagnetic tunnel barrier layer is deposited. Finally, the pinned layer is formed over the tunnel barrier layer.

Abstract: Methods of forming a magnetic memory device include oxidizing a top magnetic layer using a conductive capping pattern as a mask. An etch selectivity between an oxidized portion of the top magnetic layer and a tunnel barrier layer may be relatively high. Using the tunnel barrier layer as an etch-stop layer, the oxidized portion of the top magnetic layer is selectively removed to form a top magnetic pattern, and to expose at least a portion of opposite sidewalls of the top magnetic pattern and the tunnel barrier layer. The unoxidized portion of the top magnetic layer forms a top magnetic pattern.

Abstract: A MgO tunnel barrier is sandwiched between semiconductor material on one side and a ferri- and/or ferromagnetic material on the other side to form a spintronic element. The semiconductor material may include GaAs, for example. The spintronic element may be used as a spin injection device by injecting charge carriers from the magnetic material into the MgO tunnel barrier and then into the semiconductor. Similarly, the spintronic element may be used as a detector or analyzer of spin-polarized charge carriers by flowing charge carriers from the surface of the semiconducting layer through the MgO tunnel barrier and into the (ferri- or ferro-) magnetic material, which then acts as a detector. The MgO tunnel barrier is preferably formed by forming a Mg layer on an underlayer (e.g., a ferromagnetic layer), and then directing additional Mg, in the presence of oxygen, towards the underlayer.

Abstract: A tunnel barrier in proximity with a layer of a rare earth element-transition metal (RE-TM) alloy forms a device that passes negatively spin-polarized current. The rare earth element includes at least one element selected from the group consisting of Gd, Tb, Dy, Ho, Er, Tm, and Yb. The RE and TM have respective sub-network moments such that the absolute magnitude of the RE sub-network moment is greater than the absolute magnitude of the TM sub-network moment. An additional layer of magnetic material may be used in combination with the tunnel barrier and the RE-TM alloy layer to form a magnetic tunnel junction. Still other layers of tunnel barrier and magnetic material may be used in combination with the foregoing to form a flux-closed double tunnel junction device.

Abstract: Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.

Abstract: A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a write current is passed through the magnetic element. The magnetic element may also include a barrier layer, a second pinned layer. Alternatively, second pinned and second spacer layers and a second free layer magnetostatically coupled to the free layer are included. At least one free layer has a high perpendicular anisotropy. The high perpendicular anisotropy has a perpendicular anisotropy energy that is at least twenty and less than one hundred percent of the out-of-plane demagnetization energy.

Abstract: A method for fabricating a magnetic tunnel junction cell comprises forming an insulation layer with an opening, forming a first pattern including multiple layers of a first electrode pattern on a bottom surface and a sidewall of the opening and an anti-ferromagnetic pattern over the first electrode pattern, forming a magnetic tunnel junction layer over the first pattern and the insulation layer, forming a second electrode having a line width greater than the width of the opening, over the magnetic tunnel junction layer, and etching the magnetic tunnel junction layer using the second electrode as an etch barrier.

Abstract: A STT-RAM MTJ that minimizes spin-transfer magnetization switching current (Jc) is disclosed. The MTJ has a MgO tunnel barrier layer formed with a natural oxidation process to achieve a low RA (10 ohm-um2) and a Fe or Fe/CoFeB/Fe free layer which provides a lower intrinsic damping constant than a CoFeB free layer. A Fe, FeB, or Fe/CoFeB/Fe free layer when formed with a MgO tunnel barrier (radical oxidation process) and a CoFeB AP1 pinned layer in a MRAM MTJ stack annealed at 360° C. provides a high dR/R (TMR)>100% and a substantial improvement in read margin with a TMR/Rp_cov=20. High speed measurement of 100 nm×200 nm oval STT-RAM MTJs has shown a Jc0 for switching a Fe free layer is one half that for switching an amorphous CO40Fe40B20 free layer. A Fe/CoFeB/Fe free layer configuration allows the Hc value to be increased for STT-RAM applications.

Abstract: A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells can advantageously be formed such that the domain walls, to the extent they exist, fall between (rather than within) the memory cells, thereby improving the performance of the MRAM device.

Abstract: Techniques of sensing a temperature of a heat source disposed in a substrate of an integrated circuit are provided. According to one exemplary method, a Magnetic Tunnel Junction (“MTJ”) temperature sensor is provided over the heat source. The MTJ temperature sensor comprises an MTJ core configured to output a current during operation thereof. The value of the current varies based on a resistance value of the particular MTJ core. The resistance value of the MTJ core varies as a function of the temperature of the heat source. A value of the current of the MTJ core can then be associated with a corresponding temperature of the heat source.

Abstract: A method for forming an MTJ structure suitable for use in a MRAM device having a bottom electrode including a layer of platinum, ruthenium, iridium, rhodium, osmium, palladium or their oxides and having reduced surface roughness to improve the hysteresis loop characteristics of the resulting MTJ structure. The bottom electrode layer may also combine the functions of both the seeding layer and bottom electrode of the conventional two-layer structure, thereby simplifying the manufacturing process.

Abstract: A second shield layer, under the master shielding layer, is added to a segmented MRAM array. This additional shielding is patterned so as to provide one shield per bit slice. The placement of longitudinal biasing tabs at the ends of these segmented shields ensures that each segmented shield is a single magnetic domain, making it highly effective as a shield against very small stray fields.

Abstract: An MTJ memory cell is independently provided with a write word line and a read word line used for data write and data read. By separately arranging read word lines every two regions formed by dividing a memory array in the column direction, it is possible to reduce signal propagation delays of the read word lines and accelerate the data read operation. Activation of each read word line is controlled by a write word line in accordance with a row selection result in a hierarchical manner. A word-line-current control circuit forms and cuts off the current path of a write word line correspondingly to data write and data read.

Abstract: A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering layer includes tantalum. A first mask layer is formed over the covering layer followed by a second mask layer. The first mask layer and second mask layer are etchable by the same etching process. The first and second mask layer are etched. Etch residue is removed from the first and second mask layers. The first mask layer is then selectively removed and the second mask layer remains.

Abstract: An improved tunneling barrier layer is formed for use in a MTJ device. This is accomplished by forming the tunneling barrier layer in two steps. First a layer of magnesium is deposited by DC sputtering and converted to magnesium oxide through radical oxidation. This is followed by a second, thinner, magnesium layer that is converted to magnesium oxide through normal oxidation. Optionally, there may also be a thin layer of magnesium on the two magnesium oxide layers.

Abstract: An MRAM structure is disclosed where the distance from a bit line or word line to an underlying free layer in an MTJ is small and well controlled. As a result, the bit line or word line switching current is reduced and tightly distributed for better device performance. A key feature in the method of forming the MRAM cell structure is a two step planarization of an insulation layer deposited on the MTJ array. A CMP step flattens the insulation layer at a distance about 60 to 200 Angstroms above the cap layer in the MTJ. Then an etch back step thins the insulation layer to a level about 50 to 190 Angstroms below the top of the cap layer. Less than 5 Angstroms of the cap layer is removed. The distance variation from the free layer to an overlying bit line or word line is within +/?5 Angstroms.

Abstract: A magnetic random access memory (MRAM), and a method of manufacturing the same, includes a cell including a transistor and a magnetic tunneling junction (MTJ) layer connected to the transistor, wherein the MTJ layer includes a lower electrode, a lower magnetic film, a tunneling film having a uniform thickness and a substantially flat upper surface, and an upper magnetic film, wherein the lower electrode includes a first lower electrode and an amorphous second lower electrode. An amorphous flattening film may be further formed between the lower electrode and the lower magnetic film.

Abstract: A nitrogenated carbon electrode suitable for use in a chalcogenide device and method of making the same are described. The electrode comprises nitrogenated carbon and is in electrical communication with a chalcogenide material. The nitrogenated carbon material may be produced by combining nitrogen and vaporized carbon in a physical vapor deposition process.

Abstract: The direction of magnetization of a reading ferromagnetic material 5R forming a spin filter when reading is the same as that of a pinned layer 1. In this case, a torque that works on the spin of a free layer 3 due to a spin polarized current becomes “zero.” When the element size is made small so as to improve the integration degree of the magnetic memory, according to the scaling law, the writing current can be made small. In the present invention, the resistance to the spin injection magnetization reversal due to a reading current is high, so that the magnitude of the writing current can be lowered.

Abstract: There are provided a first reference layer, in which a direction of magnetization is fixed, and a storage layer including a main body, in which a length in an easy magnetization axis direction is longer than a length in a hard magnetization axis direction, and a projecting portion provided to a central portion of the main body in the hard magnetization axis direction, a direction of magnetization of the storage layer being changeable in accordance with an external magnetic field.

Abstract: A spin transistor and a manufacturing method thereof are provided. The method includes defining a required area on a substrate by lithography; forming a doping area by ion-implantation, and forming a magnetoresistive film on the substrate. Finally, the method produces a spin transistor with the emitter, the base, and the collector in the same plane surface. The manufacturing method integrates the emitter, the base, and the collector into one plane, so that miniaturization of the spin transistor is achieved, and it is advantageous for the integration and subsequent packaging of the spin transistor and integrated circuit elements.

Abstract: A magnetic memory capable of reducing diffusion of ferromagnetic material into semiconductor element area is provided. A magnetic memory 1 includes plural memory areas 3 disposed in two-dimension of m rows and n columns (m, n are integers of 2 or more). The magnetic memory 1 includes semiconductor layer 6 including drain area 32a and source area 32c for write transistor 32, magnetic material layer 8 including TMR element 4 and write wiring 31, and wiring layer 7 including bit wirings 13a and 13b and word wiring 14 being sandwiched between semiconductor layer 6 and magnetic material layer 8. Since wiring layer 7 is sandwiched between magnetic material layer 8 and semiconductor layer 6, the ferromagnetic material diffusing (migrates) from TMR element 4 hardly reaches to semiconductor layer 6. Thus, the diffusion of the ferromagnetic material into the drain area 32a and the source area 32c can be reduced.