Abstract: A pin junction element includes a ferromagnetic p-type semiconductor layer and a n-type semiconductor layer which are connected via an insulating layer, and which shows a tunneling magnetic resistance according to the magnetization of the ferromagnetic p-type semiconductor layer and the magnetization of the ferromagnetic n-type semiconductor layer. In this pin junction element, an empty layer is formed with an applied bias, thereby generating tunnel current via an empty layer. As a result, it is possible to generate tunnel current even when adopting a thicker insulating layer than that of the conventional tunnel magnetic resistance element.

Abstract: A magnetic memory cell and a magnetic memory incorporating the cell are described. The magnetic memory cell includes at least one magnetic element and at least one non-planar selection device. The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The magnetic memory may include a plurality of magnetic storage cells, a plurality of bit lines corresponding to the plurality of magnetic storage cells, and a plurality of source lines corresponding to the plurality of magnetic storage cells.

Abstract: A multi-state magnetoresistive random access memory device having a pinned ferromagnetic region with a magnetic moment vector fixed in a preferred direction in the absence of an applied magnetic field, a non-ferromagnetic spacer layer positioned on the pinned ferromagnetic region, and a free ferromagnetic region with an anisotropy designed to provide a free magnetic moment vector within the free ferromagnetic region with N stable positions, wherein N is a whole number greater than two, positioned on the non-ferromagnetic spacer layer. The number N of stable positions can be induced by a shape anisotropy of the free ferromagnetic region wherein each N stable position has a unique resistance value.

Abstract: An MRAM cell is formed in two separate portions. A first portion, that includes a pinned layer, a tunneling barrier layer and first free layer part, is used to read the value of a stored bit of information. A second portion includes a second free layer part on which information is written and stored. The second free layer part is formed with a high aspect ratio cross-section that renders it strongly magnetically anisotropic and enables it to couple to the relatively isotropic first free layer through a magnetostatic interaction. This interaction aligns the magnetization of the first free layer part in an opposite direction to the magnetization of the second free layer part. The magnetic orientation of the first free layer part relative to that of its adjacent pinned layer determines the resistance state of the first cell portion and this resistance state can be read by passing a current through the first cell portion.

Abstract: A magnetoelectronic device structure 20 includes programming lines 26 and 28 and a magnetoelectronic device 24 between the programming lines 26 and 28. In one embodiment, layers 38, 40, and 42 of a colloidal dispersion of an electrically insulating material and magnetic particles are positioned between the magnetoelectronic device 24 and the programming lines 26 and 28. The magnetic particles cause the colloidal dispersion to have an enhanced magnetic permeability property. The layers 38, 40, and 42 are disposed by a spin coating technique.

Abstract: The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated magnetic memory structures. In one aspect, the present teachings relate to magnetic memory structure fabrication techniques in a high density configuration that includes an efficient means for programming high density magnetic memory structures.

Abstract: It is an object of the invention to relax magnetic saturation and realize a high-performance magnetic shield effect that is suitable for magnetic devices such as an MRAM. A magnetic shield member of the invention is suitable for a magnetic memory device in which a magnetic random access memory (MRAM) consisting of a TMR element formed by stacking a magnetization fixed layer with a direction of magnetization fixed and a magnetic layer, in which a direction of magnetization can be changed, via a tunnel barrier layer is sealed by a sealing material such as resin.

Abstract: A magnetic random access memory includes a single tunnel junction element which includes a first fixed layer, a first recording layer, and a first nonmagnetic layer, a double tunnel junction element which includes a second fixed layer and a third fixed layer, a second recording layer, a second nonmagnetic layer formed between the second fixed layer and the second recording layer, and a third nonmagnetic layer formed between the third fixed layer and the second recording layer, and in which the magnetization directions in the second fixed layer and the second recording layer take one of the parallel state and the antiparallel state in accordance with a direction of an electric current flowing between the second fixed layer and the second recording layer, and a transistor connected to a memory cell having the single tunnel junction element and the double tunnel junction element connected in parallel.

Abstract: A second shield layer, under the master shielding layer, is added to a segmented MRAM array. This additional shielding is patterned so as to provide one shield per bit slice. The placement of longitudinal biasing tabs at the ends of these segmented shields ensures that each segmented shield is a single magnetic domain, making it highly effective as a shield against very small stray fields.

Abstract: A spin-transfer MRAM bit includes a free magnet layer positioned between a pair of spin polarizers, wherein at least one of the spin polarizers comprises an unpinned synthetic antiferromagnet (SAF). The SAF may include two antiparallel fixed magnet layers separated by a coupling layer. To improve manufacturability, the layers of the SAF may be non-symmetrical (e.g., having different thicknesses or different inherent anisotropies) to assist in achieving proper alignment during anneal. The total magnetic moment of the SAF may be greater than that of the free magnet layer.

Abstract: A magnetic memory device includes a magnetoresistive element and a first wiring layer. The magnetoresistive element includes a fixed layer, a recording layer, and a non-magnetic layer interposed therebetween. The first wiring layer extends in a first direction and generates a magnetic field for recording data in the magnetoresistive element. The recording layer includes a base portion extending in a second direction rotated from the first direction by an angle falling within a range of more than 0° to not more than 20°, and first and second projections projecting from the first and second sides of the base portion in a third direction perpendicular to the second direction. The third and fourth sides of the base portion are inclined with respect to the third direction in the same rotational direction as a rotational direction in which the second direction is rotated.

Abstract: A magnetic memory device includes a first interconnection which runs in a first direction, a second interconnection which runs in a second direction different from the first direction, a magnetoresistive element which is arranged at the intersection of and between the first and second interconnections, and a metal layer which is connected to the magnetoresistive element and has a side surface that partially coincides with a side surface of the magnetoresistive element.

Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

Abstract: Techniques for forming a magnetic device are provided. In one aspect, a method of forming a via hole self-aligned with a magnetic device comprises the following steps. A dielectric layer is formed over at least a portion of the magnetic device. The dielectric layer is configured to have an underlayer proximate to the magnetic device which comprises a first material, and an overlayer on a side of the underlayer opposite the magnetic device which comprises a second material. The first material is different from the second material. In a first etching phase, a first etchant is used to etch the dielectric layer, beginning with the overlayer, and through the overlayer. In a second etching phase, a second etchant which is selective for etching the underlayer is used to etch the dielectric layer through the underlayer.

Abstract: A method and a structure are provided for improving the contact of two adjacent GMR memory bits. Two adjacent bit ends are connected by utilizing a single via.

Abstract: An electronic component includes a semiconductor chip with a chip topside, an integrated circuit, and a chip backside. The chip backside includes a magnetic layer. The electronic component further includes a chip carrier with a magnetic layer on its carrier topside. At least one of the two magnetic layers is permanently magnetic such that the semiconductor chip is magnetically fixed on the chip carrier.

Abstract: An MTJ MRAM cell is formed between ultra-thin orthogonal word and bit lines of high conductivity material whose thickness is less than 100 nm. Lines of this thickness produce switching magnetic fields at the cell free layer that are enhanced by a factor of approximately two for a given current. Because the lines require thinner depositions, there is no necessity of removing material by CMP during patterning and polishing. Therefore, there is a uniform spacing between the lines and the cell free layer.

Abstract: An apparatus and methods store data in a magnetic random access memory (MRAM) in a fast and efficient manner. Embodiments advantageously decrease the number of clock cycles required to store data by eliminating at least one wait state in a transition from a read state to a write state. Embodiments advantageously enhance the throughput of the MRAM and a related digital circuit, such as a computer system, which advantageously enhances the operating speed of the digital circuit.

Abstract: A method of fabricating a multi-level 3D memory array includes: preparing a wafer and peripheral circuits thereon; layers of metal, memory resistor material, and metal are deposited, patterned and etched. The steps of the method of the invention are repeated for N levels of a memory array.

Abstract: A magnetic tunnel junction device includes a magnetically programmable free magnetic layer. The free magnetic layer includes a lamination of at least two ferromagnetic layers and at least one intermediate layer interposed between the at least two ferromagnetic layers.

Abstract: The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.

Abstract: Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line.

Abstract: A magnetic random access memory includes, a lower electrode, a magnetoresistive element which is arranged above the lower electrode and has side surfaces, and a protective film which covers the side surfaces of the magnetoresistive element, has a same planar shape as the lower electrode, and is formed by one of sputtering, plasma CVD, and ALD.

Abstract: A magnetic memory cell for use in a magnetic random access memory array that uses the antiferromagnetic to ferromagnetic transition properties of FeRh to assist in the control of switching of the memory cell.

Abstract: Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices, wherein the second magnetic layer or free layer of a magnetic stack may be patterned using a wet etch technique. A cap layer is formed over the free layer after the free layer is patterned. The cap layer is formed using lift-off techniques. To form the cap layer, resist layers are deposited and patterned, and material layers are deposited over the resist layers. Portions of the material layers are removed when the resist is stripped.

Abstract: One embodiment of the present invention includes a non-uniform switching based non-volatile magnetic memory element including a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer, wherein switching current is applied, in a direction that is substantially perpendicular to the fixed, barrier, first free, non-uniform and the second free layers causing switching between states of the first, second free and non-uniform layers with substantially reduced switching current.

Abstract: A method to fabricate an MTJ device and its connections to a CMOS integrated circuit is described. The device is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum.

Abstract: Magnetic Random Access Memory (MRAM) devices include a lower electrode and a magnetic tunnel junction on the lower electrode. The magnetic tunnel junction includes a seed layer and a tunneling barrier that is oriented in a same direction as the most closely packed plane direction of the seed layer. An oxide layer may be provided between the lower electrode and the magnetic tunnel junction. The lower electrode may be a titanium-rich TiN layer having more than 50 atomic percent titanium content. Analogous fabrication methods are also described.

Abstract: A magnetic memory device exhibits improved writing characteristics by providing a magnetic flux concentrator which efficiently applies the magnetic field, which is generated by the writing word line, to the memory layer of the TMR element. The magnetic memory device (1) is composed of the TMR element (13), the writing word line (the first wiring) (11) which is electrically insulated from the TMR element (13), and the bit line (the second wiring) (12) which is electrically connected to the TMR element (13) and intersecting three-dimensionally with the writing word line (11), with the TMR element (13) interposed therebetween. The magnetic memory device (1) is characterized as follows. The magnetic flux concentrator (51) of high-permeability layer is formed along at least the lateral sides of the writing word line (11) and the side of the writing word line (11) which is opposite to the side facing the TMR element (13).

Abstract: To integrate a capacitor device (40) into the region of a semiconductor memory device with a particularly small number of process steps, a lower electrode device (43) and an upper electrode device (44) of the capacitor device (40) are provided to be formed directly underneath or directly above the material region (30) which has the memory elements (20), in such a way that as a result at least a part of the material region (30) which has the memory elements (20) functions at least as part of the respective dielectric (45) between the electrodes devices (43, 44).

Abstract: A method of forming a magnetic memory device (and a resulting structure) on a low-temperature substrate, includes forming the memory device on a transparent substrate coated with a decomposable material layer subject to rapid heating resulting in a predetermined high pressure, and transferring the memory device to the low-temperature substrate.

Abstract: A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.

Abstract: An apparatus including a pillar located over a substrate and having at least one sloped surface oriented at an acute angle relative to the substrate. The apparatus also includes an MRAM stack substantially conforming to the sloped surface, the MRAM stack thereby also oriented at the acute angle relative to the substrate. The MRAM stack may comprise a plurality of substantially planar, parallel layers each oriented at an acute angle relative to the substrate.

Abstract: Write characteristics and read characteristics can be improved at the same time by applying novel materials to ferromagnetic layers. In a magneto resistive effect element having a pair of ferromagnetic layers being opposed to each other through an intermediate layer to cause a current to flow in the direction perpendicular to the film plane to obtain a magnetoresistive change, at least one of the ferromagnetic layers contains a ferromagnetic material containing Fe, Co and B. The ferromagnetic material should preferably contain FeaCobNicBd (in the chemical formula, a, b, c and d represent atomic %. 5?a?45, 35?b?85, 0?c?35, 10?d?30. a+b+C+d=100).

Abstract: An annular microstructure element, in particular an annularly arranged monolayer or multilayer thin film, is formed over a substrate (S), e.g., for use in a magnetoresistive memory. To that end, a masking layer is applied over the substrate. An opening (C) is etched into the masking layer, so that a partial region of the surface is uncovered. The etching operation is performed in such a way that the opening (C) is formed with an overhang (B). The overhang at least partially shades the uncovered surface from an incident particle beam (TS). A particle beam (TS) is directed at the substrate (S) at an oblique angle (?) of incidence. In this case, the substrate (S) is rotated relative to the directed particle beam (TS). From the particle beam, material is thereby deposited annularly on the uncovered surface for the purpose of forming a hole-like microstructure element (R).

Abstract: Write characteristics and read characteristics can be improved at the same time by applying novel materials to ferromagnetic layers. In a magnetoresistive effect element having a pair of ferromagnetic layers being opposed to each other through an intermediate layer to cause a current to flow in the direction perpendicular to the film plane to obtain a magnetoresistive change, at least one of the ferromagnetic layers contains a ferromagnetic material containing Fe, Co and B. The ferromagnetic material should preferably contain FeaCobNicBd (in the chemical formula, a, b, c and d represent atomic %. 5?a?45, 35?b?85, 0<c?35, 10?d?30. a+b+C+d=100).

Abstract: A memory element for a magnetic RAM, contained in a recess of an insulating layer, the recess including a portion with slanted sides extending down to the bottom of the recess, the memory element including a first magnetic layer portion substantially conformally covering the bottom of the recess and the recess portion with slanted sides and in contact, at the level of the bottom of the recess, with a conductive portion, a non-magnetic layer portion substantially conformally covering the first magnetic layer portion and a second magnetic layer portion covering the non-magnetic layer portion.

Abstract: A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells can advantageously be formed such that the domain walls, to the extent they exist, fall between (rather than within) the memory cells, thereby improving the performance of the MRAM device.

Abstract: A pin junction element (10) includes a ferromagnetic p-type semiconductor layer (11) and a n-type semiconductor layer (12) which are connected via an insulating layer (13), and which shows a tunneling magnetic resistance according to the magnetization of the ferromagnetic p-type semiconductor layer (11) and the magnetization of the ferromagnetic n-type semiconductor layer (12). In this pin junction element (10), an empty layer is formed with an applied bias, thereby generating tunnel current via an empty layer. As a result, it is possible to generate tunnel current even when adopting a thicker insulating layer than that of the conventional tunnel magnetic resistance element.

Abstract: MRAM structures employ the magnetic properties of layered magnetic and non-magnetic materials to read memory storage logic states. Improvements in switching reliability may be achieved by altering the shape of the layered magnetic stack structure. Forming recessed regions with sloped interior walls in an ILD layer prior to depositing the layered magnetic stack structure produces a significant advantage over the prior art by allowing a CMP process to be used to define the magnetic bit shapes. The sloped interior walls of the recessed regions, which is singular to the present invention, provide a unique formation and shaping of the magnetic stack structure, which may reduce the magnetic coupling effect between magnetic layers of the magnetic stack structure.

Abstract: A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided. The patterned mask layer exposes the deep trench. A deep trench capacitor is formed inside the deep trench. Thereafter, a trench is formed in the substrate on one side of the deep trench capacitor. The trench exposes a portion of the upper electrode of the deep trench capacitor and a portion of the substrate. After that, a semiconductor strip is formed in the trench. A gate dielectric layer is formed over the substrate to cover the exposed semiconductor strip and the substrate. A gate is formed over the gate dielectric layer such that the gate and the semiconductor strip crosses over each other, and the gate-covered portion of the semiconductor strip serves as a channel region.

Abstract: An TMR-type MRAM comprising a transistor for selection; a first connecting hole; a first wiring (write-in word line); a second insulating interlayer covering a first insulating interlayer and the first wiring; a TRM device formed on the second insulating interlayer; a second wiring (bit line) formed on a third insulating interlayer; and a second connecting hole formed through the second insulating interlayer and connected to the first connecting hole, in which an end face of an extending portion of the other end of the TRM device is in contact with the second connecting hole.

Abstract: A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells can advantageously be formed such that the domain walls, to the extent they exist, fall between (rather than within) the memory cells, thereby improving the performance of the MRAM device.

Abstract: An exemplary method for making a memory structure comprises forming a first ferromagnetic layer, forming a spacer layer above the first ferromagnetic layer, forming a second ferromagnetic layer above the spacer layer by applying a first deposition process to form a thin layer of ferromagnetic material substantially covering the spacer layer, the first layer being formed at a first energy level, and applying a second deposition process to form the remainder of the second ferromagnetic layer above the thin layer of ferromagnetic material, the second ferromagnetic layer being formed at a second energy level, higher than the first energy level. This way, the spacer layer is protected by the thin layer during the second energy level deposition.

Abstract: A structure that is well suited to connecting an MTJ device to a CMOS integrated circuit is described. It is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum. A method for its formation is also described.

Abstract: In a magnetoresistive effect element using a ferromagnetic tunnel junction having a tunnel barrier layer sandwiched between at least a pair of ferromagnetic layers, a magnetization free layer comprising one of the ferromagnetic layers is composed of a single layer of a material having an amorphous or microcrystal structure or a material layer the main portion of which has an amorphous or microcrystal structure. The magnetoresistive effect element can produce excellent magnetic-resistance characteristics, and a magnetic memory element and a magnetic memory device using the magnetoresistive effect element as a memory element thereof can improve both of write and read characteristics at the same time.

Abstract: A method of treating a substrate in manufacturing a magnetoresistive memory cell includes performing a cleaning operation on the substrate using a mask layer as a protection layer for etching of a peripheral via. Further, an etch stop layer can used as a protection layer in a cleaning operation on the substrate.

Abstract: A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells, arranged in rows and columns; and forming a plurality of resistive bit lines for connecting PCM cells arranged on a same column, each resistive bit lines comprising a respective phase change material portion, covered by a respective barrier portion. After forming the resistive bit lines, electrical connection structures for the resistive bit lines are formed directly in contact with the barrier portions of the resistive bit lines.

Abstract: An integrated circuit arrangement includes at least one electrical conductor that, when a current flows through it, produces a magnetic field that acts on at least a further part of the circuit arrangement, wherein seen in cross section, the electrical conductor has at least one recess or depression, or a region of reduced conductivity on the side facing that part, in order to influence the magnetic field which can be produced.

Abstract: A method of forming a self-aligned contact via for a MRAM is disclosed. A first conductive layer, a pinned layer, a tunneling barrier layer, a free layer, a capping layer and a first dielectric layer are formed sequentially over a substrate has formed lots of transistors and interconects. A portion of the first dielectric layer and the capping layer are removed until a surface of the free layer is exposed. A portion of the pinned layer, the tunneling barrier layer and the free layer are removed to form a MRAM device. A second dielectric layer is formed over the magnetic random access memory device. A planarization process is performed to form a planar surface of the second dielectric layer. The first dielectric layer and a portion of the second dielectric layer are removed to form a self-aligned contact opening. A second conductive layer is filled into the self-aligned contact opening.