Abstract: To provide a manufacturing method of a semiconductor device capable of forming, as a protective film of an MTJ element, a silicon nitride film having good insulation properties without deteriorating the properties of the MTJ element. The method of the invention includes steps of forming a silicon nitride film over the entire surface including an MTJ element portion (MTJ element and an upper electrode) while using a parallel plate plasma CVD apparatus as a film forming apparatus and a film forming gas not containing NH3 but composed of SiH4/N2/helium (He). The film forming temperature is set at from 200 to 350° C. More ideally, a flow rate ratio of He to SiH4 is set at from 100 to 125.

Abstract: A nonvolatile memory device including a lower electrode, a resistor structure disposed on the lower electrode, a middle electrode disposed on the resistor structure, a diode structure disposed on the middle electrode, and an upper electrode disposed on the diode structure. A nonvolatile memory device wherein the resistor structure includes one resistor and the diode structure includes one diode. An array of nonvolatile memory device as described above. Methods of manufacturing a nonvolatile memory device and an array of nonvolatile memory device.

Abstract: A magnetic random access memory includes a bit line running in a first direction, a first word line running in a second direction different from the first direction, and a memory element having a magnetoresistive effect element including a fixed layer having a fixed magnetization direction, a recording layer having a reversible magnetization direction, and a nonmagnetic layer formed between the fixed layer and the recording layer, the magnetization directions in the fixed layer and the recording layer being perpendicular to a film surface, and a heater layer in contact with the magnetoresistive effect element, the memory element being connected to the bit line, and formed to oppose a side surface of the first word line such that the memory element is insulated from the first word line.

Abstract: A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer.

Abstract: Described herein are novel, cost effective and scalable methods for integrating a CMOS level with a memory cell level to form a field induced MRAM device. The memory portion of the device includes N parallel word lines, which may be clad, overlaid by M parallel bit lines orthogonal to the word lines and individual patterned memory cells formed on previously patterned electrodes at the N×M intersections of the two sets of lines. The memory portion is integrated with a CMOS level and the connection between levels is facilitated by the formation of interconnecting vias between the N×M electrodes and corresponding pads in the CMOS level and by word line connection pads in the memory device level and corresponding metal pads in the CMOS level.

Abstract: Embodiments of a magnetoresistive random access memory (MRAM) array include multiple transistors having source and drain regions, and multiple substantially planar MRAM bits. The MRAM bits have upper and lower electrodes and intervening magnetics layers. The lower electrodes of at least some of the MRAM bits are formed substantially directly on at least some of the source or drain regions without an intervening via. Embodiments of an MRAM array also include a first conductive interconnect layer above and in electrical contact with the upper electrodes of at least some of the MRAM bits, with no metal layers intervening between the upper electrodes and the first conductive interconnect layer.

Abstract: In an MRAM, a curved region (206) is formed in a bit line (202), and this curved region (206) is in bent shape, with a TMR element (203) serving as a center, in this case, in rough U shape (in the illustrated example, in roughly inverted U shape). The bit line (202) in which the curved region (206) is formed includes the TMR element (203) in a space formed by the curved region (206). Thanks to such relatively simple construction, this construction realizes a highly reliable MRAM which ensures that power is substantially saved during data writing into a memory cell while meeting requirements for further miniaturization of the device.

Abstract: A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.

Abstract: A magnetic memory device includes a memory region, an input and a sensor. The memory region includes a free layer, a pinned layer and a non-magnetic layer. The free layer has adjacent sectors and a magnetic domain wall. The pinned layer corresponds to the sectors and has a fixed magnetization direction. The non-magnetic layer is formed between the free layer and the pinned layer. The memory region includes a magnetic domain wall stopper for stopping the magnetic domain wall formed at each boundary of the sectors. The input is electrically connected to one end of the free layer for inputting a signal for magnetic domain dragging. The sensor measures a current flowing through the memory region.

Abstract: A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming a top electrode layer over an MTJ structure. The top electrode layer includes a first nitrified metal.

Abstract: Provided are a ferroelectric recording medium and a method of manufacturing the same. The ferroelectric recording medium includes a substrate, a plurality of supporting layers which are formed on the substrate, each of the supporting layers having at least two lateral surfaces; and data recording layers formed on the lateral surfaces of the supporting layers. First and second data recording layers may be respectively disposed on two facing lateral surfaces of each of the supporting layers. The supporting layers may be polygonal pillars having at least three lateral surfaces. A plurality of the supporting layers can be disposed at uniform intervals in a two-dimensional array.

Abstract: Techniques for exchange coupling of magnetic layers in semiconductor devices are provided. In one aspect, a semiconductor device is provided. The device comprises at least two magnetic layers, and a spacer layer formed between the magnetic layers, the spacer layer being configured to provide ferromagnetic exchange coupling between the layers, the magnetic layers experiencing anti-ferromagnetic dipole coupling, such that a net coupling of the magnetic layers is anti-ferromagnetic in a zero applied magnetic field. The semiconductor device may comprise magnetic random access memory (MRAM). In another aspect, a method for coupling magnetic layers in a semiconductor device comprising at least two magnetic layers and a spacer layer therebetween, the method comprises the following step.

Abstract: A method of forming a magnetic memory device (and a resulting structure) on a low-temperature substrate, includes forming the memory device on a transparent substrate coated with a decomposable material layer subject to rapid heating resulting in a predetermined high pressure, and transferring the memory device to the low-temperature substrate.

Abstract: A multilayered magnetoresistive device includes a specular layer positioned on at least one sidewall and a copper layer is positioned between the specular layer and the sidewall.

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.

Abstract: A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps each followed by two plasma etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers. The hard mask has an upper Ta layer with a thickness of 300 to 400 Angstroms and a lower NiCr layer less than 50 Angstroms thick. The upper Ta layer is etched with a fluorocarbon etch while lower NiCr layer and underlying MTJ layers are etched with a CH3OH. Preferably, a photoresist mask layer is removed by oxygen plasma between the fluorocarbon and CH3OH plasma etches. A lower hard mask layer made of NiCr or the like is inserted to prevent formation and buildup of Ta etch residues that can cause device shunting.

Abstract: A nano-magnetic device includes a first hard magnet having a first magnetization direction and having a central axis. The device also includes a second hard magnet separated from the first hard magnet by a dielectric liner. The second hard magnet has a second magnetization direction opposite to the first magnetization direction of the first hard magnet, and a central axis, such that when the first hard magnet and the second hard magnet are aligned a closed magnetic flux loop is formed through the first and second hard magnets. The device additionally includes a ferromagnetic free layer having a central axis. A spin-torque transfer current passes along the central axes of the first and second hard magnets and the ferromagnetic free layer, and affects the magnetization direction of the ferromagnetic free layer.

Abstract: A method of forming a magnetoelectronic device includes forming a dielectric material (114) surrounding a magnetic bit (112), etching the dielectric material (114) to define an opening (122) over the magnetic bit (112) without exposing the magnetic bit (112), the opening (122) having a sidewall, depositing a blanket layer (132) of cladding material over the dielectric material (118), including over the sidewall, removing by a sputtering process the blanket layer (132) in the bottom of the opening (122) and the dielectric material (124) over the magnetic bit (112), and forming a conductive material (146) within the opening (122) to form a bit line (154). This process reduces errors caused by process irregularities such as edges of the bits (112) protruding and thereby causing defects in the cladding layer (132) formed thereover.

Abstract: In a method for manufacturing a nonvolatile memory device, an etch mask layer formed on a dielectric layer to define contact holes in the dielectric layer is slope-etched to form an etch mask pattern having an opening wider at the upper end thereof than the lower end thereof. Thus, the contact holes are defined in the dielectric layer to have a finer size than the upper end of the opening of the etch mask pattern. The method for manufacturing a nonvolatile memory device includes forming an etch mask pattern on a dielectric layer such that a width of a lower end of each opening defined in the etch mask pattern is less than a width of an upper end thereof; and defining contact holes by removing portions of the dielectric layer using the etch mask pattern.

Abstract: A method for manufacturing a magnetoresistive sensor that provides increased magnetoresistive performance. The method includes forming a series of sensor layers with at least one layer containing CoFeB, and having a first capping layer thereover. A high temperature annealing is performed to optimize the grains structure of the sensor layers. The first capping layer is then removed, such as by reactive ion etching (RIE). An antiferromagnetic layer is then deposited followed by a second capping layer. A second annealing is performed to set the magnetization of the pinned layer, the second annealing being performed at a lower temperature than the first annealing.

Abstract: A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a write current is passed through the magnetic element. The free layer includes a first ferromagnetic layer and a second ferromagnetic layer. The second ferromagnetic layer has a very high perpendicular anisotropy and an out-of-plane demagnetization energy. The very high perpendicular anisotropy energy is greater than the out-of-plane demagnetization energy of the second layer.

Abstract: A nonvolatile memory device including one resistor and one transistor. The resistor may correspond to a resistance layer electrically connected to a first impurity region and a second impurity region of the transistor.

Abstract: A semiconductor memory device, comprising: a semiconductor substrate; a memory cell section comprising a memory transistor provided on the semiconductor substrate, the memory transistor including a first gate electrode provided on the semiconductor substrate with a gate insulating film interposed therebetween, and a source and drain provided at both sides of the first gate electrode on the semiconductor substrate, and a ferroelectric capacitor provided above the memory transistor, the ferroelectric capacitor including a first electrode film connected to any one of a source and drain of the memory transistor, a second electrode film connected to the other one of the drain and source of the memory transistor, and a ferroelectric film provided between the first electrode film and the second electrode film, the memory cell section having the memory transistor and the ferroelectric capacitor connected in parallel to each other; and a select transistor section, comprising a select transistor provided at an end of t

Abstract: A conductive plug located in a planar dielectric layer, under GMR memory cells, are used to directly connect the lower ferromagnetic layer of one of the GMR memory cell and a conductive layer under the planar dielectric layer.

Abstract: A spin-tunnel transistor having a tunnel barrier layer formed of an antiferromagnetic material which is exchange coupled with a first or second ferromagnetic metal layer of a base B formed adjoining to the antiferromagnetic material, so as to fix magnetization of the adjoining ferromagnetic layer. The base B includes a nonmagnetic metal layer which is formed between the first and second ferromagnetic metal layers and decouple magnetization coupling between the first and second ferromagnetic metal layers. The base B is formed between a collector and an emitter to form tri-terminal device. Those spin-tunnel transistor may be used as a sensor of a magnetic reproducing head used in a hard disk drive.

Abstract: A method of forming a STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a free layer that comprises an amorphous layer of Co60Fe20B20.of approximately 20 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.

Abstract: Provided are a multi-purpose magnetic film structure using a spin charge, a method of manufacturing the same, a semiconductor device having the same, and a method of operating the semiconductor memory device. The multi-purpose magnetic film structure includes a lower magnetic film, a tunneling film formed on the lower magnetic film, and an upper magnetic film formed on the tunneling film, wherein the lower and upper magnetic films are ferromagnetic films forming an electrochemical potential difference therebetween when the lower and upper magnetic films have opposite magnetization directions.

Abstract: An MTJ MRAM cell and its method of formation are described. The cell includes a composite free layer having the general form (Ni88Fe12)1-xCo100x—Ni92Fe8 with x between 0.05 and 0.1 that provides low magnetization and negative magnetostriction. The magnetostriction can be tuned to a low value by a multilayer capping layer that includes a positive magnetostriction layer of NiFeHf(15%). When this cell forms an MRAM array, it contributes to a TMR?26%, a TMR/Rp—cov?15.5 and a high AQF (array quality factor) for write operations.

Abstract: A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer.

Abstract: Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes.

Abstract: A nonvolatile magnetic memory device including a magnetoresistance device having a recording layer formed of a ferromagnetic material for storing information by use of variation in resistance depending on the magnetization inversion state. The plan-view shape of the recording layer includes a pseudo-rhombic shape having four sides, at least two of the four sides each include a smooth curve having a central portion curved toward the center of the pseudo-rhombic shape. The easy axis of magnetization of the recording layer is substantially parallel to the longer axis of the pseudo-rhombic shape. The hard axis of magnetization of the recording layer is substantially parallel to the shorter axis of the pseudo-rhombic shape. The sides constituting the plan-view shape of the recording layer are smoothly connected to each other.

Abstract: A method of manufacturing a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, depositing a conductive terminal within the trench, and depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a configurable magnetic orientation. The fixed magnetic layer is coupled to the conductive terminal along an interface that extends substantially normal to a surface of the substrate. The free magnetic layer that is adjacent to the conductive terminal carries a magnetic domain adapted to store a digital value.

Abstract: A system and method to fabricate magnetic random access memory is disclosed. In a particular embodiment, the method includes depositing a cap layer on a magnetic tunnel junction (MTJ) structure, depositing a first spin-on material layer over the cap layer, and etching the first spin-on material layer and at least a portion of the cap layer.

Abstract: In one embodiment, the invention is a method and apparatus for bitline and contact via integration in magnetic random access memory arrays. One embodiment of a magnetic random access memory according to the present invention includes a magnetic tunnel junction and a top wire that surrounds the magnetic tunnel junction on at least three sides.

Abstract: The magnetic device comprises a least two layers made of a magnetic material that are separated by at least one interlayer made of a non-magnetic material. The layers made of a magnetic material each have magnetization oriented substantially perpendicular to the plane of the layers. The layer of non-magnetic material induces an antiferromagnetic coupling field between the layers made of a magnetic material, the direction and amplitude of this field attenuating the effects of the ferromagnetic coupling field of magnetostatic origin that occurs between the magnetic layers.

Abstract: A STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a free layer that comprises an amorphous layer of Co60Fe20B20 of approximately 20 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively or on a single such layer. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.

Abstract: A magnetic structure (2) comprising a magnetic layer (18) having an upper surface and a lower surface is disclosed. The magnetic layer comprises a plurality of regions, each of which is adapted to be magnetised predominantly along a first or second direction. The magnetic layer further comprises at least one structured feature (21) adapted to prevent passage of a magnetic domain wall (26) of a respective type and at least one second structural feature (22) adapted to prevent propagation of at least one magnetic domain wall (34) of a second type. A data storage device (46) incorporating the magnetic structure is also disclosed.

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: There is provided a magnetic memory device and a method of forming the same. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions.

Abstract: A magnetoresistive element includes a stack formed by sequentially stacking a first fixed layer in which a magnetization direction is fixed, a first nonmagnetic layer, a free layer in which a magnetization direction is changeable, a second nonmagnetic layer, and a second fixed layer in which a magnetization direction is fixed, a first circumferential wall provided on the second nonmagnetic layer in contact with a circumferential surface of the second fixed layer to surround the second fixed layer, and made of an insulator, and a second circumferential wall provided on the first nonmagnetic layer in contact with a circumferential surface of the free layer to surround the free layer, and made of an insulator.

Abstract: Portions excluding magnetic elements of a laminate film of magnetic films or the like constituting magnetic elements (1) are oxidized/nitrided or oxynitrided to be insulated by a plasma processing using a conductive mask (17), whereby a plurality of magnetic elements are separated. This laminate film comprises a magnetic element region (18) formed with magnetic elements (1) and an insulated region (19) consisting of oxides/nitrides or oxynitrides. Upper wiring such as a bit line (3) is formed later. Since the conductive mask used in forming the insulated region is made part of the upper wiring, the magnetic elements and the upper wiring can be disposed in contact with each other.

Abstract: A method of forming an integrated circuit includes forming magnetic tunnel junction (MTJ) layers; etching the MTJ layers to form a MTJ cell; and forming a dielectric capping layer on sidewalls of the MTJ cell, wherein the step of forming the dielectric capping layer is in-situ performed with the step of etching the MTJ layers.

Abstract: A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode.

Abstract: A spin transistor includes a non-magnetic semiconductor substrate having a channel region, a first area, and a second area. The channel region is between the first and the second areas. The spin transistor also includes a first conductive layer located above the first area and made of a ferromagnetic material magnetized in a first direction; and a second conductive layer located above the second area and made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction. The channel region introduces electron spin between the conductive layers. The spin transistor also includes a gate electrode located between the conductive layers and above the channel region; and a tunnel barrier film located between the non-magnetic semiconductor substrate and at least one of the conductive layers.

Abstract: A memory element for a magnetic RAM, having a first magnetic portion in a first recess of a first insulating layer; and a non-magnetic portion and a second magnetic portion in a second recess of a second insulating layer covering the first insulating layer, the second recess exposing the first magnetic portion and a portion of the first insulating layer around the first magnetic portion, the non-magnetic portion being interposed between the first and second magnetic portions.

Abstract: The present invention is directed to the use of perovskite manganite thin films and other magnetic films that exhibit both planar Hall effect and biaxial magnetic anisotropy to form the active area in magnetic sensor devices and in magnetic bit cells used in magnetoresistive random access memory (MRAM) devices. The manganite thin films of the invention are ferromagnetic manganites of the formula R1-xAxMnO3, wherein R is a rare-earth metal, A is an alkaline earth metal, and x is generally between about 0.15 and about 0.5.

Abstract: A method for manufacturing an integrated circuit having a magnetic tunnel junction device is disclosed. The method includes depositing a bottom pinning structure above the bottom conductive structure. A first ferromagnetic structure is deposited above the bottom pinning structure in a chamber. A tunnel barrier structure is deposited above the first ferromagnetic layer structure in the chamber, and a second ferromagnetic structure is deposited above the tunnel barrier structure of the magnetic tunnel junction device in another chamber.

Abstract: A composite arrangement has a substrate material with a main surface, a metal-insulator arrangement including a metal sheet with an insulation area on the main surface, and a magnetoresistive structure on the metal-insulator arrangement. Thereupon, a cover layer arrangement is heated, so that the same at least partially covers the magnetoresistive structure with a target thickness D, and finally the magnetoresistive structure is heated by light radiation with given wavelength ?. The absorbed portion of the emitted radiation depends on the actual thickness D? of the cover layer arrangement and the wavelength ?, wherein the target thickness D of the cover layer arrangement is adjusted so that, if the cover layer deviates from the target thickness D in a range of ±20% with reference to the target thickness D, a change of the absorbed portion of the emitted radiation in the magnetoresistive structure of less than ±40% is caused.

Abstract: A spin injection device capable of spin injection magnetization reversal at low current density, a magnetic apparatus using the same, and magnetic thin film using the same, whereby the spin injection device (14) including a spin injection part (1) comprising a spin polarization part (9) including a ferromagnetic fixed layer (26) and an injection junction part (7) of nonmagnetic layer, and a ferromagnetic free layer (27) provided in contact with the spin injection part (1) is such that in which the nonmagnetic layer (7) is made of either an insulator (12) or a conductor (25), a nonmagnetic layer (28) is provided on the surface of the ferromagnetic free layer (27), electric current is flown in the direction perpendicular to the film surface of the spin injection device (14), and the magnetization of the ferromagnetic free layer (27) is reversed. This is applicable to such various magnetic apparatuses and magnetic memory devices as super gigabit large capacity, high speed, non-volatile MRAM and the like.

Abstract: An erase-on-demand memory cell 10(1) includes a memory layer 110 and a heating layer 130 that can heat memory layer 110 to at least an erase-effective temperature, to erase its data contents. Memory chips 270(1) and electronic systems 200 include cells 10(1). Electronic systems 200(1) include logic circuitry 210 to issue a signal to initiate heating. Electronic systems 200(2) include memory chips 270(2) with one or more erase-on-demand memory cells 10(2) that include a memory layer 110. One or more reservoirs 262 store chemicals. One or more valves 252 retain the chemicals, and respond to a signal to open, reacting the chemicals and/or exposing memory layers 110 to the chemicals. A method of erasing data contents of memory cells includes determining existence of an erase demand scenario, generating a signal in response to the erase demand scenario, and actuating erasure of the memory cells upon issue of the signal.