Abstract: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Abstract: New temporary bonding methods and articles formed from those methods are provided. The methods comprise bonding a device wafer to a carrier wafer or substrate only at their outer perimeters in order to assist in protecting the device wafer and its device sites during subsequent processing and handling. The edge bonds formed by this method are chemically and thermally resistant, but can also be softened, dissolved, or mechanically disrupted to allow the wafers to be easily separated with very low forces and at or near room temperature at the appropriate stage in the fabrication process.

Abstract: A technique is provided which allows a chip mounted by wire bonding and a chip mounted by bump electrodes to share a manufacturing process. Both in a case where a chip is electrically coupled to an external circuit by bump electrodes and a case where the chip is electrically coupled to the external circuit by bonding wires, a bump coupling part and a bonding pad are both provided in a single uppermost wiring layer. When the bump electrodes are used, an opening is provided in an insulating film on the bump coupling part and a surface of the bonding pad is covered with the insulating film. On the other hand, when the bonding wires are used, an opening is provided in an insulating film on the bonding pad and a surface of the bump coupling part is covered with the insulating film.

Abstract: An electronic device may include an electronic substrate, and an under bump seed metallurgy layer on the electronic substrate. A barrier layer may be provided on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the barrier layer and the electronic substrate, and the barrier layer may include nickel and/or copper. Moreover, portions of the under bump seed metallurgy layer may be undercut relative to portions of the barrier layer. In addition, a solder layer may be provided on the barrier layer so that the barrier layer is between the solder layer and the under bump seed metallurgy layer.

Abstract: An interconnection mechanism between plated through holes is disclosed, a first embodiment includes a first substrate having a first plated through hole; a second substrate having a second plated through hole; a metal core is configured in between the two plated through holes; the metal ball has a diameter larger than a diameter of the plated through holes; and melted solder binds the first plated through hole, metal core, and the second plated through hole. A second embodiment includes stacked substrate having a gold plated only on ring pads of the plated through holes; melted solder binds the two gold ring pads.

Abstract: In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes.

Abstract: A semiconductor device including: a semiconductor substrate on which a plurality of electrodes are formed; a plurality of resin protrusions formed on the semiconductor substrate, arranged along a straight line, and extending in a direction which intersects the straight line; and a plurality of electrical connection sections formed on the resin protrusions and electrically connected to the electrodes.

Abstract: There are constituted by a tab (1b) on which a semiconductor chip (2) is mounted, a sealing portion (3) formed by resin-sealing the semiconductor chip (2), a plurality of leads (1a) each having a mounted surface (1d) exposed to a peripheral portion of a rear surface (3a) of the sealing portion (3) and a sealing-portion forming surface (1g) disposed on an opposite side thereto, and a wire (4) for connecting a pad (2a) of the semiconductor chip (2) and a lead (1a), wherein the length (M) between inner ends (1h) of the sealing-portion forming surfaces (1g) of the leads (1a) disposed so as to oppose to each other is formed to be larger than the length (L) between inner ends (1h) of the mounted surfaces (1d). Thereby, a chip mounting region surrounded by the inner end (1h) of the sealing-portion forming surface (1g) of each lead (1a) can be expanded and the size of the mountable chip is increased.

Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device electrically connects an electrode provided on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The metal substrate is provided on one side of the insulating layer. The copper wiring layer is provided on another side of the insulating layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode provided on the semiconductor chip. The second terminal is connected with the external wiring device.

Abstract: The insulative wiring board of the present invention, with its both surfaces being covered with solder resist, includes at least one via hole in a semiconductor chip-mounting area penetrating the insulative wiring board, wherein conductor layers are electrically connected to each other via said at least one via hole. Further, the mounting area is covered with the solder resist, excluding said at least one via hole that penetrates the insulative wiring board. Therefore, it is possible to achieve an insulative wiring board that prevents defects caused by expansion occurred due to heating of moisture absorbed by the board, as well as reducing an area where a wiring cannot be provided.

Abstract: A semiconductor substrate (1) is secured by suction to a rear face (1b) of a supporting face (11a) of a substrate supporting table (11). In this event, the thickness of the semiconductor substrate (1) is made fixed by planarization on the rear face (1b), and the rear face (1b) is forcibly brought into a state free from undulation by the suction to the supporting face (11a), so that the rear face (1b) becomes a reference face for planarization of a front face (1a). In this state, a tool (10) is used to cut surface layers of Au projections (2) and a resist mask (12) on the front face (1a), thereby planarizing the Au projections (2) and the resist mask (12) so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.

Abstract: A stackable package substrate has an opening shaped and dimensioned to accommodate but not contact a mold cap of a package upon which the stackable package is to be mounted. On the die attach surface, the frame substrate accommodates a die attach margin adjacent at the edge of the opening; and a row of wire bond sites arranged along at an outer frame edge, for electrical interconnection. The frame substrate accommodates z-interconnect ball pads arranged to align with corresponding z-interconnect pads on the substrate of a package. A stackable package has a frame substrate. A stacked package assembly includes a second package mounted on a first package using peripheral solder ball z-interconnect, in which the first package includes a die enclosed by a mold cap and in which the second package includes one die mounted on the frame substrate.

Abstract: A circuit board includes a semiconductor substrate which has a plurality of through holes passing from an upper surface to a lower surface thereof. A plurality of wiring lines are provided on the upper surface of the semiconductor substrate and have bottomed cylindrical portions located within regions corresponding to the through holes. Bottom surfaces of the bottomed cylindrical portions of the wiring lines serve as connection pad portions.

Abstract: A device (1) comprising a sensor module (2) with a package (3) is produced at reduced costs by providing the package (3) with two or more substrates (4,5) each with a functional layer (14,15), at least one sensor (24,25) such as a magnetometer and/or an accelerometer being located in at least one functional layer (14,15), and by providing the package (3) with a system comprising solder bumps (7-12) for aligning the functional layers (14,15).

Abstract: A semiconductor component having a semiconductor chip mounted on a packaging substrate and a method for manufacturing the semiconductor component that uses batch processing steps for fabricating the packaging substrate. A heatsink is formed using an injection molding process. The heatsink has a front surface for mating with a semiconductor chip and a leadframe assembly. The heatsink also has a back surface from which a plurality of fins extend. The leadframe assembly includes a leadframe having leadframe leads extending from opposing sides of the leadframe to a central area of the leadframe. A liquid crystal polymer is disposed in a ring-shaped pattern on the leadframe leads. The liquid-crystal polymer is partially cured. The leadframe assembly is mounted on the front surface of the heatsink and the liquid crystal polymer is further cured to form a packaging assembly, which is then singulated into packaging substrates.

Abstract: A semiconductor device includes a semiconductor substrate having a main surface, the main surface including a first and second areas formed with a high-frequency circuit element, and a third area located around the first and second areas and formed with a low-frequency circuit element. The semiconductor device also includes a sealing resin which covers the main surface; a plurality of first external terminals which are formed above the third area and which are electrically connected to the high-frequency circuit element, the first external terminals protruding from the surface of the sealing resin. The semiconductor device further includes a plurality of second external terminals which are formed above the third area and which are electrically connected to the low-frequency circuit element, the second external terminals protruding from the surface of the sealing resin.

Abstract: A semiconductor module including multiple semiconductor devices prevents a signal that flows through a bonding wire connected to one semiconductor device from acting as noise which affects the other semiconductor devices, thereby improving the operation reliability of the semiconductor module. A second semiconductor device layered on a first semiconductor device includes a current output electrode via which large current is output. The current output electrode is electrically connected to a substrate electrode provided to a first wiring layer via a bonding wire. The bonding wire is provided across the side E1 of the second semiconductor device. A bonding wire connected to the first semiconductor device is provided across a side of the first semiconductor device other than the side F1 that corresponds to the side E1 of the second semiconductor device, i.e., across the side F2, F3, or F4 of the first semiconductor device.

Abstract: In a semiconductor module including multiple semiconductor devices, a signal that flows through a bonding wire connected to one semiconductor device is prevented from acting as noise which affects another semiconductor device, thereby improving the operation reliability of the semiconductor module. A second semiconductor device provided alongside a first semiconductor device includes a current output electrode via which large current is output. The current output electrode is electrically connected to a substrate electrode provided to a first wiring layer via a bonding wire such as a gold wire or the like. The bonding wire is provided across the side E2 which differs from the side E1 that faces the side face F1 of the first semiconductor device. Furthermore, the current output electrode is provided along the side E2.

Abstract: A semiconductor package and mounting method of improving reliability by strengthening adhesive strength of both a printed circuit board and a surface mounting package, includes a chip pad on which a semiconductor device is disposed, and lead terminals, wherein at least one of the chip pad and the lead terminals have a plurality of grooves. Accordingly, in comparison with a typical package, since a plurality of grooves are formed on both a chip pad and lead terminals of a package adhering to a printed circuit, an adhesive area of both the package and the cream solder is widened so that the shearing strength may be improved and greater solder joint reliability can be acquired.

Abstract: An exemplary glass substrate of flat panel display is adapted for an integrated circuit (IC) chip. The IC chip has two opposite long sides and two opposite short sides. The glass substrate includes a display area and a plurality of conductive wires. The display area has a plurality of display elements formed therein. The conductive wires are electrically coupled to the IC chip and the display area, to transmit a signal provided from the IC chip to the display area. The IC chip includes a plurality of output terminals arranged at the long sides and electrically coupled to the respective conductive wires. The present invention also provides a display IC chip for receiving and outputting a first color signal, a second color signal and a third color signal.

Abstract: A flip chip mounting method which is applicable to the flip chip mounting of a next-generation LSI and high in productivity and reliability as well as a method for connecting substrates are provided. A circuit board 10 having a plurality of connecting terminals 11 and a semiconductor chip 20 having a plurality of electrode terminals 21 are disposed in mutually facing relation and a resin 13 containing conductive particles 12 and a gas bubble generating agent is supplied into the space therebetween. In this state, the resin 13 is heated to generate gas bubbles 30 from the gas bubble generating agent contained in the resin 13. The resin 13 is pushed toward the outside of the generated gas bubbles 30 by the growth thereof. The resin 13 pushed to the outside is self-assembled in the form of columns between the respective terminals of the circuit board 10 and the semiconductor chip 20.

Abstract: An integrated circuit package system includes providing a substrate having a first plurality of conductive traces having a first width. An integrated circuit die is attached to the substrate. A mold clamp line is identified on the substrate. A critical area around the mold clamp line is determined. A plurality of widened conductive traces having a second width in the critical area is provided. An encapsulant encapsulates the integrated circuit die.

Abstract: A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.

Abstract: A semiconductor device includes a semiconductor element, a lead, and a gold wire electrically connecting an electrode of the semiconductor element and the lead. In the semiconductor device, the gold wire is covered with a metal and is a continuous film formed by plating.

Abstract: In this semiconductor device, connection parts between wafers are electrically insulated from each other, and a junction face shape of second electrical signal connection parts is larger than the shape of a positioning margin face that is formed by an outer shape when the periphery of a minimum junction face, which has half the area of a junction area of the first electrical signal connection part, is enclosed by a same width dimension as a positioning margin dimension between the first wafer and the second wafer.

Abstract: Packaged integrated circuits and methods to form a packaged integrated circuit are disclosed. A disclosed method comprises attaching an integrated circuit to a substrate, coupling a first end of a bond wire directly to the substrate without an intervening bonding pad and a second end of the bond wire to a contact of the integrated circuit, encapsulating the integrated circuit and the bond wire, and removing the substrate to expose the first end of the bond wire.

Abstract: A semiconductor package substrate and a method for fabricating the same are proposed. An insulating layer has a plurality of blind vias to expose inner traces underneath the insulating layer. A conductive film is formed on the insulating layer and over the bind vias. A first resist is formed on the conductive film, having openings to expose parts of the conductive film. A patterned trace layer including a plurality of contact pads is formed in the openings and the blind vias to form conductive vias, with at least one contact pad electrically connected to one conductive via. A second resist is formed on the patterned trace layer without covering the contact pads. A metal barrier layer is formed on the contact pads. Finally, the first and second resists and parts of the conductive film covered the first resist are removed.

Abstract: A signal transfer film includes a base film, a lead line formed on the base film and a passivation layer protecting the lead line. The passivation layer includes a nonlinear edge portion formed at a boundary region between the lead line and the passivation layer. The nonlinear edge portion of the passivation layer disperses a stress concentrated to the boundary region in various directions when the base film is bent. Thus, the signal transfer film may prevent breaking of the lead line, thereby enhancing yield thereof.

Abstract: A semiconductor device has a chip, a first bump electrode, a conductive wire and a second bump electrode. The chip has at least one contact pad, and the first bump electrode is formed on the contact pad. The conductive wire is disposed on an active surface of the chip and electrically connected to the first bump electrode. The second bump electrode is formed on the conductive wire, and the second bump electrode is not disposed over any contact pad of the chip. In addition, a method for packaging a chip and an IC package are also disclosed.

Abstract: A packaged semiconductor includes inner bond fingers, at least first and second semiconductor dies, and an interposer. The packaged semiconductor further includes wiring between the first and second semiconductor dies and the inner bond fingers, wiring between the interposer and the inner bond fingers, and wiring between the interposer and the first and second semiconductor dies. The wiring between the interposer and the first and second semiconductor dies thereby reduces the count of inner bond fingers needed for the wiring between the first and second semiconductor dies and the inner bond fingers. The interposer further provides indirect access to the inner bond fingers when the inner bond fingers are inaccessible by the first and second semiconductor dies.

Abstract: A semiconductor apparatus of the present invention includes: (i) a wire substrate having an insulating substrate in which a plurality of wire patterns are provided, (ii) a semiconductor element installed on the wire substrate with the insulating resin interposed therebetween, and a plurality of connecting terminals provided in the semiconductor element are electrically connected to connecting terminals of the wire patterns, respectively. In the semiconductor apparatus, the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns, and an entire upper face of each of the mark patterns is covered with the insulating resin.

Abstract: Electrode pads (5) and a solder resist (7) are disposed on the upper surface of a wiring board (1), and apertures (7a) are formed in the solder resist (7) so as to expose the electrode pads (5). Electrodes (4) are disposed on the lower surface of a semiconductor element (2). Electrodes (4) are connected to the electrode pads (5) by way of bumps (3). An underfill resin (6) is disposed in the area that excludes the solder resist (7) and the bumps (3) in the space between the wiring board (1) and the semiconductor element (2). Between the wiring board (1) and the semiconductor element (2), the thickness (B) of the solder resist (7) is equal to or greater than the thickness (A) of the underfill resin (6) on the solder resist (7). The volume (Vb) of the bumps (3) is less than the volume (Vs) of the apertures (7a).

Abstract: A semiconductor package mainly includes a chip, a substrate, an encapsulant, a plurality of external terminals and a stress release layer. The substrate has an upper surface and a lower surface. The chip is disposed on the upper surface of the substrate by a chip-attached layer and electrically connected to the substrate. The encapsulant is formed above the upper surface of the substrate. The external terminals are disposed on the lower surface of the substrate. The stress release layer is formed on the interface of the substrate and the encapsulant such that the external terminals are movable with respect to the encapsulated chip. In addition, a fabrication process of the semiconductor package is also disclosed.

Abstract: Consistent with an example embodiment, an electronic device comprises a semiconductor device, particularly an integrated circuit, and a carrier substrate with conductive layers on the first side and the second side, and voltage supply and ground connections mutually arranged according to a chessboard pattern. These connections extend in a direct path through vertical interconnects and bumps to bond pads at the integrated circuit, which bond pads are arranged in a corresponding chessboard pattern. As a result, an array of direct paths is provided, wherein the voltage supply connections form as much as possible the coaxial center conductors of a coaxial structure.

Abstract: A structure includes a circuit substrate including a first substrate and a second substrate. The first substrate has a region where an electronic component is to be mounted. The second substrate has a side surface connected to a first side surface of the first substrate. The structure further includes a frame on the circuit substrate, enclosing the region in a plane view. The frame crosses the boundary between the first substrate and the second substrate.

Abstract: Packaged semiconductor components, apparatus for packaging semiconductor devices, methods of packaging semiconductor devices, and methods of manufacturing apparatus for packaging semiconductor devices. One embodiment of an apparatus for packaging semiconductor devices comprises a first board having a front side, a backside, arrays of die contacts, arrays of first backside terminals electrically coupled to the die contacts, arrays of second backside terminals, and a plurality of individual package areas that have an array of the die contacts, an array of the first backside terminals, and an array of the second backside terminals.

Abstract: An optical module of the present invention includes: a semiconductor device 14; a grounded metal member 10 for mounting the semiconductor device 14 thereon; a substrate 16 for mounting the grounded metal member 10 thereon; and a lead pin 18 fixed to and insulated from the grounded metal member 10 and soldered to the substrate 16, the lead pin 18 being used to supply power to the semiconductor device 14; wherein the grounded metal member 10 has a protrusion on a surface thereof facing the substrate 16; and wherein the protrusion of the grounded metal member 10 is in contact with the substrate 16.

Abstract: A semiconductor device includes two semiconductor chips having different guarantee temperatures, which are individually mounted on two stages distanced from each other and are sealed with a resin mold. One semiconductor chip includes a heating circuit causing a heating temperature that is higher than the guarantee temperature of another semiconductor chip, and the backside of the stage thereof is exposed externally of the resin mold. This reduces the amount of heat transmitted from one semiconductor chip to another semiconductor chip, thus improving the reliability of the semiconductor device. Alternatively, two semiconductor chips having different heights are mounted on a single stage, wherein one semiconductor chip causing a high heating temperature is lowered in height in comparison with another semiconductor chip, thus increasing the heat-transmission path between the semiconductor chips and thus reducing the heat-dissipation path for dissipating heat of one semiconductor chip to a substrate.

Abstract: A semiconductor device comprises a package board, a first semiconductor chip which is rectangular in shape, has a plurality of first pads arranged along its short side and is placed on the package board, and a second semiconductor chip which is rectangular in shape, has a plurality of second pads arranged along its short side and is placed on the first semiconductor chip so that a vertex of the second semiconductor chip at which its long side and its short side along which no pads are arranged meet falls on a vertex of the first semiconductor chip at which its long side and its short side along which no pads are arranged, and the long sides of the first and second semiconductor chips intersect each other.

Abstract: The present invention provide a wafer level chip size packaged chip device with a N-shape junction at which external leads electrically connect to peripheral arrayed compatible pads and a method of fabricating the same. In the wafer level chip size package, with such an n-shape junction instead of a conventional T-shape junction observed in Shellcase type wafer level chip size package technology, electrical connections between compatible pads and external leads are more reliable due to larger connection area than the counterpart in the T-shape junction.

Abstract: The assembly comprises an electronic device (20) that is attached to a first side (11) of a carrier substrate (10) with solder connections (18). The first side (11) of the substrate (10) is provided with bond pads (15) and a solder resist layer (16). The space between the substrate (10) and the electronic device (20) is filled with an encapsulant (19) The substrate (10) further comprises contact pads for connection to an external board. The solder resist layer (16) is patterned according to a pattern that includes an aperture (161) adjacent to a first bond pad (15). This aperture (161) is ring-shaped and forms the circumference of the first bond pad. Herewith, delamination is prevented, also if a via (142) is present in the substrate (10) below the bond pad (15).

Abstract: A semiconductor device includes: an insulating tape having a device hole and a plurality of holes; a plurality of leads formed on one surface of the tape and extending at one end into the device hole and at the other end into the holes; a semiconductor chip having a plurality of electrodes on a main surface thereof, being connected with the leads extending into the device hole; an encapsulant formed of an insulating resin, the leads and a predetermined portion of the tape; bump electrodes provided on one surface of the leads; slits provided in the tape between the encapsulant and the bump electrodes and extending along a column of the bump electrodes; and a warp prevention reinforcement made of an insulating film and formed over the tape; wherein the semiconductor chip and the bump electrodes are connected to one and the same surface side of the leads.

Abstract: An assembly includes a structure, a plurality of terminals and a plurality of compliant pads disposed between said terminals and said structure. The terminals are aligned with at least some of said pads, with the pads providing a standoff between the structure and the terminals. The compliant pads are preferably made of a non-conductive material such as a silicone elastomer.

Abstract: A packaged chip is provided which includes a package element on which a signal-bearing conductive trace has an edge laterally adjacent to an edge of a reference conductive trace (e.g., ground trace) on the same face of a dielectric element, the two traces together functioning as a capacitor. In a particular embodiment, the laterally adjacent traces provide shunt capacitance to compensate for an inductance in a signal path to the chip which includes the signal-bearing conductive trace. In a variation thereof, a transmission line or waveguide is provided which includes the signal-bearing conductive trace and reference trace. In further variations, transmission lines are provided which include one or more metal layers of a package element, separated from each other by a thickness of a dielectric element included in the package element or the air gap between the package and a circuit panel.

Abstract: A multilayered printed wiring board having a ball grid array (BGA) land pattern in which each land in the pattern is connected to a respective via by a link connector, a method of adapting spacing between selected adjacent via and respective link pairs to receive decoupling capacitor pads, comprising rotating, elongating and/or truncating the selected adjacent pairs and rotating their respective corresponding via pairs to adapt the spacing between the selected adjacent via pairs in the BGA land pattern and applying the capacitor pads to the selected via pairs. The selected adjacent via pairs and their respective link connectors are rotated, elongated and/or truncated in mutually opposite directions.

Abstract: In a semiconductor device in which a plurality of substrates each mounting a semiconductor chip are stacked, one ends of the leads formed on the substrates are connected to the semiconductor chip and the other ends thereof are connected to connection terminals of the substrates. At least one of the leads are branched into two or more in the vicinity of the connection terminals, and one ends of the branched leads are connected to the connection terminals. A technique for sorting good products is performed in a state in which the chips are mounted on the substrates.

Abstract: A device having a substrate, a pair of ferromagnetic leads on a surface of the substrate, laterally separated by a gap, and one or more ferromagnetic microparticles comprising a conductive coating at least partially within the gap. The conductive coating forms at least part of an electrical connection between the leads. A molecular junction may connect the leads to the microparticle.

Abstract: An integrated circuit package system is provided including forming a mounting structure having an external interconnect, a paddle, and a tie bar; mounting an integrated circuit die on the paddle; soldering a stiffener structure; having an opening; on the mounting structure; connecting the stiffener structure to a ground; and molding the integrated circuit die and partially the stiffener structure through the opening.

Abstract: A chip-mounted film package includes a base film, an effective film package defined on the base film by a cutting line, a driving chip mounted on the effective film package, a plurality of input pads arranged on an input area of the effective film package and connected to the driving chip, and a plurality of output pads arranged on an output area of the effective film package and connected to the driving chip, wherein the output area includes at least one extended portion that protrudes from a side of the effective film package in a horizontal direction of the base film.

Abstract: A semiconductor device is provided including a substrate containing a wire pattern having a plurality of leads and a semiconductor chip mounted on the substrate in a manner that an electrode faces the wire pattern. The electrodes are arranged to be classified into a plurality of first groups respectively lined along a plurality of paralleling first straight lines and into a plurality of second groups respectively lined along a plurality of second straight lines extending in a direction so as to intersect with the first straight lines. Each lead includes a connecting part facing one electrode, an extension part extending along the first straight line from the connecting part, and a draw-out part that is drawn from the extension part so as to intersect with the first straight line.