Abstract: An MEMS chip is mounted face-down on a semiconductor wafer such that a movable section is opposed to the semiconductor wafer. A resin layer is formed on the semiconductor wafer around the MEMS chip to reduce a step between the MEMS chip and the semiconductor wafer. After the semiconductor substrate is removed, the land electrode is formed on the resin layer.

Abstract: A lead frame base is coated with a four-layer plating. The four-layer plating includes an underlayer plating (Ni), a palladium plating, a silver plating and a gold plating arranged in this order from bottom to top.

Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: an L-plated lead; a die conductively connected to the L-plated lead; and an encapsulant encapsulating the L-plated lead and the die.

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a first conductor pad and a passivation structure. A second conductor pad is fabricated around but not in physical contact with the first conductor pad to leave a gap. The second conductor pad is adapted to protect a portion of the passivation structure.

Abstract: A radiation-emitting semiconductor body with a carrier substrate. A structured connection is produced between a semiconductor layer sequence (2) and a carrier substrate wafer (1). The semiconductor layer sequence is subdivided into a plurality of semiconductor layer stacks (200) by means of cuts (6) through the semiconductor layer sequence, and the carrier substrate wafer (1) is subdivided into a plurality of carrier substrates (100) by means of cuts (7) through the carrier substrate wafer (1). In the method, the structured connection is formed in such a way that at least one semiconductor layer stack (200) is connected to one and only one associated carrier substrate (100). In addition, at least one cut (7) through the carrier substrate wafer is not extended by any of the cuts (6) through the semiconductor layer sequence such that a straight cut results through the carrier substrate wafer and the semiconductor layer sequence.

Abstract: A power semiconductor module comprises at least one power semiconductor component and a connection device which makes contact with the power semiconductor component. The connection device is composed of a layer assembly having at least one first electrically conductive layer facing the power semiconductor component and forming at least one first conductor track, and an insulating layer following in the layer assembly, and a second layer following further in the layer assembly and forming at least one second conductor track, the second layer being remote from the power semiconductor component. The power semiconductor module has at least one internal connection element, wherein the internal connection element is embodied as a contact spring having a first and a second contact section and a resilient section. The first contact section has a common contact area with a first or a second conductor track of the connection device.

Abstract: A stacked package and method of manufacture are provided. The stacked package may include a first semiconductor package, a second semiconductor package, plugs and spacers. The second semiconductor package may be stacked on the first semiconductor package. The plugs may electrically connect the first semiconductor to the second semiconductor package. The spacer may be interposed between the first semiconductor package and the second semiconductor package to form a gap between the first semiconductor package and the second semiconductor package, thereby preventing an electrical short between the plugs.

Abstract: A bump array structure for an integrated circuit is presented. An array of metal alloy bumps is disposed on a surface of the integrated circuit. The array of metal alloy bumps is configured to receive input from a multi-layer substrate package and transmit output to the multi-layer substrate package. The array defines a first portion of metal alloy bumps around the periphery of the surface of the integrated circuit configured to provide power and ground signals for the integrated circuit. The array further defines a second portion of metal alloy bumps providing power and ground for the integrated circuit, located between opposing sides of the periphery of the integrated circuit. Metal alloy bumps not contained in either the first or the second portion of the array are configured for input and output signals between the integrated circuit and the multi-level substrate package.

Abstract: An elongated bump structure for semiconductor devices is provided. An uppermost protective layer has an opening formed therethrough. A pillar is formed within the opening and extending over at least a portion of the uppermost protective layer. The portion extending over the uppermost protective layer exhibits a generally elongated shape. In an embodiment, the position of the opening relative to the portion of the bump structure extending over the uppermost protective layer is such that a ratio of a distance from an edge of the opening to an edge of the bump is greater than or equal to about 0.2. In another embodiment, the position of the opening is offset relative to center of the bump.

Abstract: A metal post chip connecting device without soldering materials is revealed, primarily comprising a chip and a substrate. A plurality of metal pillars are disposed on and extruded from a surface of the chip where each metal pillar has an end surface and two corresponding parallel sidewalls. The substrate has an upper surface and a plurality of bonding pads disposed on the upper surface where each bonding pad has a concaved bottom surface and two corresponding concaved sidewalls. The chip is bonded onto the upper surface of the substrate through heat, pressure, and ultrasonic power so that the end surfaces of the metal pillars self-solder to the concaved bottom surfaces and two parallel sidewalls of the metal pillars partially self-solder to two concaved sidewalls to form U-shape cross-sections of metal bonding between the metal pillars and the bonding pads.

Abstract: A device comprises a semiconductor chip including an edge elongated in a first direction. A plurality of first pads is formed on the semiconductor chip. The first pads are substantially equal in length in the first direction to each other. A second pad is formed on the semiconductor chip. The second pad is greater in length in the first direction than the first pads. The first pads and the second pad are arranged in a line elongated in the second direction, that is substantially perpendicular to the first direction, without an intervention of any one of the first pads between the second pad and the edge.

Abstract: In a method of manufacturing a semiconductor-device mounted board, connection terminals are formed on electrode pads on a semiconductor integrated circuit respectively. A first insulating layer is formed to cover the connection terminals. A plate-like medium having a rough surface is disposed on the first insulating layer. The rough surface of the plate-like medium is pressed onto the first insulating layer so that a part of each of the connection terminals is exposed. A semiconductor device is produced by removing the plate-like medium. A second insulating layer is formed to cover side surfaces of the semiconductor device. A wiring pattern is formed to cover surfaces of the first and second insulating layers, the wiring pattern being electrically connected to the exposed connection terminal parts.

Abstract: In some aspects of the invention, an insulating substrate fixed onto a metal base plate can include an insulating plate and metal foils. A semiconductor element can be disposed on each of the metal foils. External connection terminals can be fixed to a set of ends of terminal holders, respectively. The other ends of the terminal holders can be bonded to the metal foils, respectively. External connection terminals which are main terminals through which main current flows are disposed on a lid. By preparing a plurality of lids having different layouts of the external connection terminals, in which the external connection terminals are connected to the terminal holders in the resin case, respectively, and exchanging the lids, the positions of the external connection terminals can be easily changed.

Abstract: To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.

Abstract: A semiconductor device includes: a semiconductor chip including a main surface electrode; a first mounting lead; a second mounting lead; a connection lead which overlaps with the main surface electrode, the first mounting lead and the second mounting lead when viewed in a thickness direction of the semiconductor chip and makes electrical conduction between the main surface electrode, the first mounting lead and the second mounting lead; and a resin portion which covers the semiconductor chip, the first mounting lead and the second mounting lead, wherein the resin portion has a resin bottom lying on the same plane as a bottom of the first mounting lead and a bottom of the second mounting lead.

Abstract: In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes.

Abstract: A semiconductor package which is structured to allow for the edge mounting thereof in a vertical mount orientation. The semiconductor package comprises a flexible substrate or “flex circuit.” The flexible substrate includes a conductive pattern disposed on a first surface thereof, and a plurality of conductive pads or terminals disposed on a second surface thereof which is disposed in opposed relation to the first surface. Mounted to the first surface of the flexible substrate are one or more electronic components such as semiconductor dies. The semiconductor die(s) is/are electrically connected to the conductive pattern, and thereafter covered or encapsulated by a package body applied to a portion of the first surface of the flexible substrate. That portion of the flexible substrate including the conductive pads or terminals formed on the second surface thereof is thereafter folded and adhered to a portion of the package body through the use of a suitable adhesive.

Abstract: Electronic assemblies and their manufacture are described. One assembly includes a substrate and a die on a first side of the substrate. A plurality of non-solder metal bumps are positioned on a second side of the substrate. The assembly also includes a board to which the non-solder metal bumps are coupled. The assembly also includes solder positioned between the board and the substrate, wherein the board is electrically coupled to the substrate through the solder and the bumps. Other embodiments are described and claimed.

Abstract: The present invention provides a three-dimensional System-In-Package (SIP) Package-On-Package (POP) structure comprising a support element formed around a first electronic device. A filling material is filled between the first electronic device and the support element. Signal channels are coupled to first die pads of the first electronic device. Conductive elements form signal connection between the first end of the signal channels and the second die pads of a second electronic device.

Abstract: A device may includes a first conductive film, a first insulating film, a second conductive film, a third conductive film, and a fourth conductive film. The first conductive film includes copper. The first insulating film is disposed over the first conductive film. The first insulating film has a first contact hole. The contact hole reaches a first surface of the first conductive film. The second conductive film includes aluminum. The second conductive film is disposed in the first contact hole. The third conductive film includes titanium nitride. The third conductive film is disposed in the contact hole. The third conductive film covers a part of the first surface of the first conductive film. The fourth conductive film is free of titanium nitride. The fourth conductive film is disposed between the second and third conductive films.

Abstract: A semiconductor component of the present invention includes a semiconductor element and a joining layer formed on one surface of the semiconductor element and consisting of a joining material containing Bi as an essential ingredient, and projecting sections are formed on a surface of the joining layer on a side opposite to a surface in contact with the semiconductor element. By joining the semiconductor component to an electrode arranged so as to face the joining layer, the generation of a void can be suppressed.

Abstract: A hard mask composition includes a solvent and an aromatic ring-containing compound represented by the following Chemical Formula 1:

Abstract: A wiring substrate includes a plurality of connection pads, and a protection insulating layer in which opening portion exposing said plurality of connection pads collectively is provided, wherein a notched opening portion is provided to a sidewall of the opening portion of the protection insulating layer in area between said plurality of connection pads. When a semiconductor chip is flip-chip connected to the connection pads by the prior sealing technology, a void occurring in the sealing resin is trapped in the notched opening portion.

Abstract: A semiconductor module according to one embodiment includes a semiconductor chip, an insulating substrate, a case, an electrode, a busbar and a busbar support body. The semiconductor chip is mounted on the insulating substrate. The insulating substrate is housed inside the case. The electrode is disposed in the case and is electrically connected to the semiconductor chip. The electrode is supported on an electrode support section of the case. The busbar is bonded to the electrode and is led out of the case. The busbar support body holds the busbar and is mounted on the case.

Abstract: A semiconductor device includes a wiring board, a stack of semiconductor chips, and a first sealing member. The wiring board has a first surface. The wiring board includes a first insulating layer formed over the first surface. The first insulating layer has a first opening. The stack of semiconductor chips is mounted over the first surface of the wiring board. The stack of semiconductor chips includes a first semiconductor chip. The first semiconductor chip is closer to the wiring board than the other semiconductor chips. The first sealing member seals at least the first semiconductor chip. The first sealing member includes a protruding portion. The first opening of the insulating layer faces toward the protruding portion of the first sealing member.

Abstract: A semiconductor package includes a package substrate including a first wiring embedded in the package substrate, a second wiring embedded in the package substrate, the second wiring electrically insulated from the first wiring, and a capacitor embedded in the package substrate, the capacitor including a first electrode electrically connected to the first wiring and a second electrode electrically connected to the second wiring. At least a first semiconductor chip is disposed on the package substrate. A plurality of connection terminals are disposed between the package substrate and the first semiconductor chip and contact the package substrate, and form at least a first group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the first wiring, and at least a second group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the second wiring.

Abstract: A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 ?m or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring.

Abstract: A high melting point soldering layer includes a low melting point metal layer, a first high melting point metal layer disposed on a surface of the low melting point metal layer, and a second high melting point metal layer disposed at a back side of the low melting point metal layer. The low melting point metal layer, the first high melting point metal layer, and the second high melting point metal layer are mutually alloyed by transient liquid phase bonding, by annealing not less than a melting temperature of the low melting point metal layer, diffusing the metal of the low melting point metal layer into an alloy of the first high melting point metal layer and the second high melting point metal layer. The high melting point soldering layer has a higher melting point temperature than that of the low melting point metal layer.

Abstract: A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.

Abstract: Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the openings of a dielectric layer on the bottom surface, the solder bumps forming connections to the bond pads. An interposer having a die side surface and a board side surface is provided having bump lands receiving the solder bumps of the molded chip structure on the die side of the interposer. An underfill layer is formed between the die side of the interposer and the bottom surface of the molded chip structure surrounding the solder bumps. Methods for forming the molded chip interposer structure are disclosed.

Abstract: A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device electrically connects an electrode provided on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The metal substrate is provided on one side of the insulating layer. The copper wiring layer is provided on another side of the insulating layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode provided on the semiconductor chip. The second terminal is connected with the external wiring device.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a hole, a recess, and a pad, the hole over the recess; mounting an integrated circuit to the package paddle; forming a lead having a bottom surface coplanar with a bottom surface of the pad, the lead isolated from the package paddle; attaching connectors directly on the integrated circuit, the lead, and the package paddle; and forming an encapsulation covering the integrated circuit and within the hole and the recess.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an elevated contact above and between a lead and a die pad that is coplanar with the lead; connecting an integrated circuit and the lead; attaching a jumper interconnect between the elevated contact and the lead; and forming an encapsulant over the integrated circuit, the lead, the die pad, the elevated contact, and the jumper interconnect, the encapsulant having a recess in a base side with the elevated contact exposed in the recess and the lead exposed from the base side.

Abstract: In a semiconductor module where a metal sheet, an insulating layer and a circuit element are stacked in a manner that the insulating layer is penetrated with a bump structure, the connection reliability of the bump structure and the circuit element is enhanced. A semiconductor wafer is prepared where a semiconductor substrate having electrodes and protective film on the surface are arranged in a matrix shape. On the surface of the semiconductor substrate, an insulating layer is held between the substrate and a copper sheet, integrally formed with bumps, having grooves in the vicinity of the bumps. The semiconductor substrate, the insulating layer and the copper sheet are press-bonded by a press machine into a single block. The bump penetrates the insulating layer, and the bump and the electrode are electrically connected together. An extra part of the insulating layer pushed out by the bump flows into the groove.

Abstract: A semiconductor device includes an interlayer film formed over a semiconductor substrate. A groove is formed in the interlayer film. A wiring formed in the groove is a copper alloy including copper and a metal element. An oxide layer of the metal element is formed over the surface of the wiring. The oxide layer is formed in a first region along a grain boundary of a copper crystal and a second region surrounded by the grain boundary, over the surface of the wiring. The oxide layer formed in the first region has a thickness greater than that of the oxide layer formed in the second region.

Abstract: A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.

Abstract: A method for producing an electrical circuit having at least one semiconductor chip is disclosed. The method includes forming a wiring layer at a contact side of the at least one semiconductor chip, which is encapsulated with a potting compound apart from the contact side. The wiring layer has at least one conductor loop for the purpose of forming an electrical coil.

Abstract: There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

Abstract: Apparatus and methods for providing a package substrate and assembly for a flip chip integrated circuit. A substrate is provided having a solder mask layer, openings in the solder mask layer for conductive bump pads, and openings in the solder mask layer between the conductive bump pads exposing a dielectric layer underneath the solder mask layer. A flip chip integrated circuit is attached to the substrate using a thermal reflow to reflow conductive solder bumps on the integrated circuit to the conductive bump pads. An underfill material is dispensed beneath the integrated circuit and physically contacting the dielectric layer of the substrate. In additional embodiments, one or more integrated circuits are flip chip mounted to the substrate. The resulting assembly has improved thermal characteristics over the assemblies of the prior art.

Abstract: A semiconductor device is made by forming first and interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.

Abstract: A mounting structure includes: at least one semiconductor device having solder bumps as outer terminals and a flexible wiring board with wiring formed thereon. The semiconductor device is structured to be wrapped by the flexible wiring board, the mounting structure is provided with outer electrodes on both sides of the flexible wiring board, one side being a side where outer terminals of the semiconductor device are formed, and the other side being an opposite side thereof. At least one wiring layer is formed on the flexible wiring board. A supporting member is provided covering side faces and a surface of the semiconductor device opposite to the side where the outer terminals are formed and protruding from the side faces of the semiconductor device and extending toward the surface on which the outer terminals are formed.

Abstract: A circuit board has an insulative layer including a first surface and a second surface opposite to the first surface. A plurality of electrically conductive patterns is formed on the first surface of the insulative layer. Conductive lands are formed in a die mounting region of the first surface of the insulative layer and electrically connected to one of the plurality of conductive patterns on the first surface. An extending pattern extends from the conductive lands to outside of the mounting region. A protective layer covers the first surface of the insulative layer and the electrically conductive patterns. A trench is formed in the protective layer to expose the conductive lands and the extending patterns.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device; forming package interconnects adjacent the integrated circuit device, the package interconnects having an internal interconnect side with a lock structure; applying an encapsulation over the integrated circuit device and the package interconnects, the lock structure conformally filled with the encapsulation; and forming a base cavity with sides formed by the encapsulation and an external interconnect side of each of an adjacent pair of package interconnects facing one another, the base cavity having a cross-sectional length at least two times a cross-sectional width.

Abstract: There is provided an LED package having high heat dissipation efficiency. An LED package according to an aspect of the invention may include: a package body including a first groove portion being recessed into the package body and provided as a mounting area on the top of the package body; first and second lead frames arranged on a lower surface of the first groove portion while parts of the first and second lead frames are exposed; an LED chip mounted onto the lower surface of the first groove portion and electrically connected to the first and second lead frames; and a plurality of heat dissipation patterns provided on the bottom of the package body and formed of carbon nanotubes.

Abstract: A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.

Abstract: A disclosed circuit board includes a substrate, a plurality of electrode pads formed on the substrate, and a groove formed between adjacent electrode pads on the substrate. Further, the electrode pads are surrounded by the groove to have an air space between the adjacent electrode pads.

Abstract: A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chi on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.

Abstract: A package structure and a package substrate thereof are provided. The package structure includes a package substrate, a chip and a molding compound. The package substrate has an upper surface and a lower surface. The lower surface has a molding area and a pad area. The molding area has at least one window opening penetrating the upper surface and the lower surface. The pad area is used for disposing at least one solder ball or at least one connecting pin. The package substrate includes a solder mask. The solder mask covers the lower surface of the package substrate. The solder mask has at least one groove. The groove is disposed between the molding area and the pad area. The chip disposed on the package substrate has an active surface. The active surface contacts with the upper surface of the package substrate. The molding area is covered by the molding compound.