Abstract: A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming a channel through the integrated circuit; forming an indent, having a flange and an indent side, from a peripheral region of the non-active side; and forming a conformal interconnect, having an offset segment, a sloped segment, and a flange segment, under the indent.

Abstract: A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.

Abstract: A semiconductor device has a conductive layer formed on a substrate. The conductive layer has a first portion constituting contact pads and a second portion constituting an integrated passive device such as an inductor. A spacer is formed on the substrate around the second portion of the conductive layer. The spacer can be insulating material or conductive material for shielding. A semiconductor die is mounted to the spacer. An electrical connection is formed between contact pads on the semiconductor die and the contact pads on the substrate. An encapsulant is formed around the semiconductor die, electrical connections, spacer, and conductive layer. The substrate is removed to expose the conductive layer. An interconnect structure is formed on the backside of the substrate. The interconnect structure is electrically connected to the conductive layer. The semiconductor device can be integrated into a package.

Abstract: Semiconductor device 1 according to the present invention includes wiring board 8 having mounting surface 8a mounted with laminated semiconductor chips 2 and plural semiconductor chips 2 mounted on mounting surface 8a of wiring board 8. Plural semiconductor chips 2 mounted on mounting surface 8a of wiring board 8 include second semiconductor chips 2b with circuit formation surfaces 3 directed to the mounting surface 8a side of wiring board 8 and first semiconductor chips 2a with circuit formation surfaces 3 directed to the opposite side of the mounting surface 8a side of wiring board 8.

Abstract: A wiring board includes a substrate made of an insulation material and wired by a conductive material. A plurality of electrodes is formed on a surface of the substrate. A non-Au electrode not having an Au surface layer and an Au electrode having the Au surface layer are formed as the electrodes.

Abstract: A microelectronic element package has one or more individual carrier units overlying a region or regions of the front or rear surface of the microelectronic element, leaving other regions of the microelectronic element surface uncovered. The carrier units can be made economically using only a small area of a dielectric film or other circuit panel material.

Abstract: A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

Abstract: A semiconductor package comprising a first semiconductor sub-package (40) having a connection face (44) with un-supported connectors (21) depending therefrom arranged to electrically connect a first semiconductor device contained therein to an external circuit, and at least one second semiconductor sub-package (42) also having a connection face (46) with un-supported connectors (25) depending therefrom arranged to electrically connect a second semiconductor device contained therein to an external circuit, the second semiconductor sub-package (42) also having an attachment face (48), on an opposite side thereof from the connection face (46); wherein the second semiconductor sub-package (42) is mounted on the first semiconductor sub-package (40) such that its attachment face (48) is coupled to the connection face (44) of the first semiconductor sub-package (40).

Abstract: A semiconductor package system includes providing a substrate having a plurality of thermal vias extending through the substrate. A solder mask is positioned over the plurality of thermal vias. A plurality of thermally conductive bumps is formed on at least some of the plurality of thermal vias using the solder mask. An integrated circuit die is attached to the plurality of thermally conductive bumps. An encapsulant encapsulates the integrated circuit die.

Abstract: An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.

Abstract: There is provided a flip-chip substrate which is flip-chip connected to electrode terminals provided on one surface of an electronic component. The flip-chip substrate includes: mounting pads which are exposed to a surface of the flip-chip substrate on which the electronic component is mounted and each of which comprises a pad surface which is flip-chip connected to a corresponding one of the electrode terminals; wiring patterns which are electrically connected to the mounting pads; an insulating layer which covers the wiring patterns; and a solder resist formed on an entire surface of the insulating layer such that each pad surface of the mounting pads is exposed from the solder resist.

Abstract: In a manufacturing process of a semiconductor device, electroplating and CMP have had a problem of increase in manufacturing costs for forming a wiring. Correspondingly, an opening is formed in a porous insulating film after a mask is formed thereover, and a conductive material containing Ag is dropped into the opening. Further, a first conductive layer is formed by baking the conductive material dropped into the opening by selective irradiation with laser light. Subsequently, a metal film is formed over the entire surface by sputtering, and the mask is removed thereafter to have only the metal film remain over the first conductive layer, thereby forming an embedded wiring layer formed with a stack of the first conductive layer containing Ag and the second conductive layer (metal film).

Abstract: Provided is a semiconductor package including a mark pattern and a method of manufacturing the same. The semiconductor package may include at least one semiconductor chip including a circuit region, a protection layer covering the circuit region, a molding portion sealing the protection layer and the at least one semiconductor chip, the molding portion having an exposed top surface on the circuit region, and a mark pattern at the top surface of the molding portion. A method of fabricating the semiconductor package may include providing at least one semiconductor chip including a circuit region, forming a protection layer covering the circuit region, forming a molding portion sealing the protection layer and the at least one semiconductor chip, the molding portion having an exposed top surface on the circuit region, and forming a mark pattern at the top surface of the molding portion using a laser.

Abstract: A conductive composition includes a mono-acid hybrid that includes an unprotected, single reactive group. The mono-acid hybrid may include substantially non-reactive groups elsewhere such that the mono-acid hybrid is functional as a chain terminator. Methods and devices using the compositions are also disclosed.

Abstract: A system and method for forming an embedded chip package is disclosed. The embedded chip package includes a first chip portion having a plurality of pre-patterned re-distribution layers joined together to form a pre-patterned lamination stack, with the pre-patterned lamination stack having a die opening extending therethrough. The embedded chip package also includes a die positioned in the die opening and a second chip portion having at least one uncut re-distribution layer, with the second chip portion affixed to each of the first chip portion and the die and being patterned to be electrically connected to both of the first chip portion and the die.

Abstract: A low cost flexible substrate is described which comprises a thin metal foil and a layer of solder mask. The metal foil layer is patterned to create tracks and lands for solder bonding and/or wirebonding and the layer of solder mask is patterned to create openings for solder bonding, wirebonding and/or for mounting the die. The substrate may be used as a package substrate to create a packaged die or may be used as a replacement for more expensive flexible printed circuit boards.

Abstract: A device is provided in which a glass panel having beveled edge is flexibly connected to a TAB package. The outer lead portions of the TAB package include an end portion of first width connected to a connection pattern on the glass panel, a terminal portion having a second width greater than the first width, and a transition portion having a width that varies between the first and second widths. When the TAB package is connected the transition portion of the respective outer lead portions are disposed over the beveled edge of the glass panel.

Abstract: The semiconductor device package structure includes a first die with a through silicon via (TSV) open from back side of the first die to expose bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via (TSV); a substrate with a second die embedded inside and top circuit wiring and bottom circuit wiring on top and bottom side of the substrate respectively; and a conductive through hole structure coupled between the terminal metal pads to the top circuit wiring and the bottom circuit wiring.

Abstract: An advanced quad flat non-leaded package structure includes a carrier, a chip and a molding compound. The carrier includes a die pad and a plurality of leads. The die pad has a central portion, a peripheral portion disposed around the central portion and a plurality of connecting portions connecting the central portion and the peripheral portion. The central portion, the peripheral portion, and the connecting portions define at least two hollow regions. The leads are disposed around the die pad. The chip is located within the central portion of the die pad and electrically connected to the leads via a plurality of wires. The molding compound encapsulates the chip, the wires, inner leads and a portion of the carrier.

Abstract: In accordance with one or more embodiments, a flange package comprises a flange and an interposer having two or more fingers disposed in an interposer trench. The flange has a mold lock formed about a periphery of the interposer trench. A dielectric ring comprising a dielectric material is formed in the interposer trench, and in and around the periphery of the mold lock. A semiconductor die is disposed within the dielectric ring having gate pads and source pads formed on a first side, and having drain pads disposed on a second side of the die. The gate pads are coupled to the interposer and the source pads are coupled to the flange. A gate lead is coupled to the interposer and a drain lead is coupled to the drain pads. Other embodiments are disclosed.

Abstract: In this semiconductor chip 3, a table electrode 13 is interposed between a bump electrode 14 and an electrode pad 6. The table electrode 13 is formed by forming a plurality of cores 15 having a smaller Young's modulus than the bump electrode 14, on the electrode pad 6, and then covering the surfaces of the cores 15 with a conductive electrode 16. When the semiconductor chip 3 is flip-chip mounted, the bump electrode 14 is plastically deformed and the table electrode 13 is elastically deformed appropriately, thereby obtaining a good conductive state.

Abstract: An integrated circuit package is described that includes an integrated circuit die, a plurality of lower contact leads, and an insulating substrate positioned over the die and lower contact leads. The insulating substrate includes a plurality of electrically conducting upper routing traces formed on the bottom surface of the substrate. The traces on the bottom surface of the substrate electrically couple each lower contact lead with an associated I/O pad.

Abstract: There is provided a low-cost semiconductor device that commercial and quality-assured (inspected) chip size packages can be stacked and has a small co-planarity value and a high mounting reliability. A semiconductor device in which a flexible circuit substrate is adhered to at least a part of a lateral side of a semiconductor package, and the flexible circuit substrate, which is on a side facing solder balls of the semiconductor package, is folded at a region inside of an edge of the semiconductor package.

Abstract: A housing for a semiconductor component, in which the housing has a plurality of pins which are provided at the edge of the housing at distances, the pins each having a width, a thickness and a length. In order to create a housing for a semiconductor component whose characteristic frequencies are outside a range in which the characteristic frequencies of the housing negatively influence the semiconductor component, either at least one of the distances lies outside the range of 1.24 mm to 1.30 mm, at least one of the widths lies outside the range of 0.33 mm to 0.51 mm, at least one of the thicknesses lies outside the range of 0.23 to 0.32 mm, or at least one of the lengths lies outside the range of 2.05 to 4.12 mm.

Abstract: A method of securing a bond pad in to a semiconductor chip having an upper top metal surface which includes one or more holes, the method comprising the steps of forming a passivation layer over the upper metal surface, which passivation layer has holes therein substantially corresponding to the or each hole in the upper metal layer and being substantially the same size or smaller than the holes in the upper metal layer; forming the bond pad over the passivation layer; characterised in that the step of forming the bond pad comprises introducing some of the material from the bond pad into the holes in the passivation layer and upper metal layer when forming the bond pad, securing the bond pad to the passivation layer by allowing said material to flow under the surface thereof and attach thereto without attaching to the upper metal layer to thereby form a securing means.

Abstract: A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.

Abstract: Some embodiments provide surface mount devices that include a first electrode comprising a chip carrier part, a second electrode disposed proximate to the chip carrier part, and a casing encasing a portion of the first and second electrodes. The first electrode can extend from the chip carrier part toward a perimeter of the casing, and the second electrode can extend away from the chip carrier part and projects outside of the casing. In extending away from the chip carrier part the first electrode divides into a plurality of leads separated by an aperture that join into a single first joined lead portion with a first width before projecting outside of the casing and maintains the first width outside of the casing. The second electrode can attain a second width prior to projecting outside of the casing and maintains the second width outside the casing.

Abstract: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.

Abstract: To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.

Abstract: A method for manufacturing a substrate for a semiconductor package includes the steps of attaching first and second insulation layers which have first surfaces and second surfaces and are formed with conductive layers on the first surfaces, by the medium of a release film which has adhesives attached to both surfaces thereof, such that the second surfaces of the first and second insulation layers face each other; forming first conductive patterns on the first surfaces of the first and second insulation layers by patterning the conductive layers; forming solder masks on the first surfaces of the first and second insulation layers including the first conductive patterns to open portions of the first conductive patterns; and separating the first and second insulation layers from each other by removing the release film.

Abstract: A flip-chip package includes a package carrier; a semiconductor die having a die face and a die edge, the semiconductor die being assembled face-down to a chip side of the package carrier, and contact pads are situated on the die face; a rewiring laminate structure between the semiconductor die and the package carrier, the rewiring laminate structure including a re-routed metal layer, and at least a portion of the re-routed metal layer projects beyond the die edge; and bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier.

Abstract: A semiconductor device includes an insulating substrate; at least one semiconductor element mounted on a first principal surface of the insulating substrate; and a heat radiator joined through a solder member to a second principal surface of the insulating substrate opposite to the first principal surface on which the semiconductor element is mounted. The solder member contains at least tin and antimony, and the antimony content of the solder member is in a range of from 7% by weight to 15% by weight, both inclusively. Thus, reliability of the semiconductor device is improved.

Abstract: A semiconductor element includes: a substrate having an integrated circuit; and a wire connection electrode and a bump connection electrode which are provided on a same main surface of the substrate as electrodes having a same connection function to the integrated circuit. The wire connection electrode is provided in a periphery of the main surface. The bump connection electrode is provided inside the wire connection electrode on the main surface. When a straight line dividing the main surface into two regions is determined, the wire connection electrode and the bump connection electrode are located opposite to each other with respect to the straight line.

Abstract: A semiconductor package including a substrate with a semiconductor device mounted on the substrate and a resin member sealing the substrate and semiconductor device. The resin member includes a first surface and a second surface located on the other side of the first surface and a plurality of leads electrically connected with the semiconductor device. The leads project from the resin member and extend to the second surface side; wherein the second surface of the resin member includes a first area having a first concave portion and a second area having a second concave portion which is different from the first area, and the second concave portion is deeper than the first concave portion.

Abstract: A method of manufacture of an integrated circuit package system including: providing a selective slot die paddle having selective slots and edge pieces around the perimeter; providing extended leads protruding into the selective slots; mounting an integrated circuit die on the selective slot die paddle; and coupling bond wires between the integrated circuit die, the edge pieces, the extended leads, or a combination thereof.

Abstract: Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.

Abstract: The invention relates to a liquid resin composition for electronic components which is used in sealing of electronic components, comprising a liquid epoxy resin, a curing agent containing a liquid aromatic amine, and an inorganic filler, and further comprising at least one member selected from a hardening accelerator, silicone polymer particles, and a nonionic surfactant. There is thereby provided a liquid resin composition for electronic components, which is excellent in fluidity in narrow gaps, is free of void generation, is excellent in adhesiveness and low-stress characteristic and is excellent in fillet formation, as well as an electronic component device having high reliability (moisture resistance, thermal shock resistance), which is sealed therewith.

Abstract: Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Abstract: A semiconductor device. In one embodiment the device includes a carrier. A first material is deposited on the carrier. The first material has an elastic modulus of less than 100 MPa. A semiconductor chip is placed over the first material. A second material is deposited on the semiconductor chip, the second material being electrically insulating. A metal layer is placed over the second material.

Abstract: A vertical transmission structure for high frequency transmission lines includes a conductive axial core and a conductive structure surrounding the conductive axial core. The vertical transmission structure is applied to a high-frequency flip chip package for reducing the possibility of underfill from coming in contact with the conductive axial core.

Abstract: A semiconductor device including a semiconductor chip having a plurality of electrodes on one surface thereof in a thickness direction, a resin layer overlapping the one chip surface to provide a rectangular mounting surface, a plurality of metal posts in the resin layer, where the metal posts are electrically connected to the electrodes, and solder terminals respectively connected to the metal posts. The resin layer has a groove formed therein at the mounting surface so as to surround an area on which the metal posts are provided. The semiconductor device is mounted on the mounting substrate with an underfill material filled in a space between the mounting surface and the mounting substrate.

Abstract: An RF power transistor package with a rectangular ceramic base can house one or more dies affixed to an upper surface of the ceramic base. Source leads attached to the ceramic base extend from at least opposite sides of the rectangular base beneath a periphery of a non-conductive cover overlying the ceramic base. The cover includes recesses arranged to receive the one or more die, the ceramic base, gate and drain leads and a portion of the source leads. The cover further includes bolt holes arranged to clamp the ceramic base and source leads to a heat sink. Bosses at corners of the cover outward of the bolt holes exert a downward bowing force along the periphery of the cover between the bolt holes.

Abstract: A solder resist and a central pad to which a central Au bump provided on a semiconductor chip is flip-chip bonded are formed on a substrate main body. In a flip-chip mounting substrate where an underfill resin is provided after the semiconductor chip is mounted, a central opening portion for exposing the central pad is formed in the solder resist, and also, an edge portion forming the central opening portion of the solder resist is partially overlapped with the outer peripheral portion of the central pad.

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths of 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is used to fabricate the interconnection circuits. A polymer base layer is formed on a glass carrier with an intermediate release layer. Alternate layers of metal and dielectric are formed on the base layer, and patterned to create an array of multi-layer interconnection circuits on the glass panel. A thick layer of polymer is deposited on the interconnection circuit, and openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings to form wells filled with solder.

Abstract: A mounting structure comprises: at least one semiconductor device having solder bumps as outer terminals and a flexible wiring board with wiring formed thereon. The semiconductor device is structured to be wrapped by the flexible wiring board, the mounting structure is provided with outer electrodes on both sides of the flexible wiring board, one side being a side where outer terminals of the semiconductor device are formed, and the other side being an opposite side thereof. At least one wiring layer is formed on the flexible wiring board. A supporting member is provided covering side faces and a surface of the semiconductor device opposite to the side where the outer terminals are formed and protruding from the side faces of the semiconductor device and extending toward the surface on which the outer terminals are formed.

Abstract: An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region.

Abstract: A semiconductor package that includes a substrate having first and second major surfaces is presented. The package includes a plurality of landing pads and a semiconductor die disposed on the first major surface. A molded cap is disposed on the first surface to encapsulate the die and substrate. The landing pads are covered when the cap is molded. Package interconnects are coupled to the landing pads. The package interconnects are exposed by the cap to facilitate package stacking.

Abstract: A mounted body of the present invention includes: a multilayer semiconductor chip 20 including a plurality of semiconductor chips 10 (10a, 10b) that are stacked; and a mounting board 13 on which the multilayer semiconductor chip 20 is mounted. In this mounted body, each of the semiconductor chips 10 (10a, 10b) in the multilayer semiconductor chip 20 has a plurality of element electrodes 12 (12a, 12b) on a chip surface 21 (21a, 21b) facing toward the mounting board 13. On the mounting board 13, electrode terminals 14 are formed so as to correspond to the plurality of element electrodes (12a, 12b), respectively, and the electrode terminals 14 of the mounting board and the element electrodes (12a, 12b) are connected electrically to each other via solder bump formed as a result of assembly of solder particles. With this configuration, a mounted body on which a stacked package is mounted can be manufactured easily.

Abstract: A flip chip interconnect is made by mating the interconnect bump directly onto a lead, rather than onto a capture pad. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having electrically conductive traces in a die attach surface, in which the bumps are mated directly onto the traces. In some embodiments the interconnection is formed without employing a solder mask. In some methods a curable adhesive is dispensed either onto the bumps on the die or onto the traces on the substrate; the adhesive is partly cured during the mating process, and the partly cured adhesive serves to confine the molten solder during a reflow process.

Abstract: The present invention provides a semiconductor device capable of eliminating voltage (IR) drop of a semiconductor die inside the semiconductor device and a fabricating method of the semiconductor device. The semiconductor device comprises the semiconductor die, and the semiconductor die comprises a first surface area, a plurality of first pads potentially equivalent to each other, a passivation layer, a plurality of first openings, and a first conducting medium layer. The passivation layer is disposed on the plurality of first pads. The plurality of first openings is formed on the passivation layer, and utilized for exposing the plurality of first pads. The first conducting medium layer is formed on the first surface area, and utilized for fulfilling the plurality of first openings to connect the plurality of first pads.