Abstract: An SCR device includes a substrate, a plurality of isolation structures defining a first region and a second region in the substrate, an n well disposed in the substrate, an n type first doped region disposed in the first region in the substrate, a p type second doped region disposed in the second region in the substrate, and a p type third doped region (PESD implant region) disposed underneath the first doped region in the first region in the substrate. The well is disposed underneath the first region and the second region, and the third doped region isolates the first doped region from the well.

Abstract: This publication discloses a method for forming electrically conducting structures on a substrate. According to the method nanoparticles containing conducting or semiconducting material are applied on the substrate in a dense formation and a voltage is applied over the nanoparticles so as to at least locally increase the conductivity of the formation. According to the invention, the voltage is high enough to cause melting of the nanoparticles in a breakthrough-like manner. With the aid of the invention, small-linewidth structures can be created without high-precision lithography.

Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.

Abstract: According to one embodiment of the present invention, an integrated circuit is provided which includes a plurality of resistivity changing cells. At least two resistance ranges are assigned to each resistivity changing cell, each resistance range defining a possible state of the resistivity changing cell. The integrated circuit is operable in a cell initializing mode in which initializing signals are applied to the resistivity changing cells. The strengths and durations of the initializing signals are chosen such that the resistance of each resistivity changing cell is shifted into one of the resistance ranges assigned to the resistivity changing cell.

Abstract: A method comprises forming a gate stack comprising a polysilicon layer, a metal layer and a polysilicon layer over a gate dielectric and substrate. The metal layer is buried inside the gate stack to alloy the silicon and metal at the bottom of the gate. The gate stack is then etched to form a gate. A silicidation is then performed to form a silicide at the bottom of the gate. Optionally, a second metal layer may be formed on top of the gate stack. As such, during silicidation, a silicide may be formed at the top of the gate.

Abstract: A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

Abstract: It is an object of the present invention to provide a high-performance and high reliable semiconductor device and to provide a technique of manufacturing the semiconductor device at low cost with high yield. The semiconductor device is manufactured by steps of forming a first conductive layer, forming a first liquid-repellent layer over the first conductive layer, discharging a composition containing a material for a mask layer over the first liquid-repellent layer to form a mask layer, processing the first liquid-repellent layer with the use of the mask layer, forming a second liquid-repellent layer, forming an insulating layer over the first conductive layer and the second conductive layer, and forming a second conductive layer over the insulating layer.

Abstract: In a method for manufacturing a semiconductor component having a semiconductor substrate, a flat, porous diaphragm layer and a cavity underneath the porous diaphragm layer are produced to form unsupported structures for a component. In a first approach, the semiconductor substrate may receive a doping in the diaphragm region that is different from that of the cavity. This permits different pore sizes and/or porosities to be produced, which is used in producing the cavity for improved etching gas transport. Also, mesopores may be produced in the diaphragm region and nanopores may be produced as an auxiliary structure in what is to become the cavity region.

Abstract: A semiconductor laser diode comprises a p-n junction. The p-n junction comprises a substrate, an n-type semiconductor layer, a p-type semiconductor layer, and a quantum well. The quantum well is disposed between the n-type semiconductor layer and the p-type semiconductor layer. The substrate is formed from a first material system, the n-type semiconductor layer is formed from a second material system, the p-type semiconductor layer is formed from a third material system, and the quantum well is formed from a fourth material system. The second material system is different from the third material system. The second material system and the third material system are selected such that there is an increase in the rate of recombinations of the electrons from the n-type semiconductor layer and the holes from the p-type semiconductor layer in the quantum well. This results in a lower turn-on voltage for the semiconductor laser diode.

Abstract: The present invention relates to a heat-resistant dicing tape or sheet, which includes a substrate having a glass transition temperature of 70° C. or higher; and at least one pressure-sensitive adhesive layer disposed on at least one side of the substrate, the pressure-sensitive adhesive layer having a degree of weight loss upon heating of less than 2% when the pressure-sensitive adhesive layer is heated from room temperature to 200° C. at a rate of temperature increase of 2° C./min, in which the pressure-sensitive adhesive layer has an adhesive force (peel rate: 300 mm/min; peel angle: 180°) of 0.5 N/20 mm or lower when the heat-resistant dicing tape or sheet is applied to a silicon mirror wafer, is subsequently heated at 200° C. for 30 seconds, and is then cooled to 23° C.

Abstract: A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of MOSFET diode-connected transistors. In addition, a method for manufacturing the bulk isolated PN diodes is recited.

Abstract: The present invention is related to the localised/patterned deposition and/or desorption of (bio)molecules using microelectronic structures. Often pre-existing structures needed for proper functioning of the device (e.g. sensors, . . . ) can be used as individually addressable control structures to achieve localised deposition through thermal and/or electrochemical spotting, thereby reducing the need for and simplifying additional processing steps to achieve localised/patterned deposition. If these multi-purpose structures are not available, additional control structures can be implemented, using microelectronic VLSI production technology.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen content of less than 1%.

Abstract: A method and device for alternately contacting two wafer-like component composite arrangements (12, 14) consisting of a plurality of cohesively designed similar components, in particular of a semiconductor wafer with a function component wafer for manufacturing electronic modules on a wafer level, in which the two component composite arrangements, each provided with contact metallizations on their opposing contact surfaces (38, 39), are brought into a coverage position with their contact metallizations to form contact pairs, in which position the contact metallizations that are to be joined together are pressed against one another, the contact metallizations being thereby contacted by exposing the rear of one of the component composite arrangements (12) to laser radiation (20), the wavelength of the laser radiation being selected as a function of the degree of absorption of the component composite arrangement exposed to laser radiation at the rear, so that a transmission of the laser radiation through the com

Abstract: It is an object of the present invention to provide a semiconductor display device using a protective circuit in which dielectric breakdown is prevented more effectively. In the invention, in the cases that a first interlayer insulating film is formed covering a TFT used for a protective circuit and a second interlayer insulating film, which is an insulating coating film, is formed covering a wiring formed over the first interlayer insulating film, a wiring for connecting the TFT to other semiconductor elements is formed so as to be in contact with the surface of the second interlayer insulating film so as to secure a path discharging charge accumulated in the surface of the second interlayer insulating film. Note that the TFT used for the protective diode is a so-called diode-connected TFT in which either of the first terminal or the second terminal is connected to a gate electrode.