Abstract: Preferred embodiments of the invention provide semiconducting microcavity plasma devices. Preferred embodiments of the invention are microcavity plasma devices having at least two pn junctions, separated by a microcavity or microchannel and powered by alternate half-cycles of a time-varying voltage waveform. Alternate embodiments have a single pn junction. Microplasma is produced throughout the cavity between single or multiple pn junctions and a dielectric layer isolates the microplasma from the single or multiple pn junctions. Additional preferred embodiments are devices in which the spatial extent of the plasma itself or the n or p regions associated with a pn junction are altered by a third (control) electrode.

Abstract: An apparatus includes a substrate, a Group III-nitride layer over the substrate, and an electrical contact over the Group III-nitride layer. The electrical contact includes a stack having multiple layers of conductive material, and at least one of the layers in the stack includes germanium. The layers in the stack may include a contact layer, where the contact layer includes aluminum copper. The stack could include a titanium or titanium alloy layer, an aluminum or aluminum alloy layer, and a germanium or germanium alloy layer. At least one of the layers in the stack could include an aluminum or titanium alloy having a germanium content between about 1% and about 5%.

Abstract: A method includes forming a stress compensating stack over a substrate, where the stress compensating stack has compressive stress on the substrate. The method also includes forming one or more Group III-nitride islands over the substrate, where the one or more Group III-nitride islands have tensile stress on the substrate. The method further includes at least partially counteracting the tensile stress from the one or more Group III-nitride islands using the compressive stress from the stress compensating stack. Forming the stress compensating stack could include forming one or more oxide layers and one or more nitride layers over the substrate. The one or more oxide layers can have compressive stress, the one or more nitride layers can have tensile stress, and the oxide and nitride layers could collectively have compressive stress. Thicknesses of the oxide and nitride layers can be selected to provide the desired amount of stress compensation.

Abstract: The disclosure relates to a fabrication process of a biosensor on a semiconductor wafer, comprising steps of: making a central photosensitive zone comprising at least one pixel-type biological analysis device comprising a photosensitive layer, and a first peripheral zone surrounding the central photosensitive zone, comprising electronic circuits. The first peripheral zone is covered by a hydrophilic coating, and the central photosensitive zone is covered with a hydrophobic coating. A barrier of a bio-compatible resin is formed on the second peripheral zone.

Abstract: A micro structure for sensing a substance using light scattering includes a substrate, a first layer on the substrate, wherein the first layer comprises a metallic material, a second layer over the first layer, and a mask layer over the second layer. A plurality of nano holes are formed through the mask layer and the second layer, wherein the plurality of holes are defined in part by internal surfaces on the second layer and the mask layer. Two or more structure layers are formed on the mask layer and the internal surfaces in the plurality of holes. The two or more structure layers comprise different material compositions.

Abstract: A semiconductor chip is disposed on a first surface of a mounting board with its active surface upward. An inductor is provided at the active surface side, that is, at the surface side of the semiconductor chip not facing the mounting board in order to perform communication between the semiconductor chip and the outside. A sealing resin layer is formed on the first surface of the mounting board in order to seal the semiconductor chip. In addition, a recess or an opening (in the present embodiment, a recess) is provided in the sealing resin layer. The recess includes the inductor thereinside when seen in a plan view.

Abstract: A device for the detection of a peroxide-based explosive, in particular, triacetone triperoxide (TATP), which is based on a molecular controlled semiconductor resistor (MOCSER) and composed of at least one insulating or semi-insulating layer, at least one conducting semiconductor layer, two conducting pads and a layer of multifunctional organic molecules capable of adsorbing molecules of said peroxide-based explosive. Further is provided an array of semiconductor devices for the selective detection of a peroxide-based explosive, as well as a method for the selective detection of vapors of a peroxide-based explosive in a gaseous mixture using said array. The multifunctional organic molecules are from the group of cyclodextrins, thiols or alkylphosphonates with RPO(OH) 2 wherein R is an aliphatic hydrocarbyl with C6-C22.

Abstract: A sensor is provided for sensing a value of a physical parameter characteristic of the sensor's environment. The sensor is implemented in semiconductor technology. A behavior of the sensor's electronic circuitry is affected by stress. The stress is induced by a film covering the circuitry or only part thereof. The stress is caused by the film's material, whose dimensions depend on a value of the parameter. This dependence is different from the 5 dependence of the circuitry's substrate on the same parameter.

Abstract: A biosensor device is provided, including a first semiconductor layer formed over an interconnect structure. A plurality of detection elements are formed in the first semiconductor layer. An optical filter layer is formed over and physically contacts the first semiconductor layer. A second semiconductor layer is formed over the optical filter layer, having opposing first and second surfaces, wherein the first surface physically contacts the optical filter layer. A plurality of isolation walls are formed over the second semiconductor layer from the second surface thereof, defining a plurality of micro-wells over the second semiconductor layer, wherein the isolation walls and the second semiconductor layer comprises the same material, and the micro-wells are correspondingly arranged with the detection elements. An immobilization layer is formed over the second semiconductor layer exposed by the micro-wells and a plurality of capture molecules are formed over the immobilization layer in the mirco-wells.

Abstract: A smartcard or other media that detects the presence of chemical and/or biological compounds or other items of interest on individuals handling by using chemical-selective devices. These chemical-selective devices can include non-linear (e.g., diode and/or transistor) and/or time non-linear (e.g., controlled resistor) electrical components and can indicate exposure to an item of interest through a change in one or more electrical characteristics. The exposure of the chemical-selective devices to items of interest is stored such that, when the smartcard or other media is presented to a card reader, the detection data can be transmitted to the card reader for appropriate processing by the system.

Abstract: Semiconductor devices having atomic lattice matching template interlayers are provided. In one aspect, a semiconductor device can include a first semiconductor material, a second semiconductor material disposed on the first semiconductor material, and an atomic template interlayer disposed between the first semiconductor material and the second semiconductor material, the atomic template interlayer bonding together and facilitating a substantial lattice matching between the first semiconductor material and the second semiconductor material.

Abstract: A nitride-based semiconductor light-emitting device 100 includes: a GaN substrate 10 with an m-plane surface 12; a semiconductor multilayer structure 20 provided on the m-plane surface 12 of the GaN substrate 10; and an electrode 30 provided on the semiconductor multilayer structure 20. The electrode 30 includes a Zn layer 32 and a metal layer 34 provided on the Zn layer 32. The Zn layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.

Abstract: A method for preparation of carbon nanotubes (CNTs) bundles for use in field emission devices (FEDs) includes forming a plurality of carbon nanotubes on a substrate, contacting the carbon nanotubes with a polymer composition comprising a polymer and a solvent, and removing at least a portion of the solvent so as to form a solid composition from the carbon nanotubes and the polymer to form a carbon nanotube bundle having a base with a periphery, and an elevated central region where, along the periphery of the base, the carbon nanotubes slope toward the central region.

Abstract: A semiconductor device and method of manufacturing the device is disclosed. In one aspect, the device includes a semiconductor substrate and a GaN-type layer stack on top of the semiconductor substrate. The GaN-type layer stack has at least one buffer layer, a first active layer and a second active layer. Active device regions are definable at an interface of the first and second active layer. The semiconductor substrate is present on an insulating layer and is patterned to define trenches according to a predefined pattern, which includes at least one trench underlying the active device region. The trenches extend from the insulating layer into at least one buffer layer of the GaN-type layer stack and are overgrown within the at least one buffer layer, so as to obtain that the first and the second active layer are continuous at least within the active device regions.

Abstract: An arrangement method of a semiconductor device including external connection terminals and inductors, the terminals being arranged at a predetermined pitch in a lattice pattern is provided. The method includes determining the arrangement of the terminals, determining a maximum width of air-core portions of the inductors, drawing first virtual lines passing a central position between two adjacent ones of the terminals in a first direction, drawing second virtual lines passing a central position between two adjacent ones of the terminals in a direction orthogonal to the first direction, determining a permissible range of distances between the first and second virtual lines nearest to each inductor and the inductor center, and arranging the inductors such that at least one of a distance between the nearest first virtual line and the inductor center and a distance between the nearest second virtual line and the inductor center falls within the permissible range.

Abstract: This invention relates to a junction device, especially a p-n junction device. This invention also relates to a backward current decoupler which is also a good sensor. An induced backward current by forward current input can be decoupled by the backward current decoupler. The new p-n junction device has built-in damper and better capacitive property so that less power is consumed. The new sensor can be interactable with thermal, magnetic, optical, force or electrical fields.

Abstract: Electric generator also can generate from silicon magnetic and quartz material by attract and repulsion polarity of silicon magnetic north and south apply force compress and decompress on quartz material to create electric signal. The other useful of silicon magnetic can keep holes charge at bay to create more free flow of electrons that help silicon switching faster and low heat.

Abstract: Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.

Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

Abstract: Monolithic IC/MEMS processes are disclosed in which high-stress silicon nitride is used as a mechanical material while amorphous silicon serves as a sacrificial layer. Electronic circuits and micro-electromechanical devices are built on separate areas of a single wafer. The sequence of IC and MEMS process steps is designed to prevent alteration of partially completed circuits and devices by subsequent high process temperatures.

Abstract: Methods and apparatuses for matching impedances in a flip-chip circuit assembly are presented. An apparatus for matching impedances in a flip-chip circuit assembly may include a first circuit associated with a first die and a through silicon via (TSV) coupling the first circuit to a second circuit. The apparatus may further include a first impedance matching inductor interposed between the TSV and the second circuit. A method for matching impedances in a flip-chip circuit assembly may include providing a die having a first circuit, and forming a TSV over the die. The method may further include providing a second circuit and forming a first impedance matching inductor interposed between the TSV and second circuit.

Abstract: There is provided a semiconductor device including a capacitorless RAM. The semiconductor device includes a field effect transistor (FET) having a floating body structure. FET includes a channel body region arranged in a first region comprising a first semiconductor (e.g., p-SiGe) having a given band gap and a second region comprising a second semiconductor (e.g., n-Si) having a larger band gap than the first semiconductor.

Abstract: A semiconductor circuit includes a first pad for a first power source, a second pad for a second power source, a third pad for an input/output signal, a protection element arranged between the first pad and the third pad, and a transistor functioning as a trigger element for use in passing a trigger current through the protection element. The transistor includes source connected to the third pad, a gate and a backgate commonly connected to the second pad.

Abstract: Electron microscope support structures and methods of making and using same. The support structures are generally constructed using semiconductor materials and semiconductor manufacturing processes. The temperature of the support structure may be controlled and/or gases or liquids may be confined in the observation region for reactions and/or imaging.

Abstract: A semiconductor device including: a substrate, which has a composition represented by the formula: Ala?Ga1-a?N, wherein a? satisfies 0<a??1; an active layer, which is formed on the substrate, and which has a composition represented by the formula: Alm?Ga1-m?N, wherein m? satisfies 0?m?<1; a buffer layer disposed between the active layer and the substrate; and a first main electrode and a second main electrode, which are formed on the active layer, and which are separated from each other, wherein the semiconductor device is operated by electric current flowing between the first main electrode and the second main electrode in the active layer, and wherein the buffer layer has a composition represented by the formula: AlbIn1-bN, wherein a composition ratio b satisfies 0<b<1, wherein the composition ratio b satisfies m?<b<a?.

Abstract: A method of forming a microelectronic device includes forming a groove structure having opposing sidewalls and a surface therebetween on a substrate to define a nano line arrangement region. The nano line arrangement region has a predetermined width and a predetermined length greater than the width. At least one nano line is formed in the nano line arrangement region extending substantially along the length thereof and coupled to the surface of the groove structure to define a nano line structure. Related devices are also discussed.

Abstract: Through substrate features in semiconductor substrates are described. In one embodiment, the semiconductor device includes a through substrate via disposed in a first region of a semiconductor substrate. A through substrate conductor coil is disposed in a second region of the semiconductor substrate.

Abstract: The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the formation of a “super-flat” interface between the two levels formed by the patterning of a full complement of active and dummy interconnecting vias using two separate patterning and etch processes. The active vias connect memory devices in the upper device level to connecting pads in the lower CMOS level. The dummy vias may extend up to an etch stop layer formed over the CMOS layer or may be stopped at an intermediate etch stop layer formed within the device level. The dummy vias thereby contact memory devices but do not connect them to active elements in the CMOS level.

Abstract: A MEMS coupler and a method to form a MEMS structure having such a coupler are described. In an embodiment, a MEMS structure comprises a member and a substrate. A coupler extends through a portion of the member and connects the member with the substrate. The member is comprised of a first material and the coupler is comprised of a second material. In one embodiment, the first and second materials are substantially the same. In one embodiment, the second material is conductive and is different than the first material. In another embodiment, a method for fabricating a MEMS structure comprises first forming a member above a substrate. A coupler comprised of a conductive material is then formed to connect the member with the substrate.

Abstract: An SCR device includes a substrate, a plurality of isolation structures defining a first region and a second region in the substrate, an n well disposed in the substrate, an n type first doped region disposed in the first region in the substrate, a p type second doped region disposed in the second region in the substrate, and a p type third doped region (PESD implant region) disposed underneath the first doped region in the first region in the substrate. The well is disposed underneath the first region and the second region, and the third doped region isolates the first doped region from the well.

Abstract: A sensor array (100) for detecting particles, the sensor array (100) comprising a substrate (102) having a plurality of holes (104), a plurality of electronic sensor chips (106) each having a sensor active region (202) being sensitive to the presence of particles to be detected, and an electric contacting structure (110) adapted for electrically contacting the plurality of electronic sensor chips (106), wherein the plurality of electronic sensor chips (106) and/or the electric contacting structure (110) are connected to the substrate (102) in such a manner that the plurality of holes (104) in combination with the plurality of electronic sensor chips (106) and/or the electric contacting structure (110) form a plurality of wells with integrated particle sensors.

Abstract: To provide a semiconductor device capable of write operation to a selected magnetoresistive element without causing a malfunction of a non-selected magnetoresistive element and a manufacturing method of this semiconductor device. The semiconductor device includes a magnetic storage element having a magnetization free layer whose magnetization direction is made variable and formed over a lead interconnect and a digit line located below the magnetic storage element, extending in a first direction, and capable of changing the magnetization state of the magnetization free layer by the magnetic field generated. The digit line includes an interconnect body portion and a cladding layer covering therewith the bottom surface and the side surface of the interconnect body portion and opened upward. The cladding layer includes a sidewall portion covering therewith the side surface of the interconnect body portion and a bottom wall portion covering therewith the bottom surface of the interconnect body portion.

Abstract: A 3D nonvolatile memory device includes: a plurality of channel structures including a plurality of channel layers and interlayer dielectric layers, which are alternately stacked, and extended in a first direction; a plurality of word lines extended in a second direction at least substantially perpendicular to the first direction; a plurality of row select lines connected to the plurality of channel layers, respectively, and extended in the second direction; and a plurality of column select lines connected to the plurality of channel structures, respectively, and extended in the first direction.

Abstract: An embodiment relates a method comprising creating a reversible change in an electrical property by adsorption of a gas by a composition, wherein the composition comprises a noble metal-containing nanoparticle and a single walled carbon nanotube. Another embodiment relates to a method comprising forming a composition comprising a noble metal-containing nanoparticle and a single walled carbon nanotube and forming a device containing the said composition. Yet another method relates to a device comprising a composition comprising a noble metal-containing nanoparticle and a single walled carbon nanotube on a silicon wafer, wherein the composition exhibits a reversible change in an electrical property by adsorption of a gas by the composition.

Abstract: Disclosed herein is a manufacturing method of metal oxide nanostructure, including the steps of: (S1) supplying a precursor containing a first metal, a precursor containing a second metal and oxygen onto a substrate; (S2) forming an amorphous second metal oxide layer on the substrate; (S3) forming first nuclei containing the first metal as a main component and second nuclei containing the second metal as a main component on the substrate; (S4) converting the first nuclei into single crystalline seed layers spaced apart from each other and converting the second nuclei into amorphous layers surrounding the first nuclei; and (S5) selectively forming rods on the seed layers and then growing the rods.

Abstract: An integrated circuit structure includes a plurality of first doped regions disposed in a substrate in a matrix having odd columns and even columns each immediately adjacent to a corresponding one of the odd columns, a plurality of buried bit lines disposed in the substrate to electrically connect to the plurality of first doped regions of the same odd column in the matrix, and a plurality of surface bit lines disposed above an uppermost surface of the substrate, wherein each of the surface bit lines electrically connects to the first doped regions of the same even column in the matrix.

Abstract: Provided are a semiconductor Field-Effect Transistor (FET) sensor and a method of fabricating the same. The method includes providing a semiconductor substrate, forming a sensor structure having a fin-shaped structure on the semiconductor substrate, injecting ions for electrical ohmic contact into the sensor structure, and depositing a metal electrode on the sensor structure, immobilizing a sensing material to be specifically combined with a target material onto both sidewall surfaces of the fin-shaped structure, and forming a passage on the sensor structure such that the target material passes through the fin-shaped structure.

Abstract: A semiconductor arrangement including a load transistor and a sense transistor that are integrated in a semiconductor body. One embodiment provides a number of transistor cells integrated in the semiconductor body, each transistor cell including a first active transistor region. A number of first contact electrodes, each of the contact electrodes contacting the first active transistor regions through contact plugs. A second contact electrode contacts a first group of the first contact electrodes, but not contacting a second group of the first contact electrodes. The transistor cells being contacted by first contact electrodes of the first group form a load transistor, with the second electrode forming a load terminal of the load transistor. The transistor cells being contacted by first contact electrodes of the second group form a sense transistor.

Abstract: Systems, devices and automated methods for minimally invasive surgery. A device is fabricated of bio-compatible semiconductor elements, and can be assembled, delivered, navigated and implanted by automated methods, using Nuclear Magnetic Resonance (NMR) technology.

Abstract: In a microwave module with at least one semiconductor chip, which provides on its upper side a connecting-line structure formed in particular as a coplanar line, which is connected to at least one adjacent incoming and/or outgoing line structure formed on the upper side of the substrate, the chip is glued with its underside and all lateral surfaces, on which no high-frequency connecting lines lead to the chip, within a recess of a metal part with good thermal conduction.

Abstract: To increase total power in a betavoltaic device, it is desirable to have greater radioisotope material and/or semiconductor surface area, rather than greater radioisotope material volume. An example of this invention is a high power density betavoltaic battery. In one example of this invention, tritium is used as a fuel source. In other examples, radioisotopes, such as Nickel-63, Phosphorus-33 or promethium, may be used. The semiconductor used in this invention may include, but is not limited to, Si, GaAs, GaP, GaN, diamond, and SiC. For example (for purposes of illustration/example, only), tritium will be referenced as an exemplary fuel source, and SiC will be referenced as an exemplary semiconductor material. Other variations and examples are also discussed and given.

Abstract: Provided is a method for fabricating an image sensor device that includes providing a substrate having a front side and a back side; patterning a photoresist on the front side of the substrate to define an opening having a first width, the photoresist having a first thickness correlated to the first width; performing an implantation process through the opening using an implantation energy correlated to the first thickness thereby forming a first doped isolation feature; forming a light sensing feature adjacent to the first doped isolation feature, the light sensing feature having a second width; and thinning the substrate from the back side so that the substrate has a second thickness that does not exceed twice a depth of the first doped isolation feature. A pixel size is substantially equal to the first and second widths.

Abstract: Nanoelements such as single walled carbon nanotubes are assembled in three dimensions into a nanoscale template on a substrate by means of electrophoresis and dielectrophoresis at ambient temperature. The current-voltage relation indicates that strong substrate-nanotube interconnects carrying mA currents are established inside the template pores. The method is suitable for large-scale, rapid, three-dimensional assembly of 1,000,000 nanotubes per square centimeter area using mild conditions. Circuit interconnects made by the method can be used for nanoscale electronics applications.

Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.

Abstract: The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a manufacturing method of a highly-reliable semiconductor device, which is not destroyed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element substrate having a semiconductor element formed using a single crystal semiconductor region, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element substrate and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are fixed together.

Abstract: Terahertz emitting devices are disclosed. The terahertz emitting device comprises a wafer and a current source. The wafer includes silicon carbide and a dopant. In particular, the wafer may consist of 6H silicon carbide; a nitrogen dopant having a concentration of approximately 1018 cm?3; a boron dopant having a concentration of approximately 1016 cm?3; and an aluminum dopant having a concentration of approximately 1015 cm?3. The current source is electrically coupled to the wafer. The wafer emits radiation having a frequency between approximately 1 THz and 20 THz when driven by the current source.

Abstract: An electronics package has a wafer level chip scale package (WLCSP) die substrate containing electronic circuits. Through-silicon vias through the die substrate electrically connect the electronic circuits to the bottom surface of the die substrate. A package sensor is coupled to the die substrate for sensing an environmental parameter. A protective encapsulant layer covers the top surface of the die substrate. A sensor aperture over the package sensor provides access for the package sensor to the environmental parameter.

Abstract: A method of forming at least one electronic device on a substrate comprising creating a depository and an attached capillary; providing a liquid containing particles in the range 1 nanometer to 1 millimeter for deposit into the depository; the liquid flowing into the at least one capillary by capillary action; evaporating the liquid such that the particles form an agglomerate beginning at the end of the at least one capillary with a substantially uniform distribution of the particles within the agglomerate; whereby the agglomerate is used to form a part of the at least one electronic device. An microelectronic integrated circuit device comprising a substrate; a depository coupled to said substrate formed by at least one wall, a capillary channel coupled to said depository adapted to be filled with liquid comprising nanoparticles by capillary action, whereby as the liquid evaporates, an agglomerate forms in the capillary channel having a substantially uniform distribution of the particles.

Abstract: A method of manufacturing a miniature electromechanical system (MEMS) device includes the steps of forming a moving member on a first substrate such that a first sacrificial layer is disposed between the moving member and the substrate, encapsulating the moving member, including the first sacrificial layer, with a second sacrificial layer, coating the encapsulating second sacrificial layer with a first film formed of a material that establishes an hermetic seal with the substrate, and removing the first and second sacrificial layers.

Abstract: A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain.