Measurement Or Control Of Test Condition Patents (Class 324/750.01)
  • Patent number: 8643392
    Abstract: An IC socket is pneumatically actuated and has an integrated heat sink. Thermally conductive elements of the heat sink extend through an opening of a pneumatically actuated element shaped as a closed curve of finite width so that heat radiating from the thermally conductive elements may dissipate through a top opening of the IC socket. Downward force exerted by the pneumatically actuated element is transferred through a gimbaled multi-plate and spring arrangement to provide even pressure on the die and substrate of an IC device being held in place by the IC socket. A spring-loaded ground tab on the bottom of the IC socket simplifies grounding of the IC socket to avoid damaging the held IC device by static discharge.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: February 4, 2014
    Assignee: Incavo Otax, Inc.
    Inventor: Glenn Chan
  • Patent number: 8633708
    Abstract: A current calibration method and the associated control circuit are provided. The method includes: providing a predetermined voltage to the differential output for obtaining an accurate current passing through the panel resistor during a calibration procedure and, providing a driving current to the differential output according to the accurate current during a normal operation procedure.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: January 21, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventors: Chih-Tien Chang, Ju-Ming Chou
  • Publication number: 20140015554
    Abstract: An inspection apparatus includes an insulating substrate, a socket in which a body portion having a through-hole in a wall thereof is integrally formed with a connection portion secured to the insulating substrate, and a contact probe detachably secured to the socket.
    Type: Application
    Filed: March 4, 2013
    Publication date: January 16, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Akira OKADA, Hajime AKIYAMA, Kinya YAMASHITA
  • Publication number: 20140015555
    Abstract: A hardware-in-the-loop (HIL) electrical grid simulation system and method that combines a reactive divider with a variable frequency converter to better mimic and control expected and unexpected parameters in an electrical grid. The invention provides grid simulation in a manner to allow improved testing of variable power generators, such as wind turbines, and their operation once interconnected with an electrical grid in multiple countries. The system further comprises an improved variable fault reactance (reactive divider) capable of providing a variable fault reactance power output to control a voltage profile, therein creating an arbitrary recovery voltage. The system further comprises an improved isolation transformer designed to isolate zero-sequence current from either a primary or secondary winding in a transformer or pass the zero-sequence current from a primary to a secondary winding.
    Type: Application
    Filed: July 16, 2013
    Publication date: January 16, 2014
    Applicant: Clemson University
    Inventors: John Curtiss Fox, Edward Randolph Collins, JR., Nikolaos Rigas
  • Publication number: 20140009180
    Abstract: A touch testing system for a capacitive touch device and a method thereof are provided. The system includes a test fixture, at least one magnetization component, at least one magnetic induction component and a driving unit. The fixture is disposed on the touch device and has at least one chute on a position corresponding to the touching area. The magnetization component is disposed on the fixture and enabled by a driving signal to produce a magnetic force. The magnetic induction component is slidably disposed in the chute and inducts the magnetic force to slide along the chute, such that the sensing unit produces a touch testing information. The driving unit is coupled to the magnetization component and the sensing unit, provides the driving signal to enable the magnetization component and receives the touch testing information to feed back a testing result on the capacitive touch device accordingly.
    Type: Application
    Filed: February 26, 2013
    Publication date: January 9, 2014
    Applicant: HANNSTAR DISPLAY CORPORATION
    Inventors: Chien-Hsiang Huang, Hui-Ju Chen
  • Publication number: 20140009179
    Abstract: A testing device including a first connector, a control unit, a first detecting circuit and a memory controller is provided. The first connector is electrically connected to a first bus. The control unit generates a plurality of first control signals according to a first enable signal from the first connector. The first detecting circuit is electrically connected to a plurality of first transmission lines in the first bus, and sequentially conducts the first transmission lines to a ground according to the first control signals. The memory controller detects states of the signals transmitted by the first transmission lines and determines whether to generate a first abnormal indication signal according to a detecting result. The control unit controls a plurality of indication lights according to the first abnormal indication signal.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 9, 2014
    Applicant: WISTRON CORPORATION
    Inventors: Quan Li, Kuan-Han Chen, Yin-Ching Wu
  • Patent number: 8624613
    Abstract: A printed circuit board of a hard disk drive system includes a first component and a plurality of second components of the hard disk drive system. The first component is configured to transmit information to, and receive information from, a host device via a communication interface of the printed circuit board. The first component includes a first testing module operating as a master testing module. Each of the plurality of second components includes a respective second testing module operating as a slave testing module. The first component is connected to each of the plurality of second components and is configured to provide test configuration data to each of the respective second testing modules. The test configuration data corresponds to the information received from the host device, and the test configuration data enables each of the respective second testing modules to test operation of the plurality of second components.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: January 7, 2014
    Assignee: Marvell International Ltd.
    Inventors: Saeed Azimi, Son Hong Ho
  • Publication number: 20140002118
    Abstract: A device for avoiding spark discharge during high voltage testing of semiconductor components on semiconductor wafers, includes a pressure chamber provided for the semiconductor wafer in a sealed manner, and having a pressurized gas feed so that the interior thereof is subjected to overpressure and thus the sparking voltage for a spark discharge between contact faces is higher than the maximum test voltage to be applied. The pressure chamber is connected to a probe card including contact probes. The pressure chamber has a movable part, which is movable relative to the parts of the pressure chamber connected to the probe card. An air bearing in the gap between the pressure chamber and the semiconductor wafer holds the movable part of the pressure chamber in a sealed manner spaced from the surface of the semiconductor wafer. The movable part is pressed by a spring force towards the semiconductor wafer.
    Type: Application
    Filed: March 12, 2012
    Publication date: January 2, 2014
    Inventor: Rainer Gaggl
  • Publication number: 20140002117
    Abstract: A system for measuring soft starter current includes a current monitoring system including a controller and a current transfer device that includes a first thyristor and a first conductor coupled to the first thyristor and configured to convey a first current flowing through the first thyristor, wherein the first current comprises current flowing through the first thyristor when the first thyristor is in an off state. The system also comprises a first current sensor configured to sense the first current and a first current measurement circuit coupled to the first current sensor and coupleable to the controller and configured to output a first output value to the controller representative of the first current flowing through the first thyristor. The controller is configured to determine an impending inoperability of the first thyristor based on the first current and alert a user if the first current indicates the impending inoperability.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Inventor: Kaijam M. Woodley
  • Patent number: 8618812
    Abstract: An electrical interconnection integrated device is described, comprising: a plurality of electrical terminals connectable to an integrated electronic circuit on a chip common to said interconnection device; at least an inside electrical device provided with a respective input connected to a first terminal of said plurality and a respective output; a fault detecting logic module having a first input connected to said output of the inner electrical device and provided with a detecting terminal for supplying a fault detecting signal.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: December 31, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventor: Marco Casarsa
  • Publication number: 20130342228
    Abstract: Embodiments are directed to coupling a first transformer to a first load, coupling a second transformer to a second load, applying a single phase power source to the first transformer, applying an inverted version of the power source to the second transformer, coupling a sensing circuit to the first and second transformers, and monitoring, by the sensing circuit, signal contributions associated with the first and second transformers.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Applicant: HAMILTON SUNDSTRAND CORPORATION
    Inventor: Kenneth D. Milkie
  • Patent number: 8610446
    Abstract: A testing device includes a pressure vessel, a mounting stand disposed in an internal space of the pressure vessel, on which a device to be tested is mounted, test electrodes, disposed in the internal space of the pressure vessel, that supply a test voltage to the device to be tested mounted on the mounting stand, and a pressurization unit that raises the pressure of the internal space of the pressure vessel. The test voltage is supplied from the test electrodes to the device to be tested mounted on the mounting stand, and testing of the device to be tested is carried out, in a condition that the pressure of the internal space of the pressure vessel is raised by the pressurization unit.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: December 17, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Atsushi Yoshida, Hiroyuki Toya, Toru Nishizawa, Seizo Uchiyama
  • Patent number: 8610438
    Abstract: A branch circuit monitoring system (BCMS) for monitoring branch circuit currents in one or more electrical circuit panels is described. The system is comprised of a data center server, one or more panel processors, each with one or more collection devices, and one or more current sensors per collection device. The BCMS is designed to be installed entirely inside the panel without the need for a dedicated enclosure or power supply to facilitate ease of installation and low-cost. The BCMS also allows for future upgradability through standard software updates so that the system can be updated or patched easily. The BCMS data center server collects, aggregates, stores, and serves historical branch circuit current data from the panel processors to networked users via a web server to provide visualization of data such as tables, charts, and gauges.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: December 17, 2013
    Inventors: Montgomery J. Sykora, Daniel L. Janovy, David L. Janovy
  • Publication number: 20130328582
    Abstract: A test system for testing an antenna tuning element is provided. The test system may include a tester, a test fixture, and a probing structure. The probing structure may include probe tips configured to mate with corresponding solder bumps formed on a device under test (DUT) containing an antenna tuning element. The DUT may be tested in a shunt or series configuration. The tester may be electrically coupled to the test probe via first and second connectors on the test fixture. An adjustable load circuit that is coupled to the second connector may be configured in a selected state so that a desired amount of electrical stress may be presented to the DUT during testing. The tester may be used to obtain measurement results on the DUT. Systematic effects associated with the test structures may be de-embedded from the measured results to obtain calibrated results.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 12, 2013
    Inventors: Liang Han, Matthew A. Mow, Ming Tsai, Thomas E. Biedka, Robert W. Schlub, Ruben Caballero
  • Publication number: 20130328581
    Abstract: An apparatus and a method for automated testing of electrostatic discharge of a Device Under Test (DUT) are provided. In the apparatus and the method, an electrostatic pulse is applied to the DUT, a malfunction type is detected from the DUT, and a control command is transmitted to the DUT to return a test mode of the DUT to a normal mode according to the detected malfunction type.
    Type: Application
    Filed: January 9, 2013
    Publication date: December 12, 2013
    Applicant: SAMSUNG ELECTRONICS CO. LTD.
    Inventors: Han-Awl LEE, Jae-Kyu LEE, Woong-Hae CHOI, Byoung-Hee LEE
  • Patent number: 8604812
    Abstract: A voltage limiting test system used to test limit voltage values of a memory includes a voltage limiting test device and an assistant test device connected to the voltage limiting test device. The voltage limiting test device includes a button to adjust a voltage of the memory. The assistant test device includes a first timer, and first and second relays. The first relay is used to receive a state signal of the motherboard, to determine whether the first timer is powered according to the state signal. The second relay is used to receive the pulse signal output by the first timer when the first timer is powered, to trigger the button to adjust the voltage of the memory per a reference time. When the motherboard stops working, the voltage value of the memory is a limit voltage value of the memory.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: December 10, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Hung Chao, Jui-Hsiung Ho, Cheng-Chung Huang, Cheng-Hung Chiang, Chung-Hsun Wu
  • Publication number: 20130321010
    Abstract: Defects in a touch sensor are detected by coupling the sensor lines to a common signal line. Each of the sensor lines is tested by disconnecting the sensor line from the common signal line, connecting it to a voltage (e.g., ground) and comparing the voltage on the common signal line to a reference voltage. Detected defects include a short circuit between any two transmit and/or receive lines and a short between any transmit or receive line to ground.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 5, 2013
    Inventors: Daniel J. Cooley, Jeffrey L. Sonntag
  • Publication number: 20130321011
    Abstract: A test device, a test system, a method and a carrier for testing electronic components under variable pressure conditions comprise: a first chamber half and a second chamber half, a first gasket and a second gasket, a carrier segment adapted to carry a plurality of electronic components, and a circular carrier section surrounding the carrier segment. The circular carrier section comprises a first side and a second side. The first gasket is placed between the first chamber half and the first side of the circular carrier section to form an airtight seal and the second gasket is placed between the second chamber half and the second side of the circular carrier section to form an airtight seal.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 5, 2013
    Inventor: Stefan Binder
  • Patent number: 8598899
    Abstract: An overvoltage protection circuit connected to protect electrical components from overvoltage conditions includes a blocking diode connected in series with a transient voltage suppression device (TVS) via a first node and includes a reference voltage for biasing the first node at a voltage sufficient to reverse bias the blocking diode during normal operations. A built-in test circuit associated with the overvoltage protection circuit includes a resistor connected to the first node and a switch connected in series with the resistor that is selectively turned On and Off. The built-in test circuit monitors voltage on a control line associated with the electrical components and at the first node while the switch is Off and while the switch is On, and detects fault conditions based on the monitored voltages.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: December 3, 2013
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Gary L. Hess
  • Patent number: 8598496
    Abstract: The invention relates to a method for testing the operation of an electric heating element which is used for heating activated carbon of an activated carbon filter and/or air which is guided through the activated carbon for the regeneration thereof. The heating element has a PTC-characteristic (positive temperature coefficient characteristic). The strength of a current flow through the heating element in a heating phase selected for the operational testing is measured at a point in time or over a time period and is used for the operational testing, in that at least one measured current flow value is compared with a corresponding current flow value to be anticipated during defect-free operation of the heating element, and the heating element is considered to be defective in the event of a deviation which exceeds a predetermined measurement.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: December 3, 2013
    Assignee: A. Kayser Automotive Systems GmbH
    Inventors: Heiko Freter, Tobias Lang
  • Publication number: 20130314111
    Abstract: An apparatus for testing a thyristor valve includes: a current source circuit that provides an electric current when a thyristor valve as a test target is turned on; a voltage source circuit that provides a reverse voltage or a forward voltage when the thyristor valve is turned off; and a first auxiliary valve provided between a connection point between the thyristor valve and the voltage source circuit and the current source circuit, and that insulates the current source circuit from the voltage source circuit to protect the current source circuit from a high voltage of the voltage source circuit.
    Type: Application
    Filed: May 8, 2013
    Publication date: November 28, 2013
    Applicants: Myongji University Industry and Academia Cooperation Foundation, Lsis Co., Ltd.
    Inventors: Seung Taek BAEK, Byung Moon HAN, Eui Cheol NHO, Yong Ho CHUNG, Wook Hwa LEE
  • Publication number: 20130307571
    Abstract: A shutdown apparatus and method for use in conjunction with automatic test equipment (ATE) is provided. A unit under test (UUT) is inserted into an ATE receiver that couples the UUT to at least one electronic device during test and extracted from the ATE receiver after test. The shutdown apparatus comprises an electro-mechanical interface that inserts the UUT into the receiver prior to test and extracts the UUT from the receiver after test A shutdown module is coupled to the electronic device and to the electro-mechanical interface and connects the electronic device to the receiver after insertion of the UUT into the receiver and disconnects the electronic device from the receiver prior to extraction of the UUT from the receiver.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 21, 2013
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Kenny Nordstrom, Krishna Munirathnam, Santhoshkumar Ramasamy
  • Publication number: 20130307572
    Abstract: A battery simulation circuit simulates a rechargeable battery. The battery simulation circuit includes an integrated amplifier, a voltage adjustment unit, a current limitation unit, and a feedback unit. The voltage adjustment unit provides a reference voltage for the integrated amplifier; the current limitation unit provides a reference current for the integrated amplifier and the feedback unit provides a negative feedback signal for the integrated amplifier to control the integrated amplifier working in a linear state. The integrated amplifier outputs an output signal according to the reference voltage and the reference current; the battery simulation circuit supplies power for an electronic device. When the output terminal is connected to a DC power source and a voltage of the DC power source is greater than the output voltage of the output terminal, the battery simulation circuit simulates a battery being recharged by the DC power source via the output terminal.
    Type: Application
    Filed: May 15, 2013
    Publication date: November 21, 2013
    Applicants: Hon Hai Precision Industry Co., Ltd., Fu Tai Hua Industry (Shenzhen) Co., Ltd.
    Inventors: QI-LONG YU, TSUNG-JEN CHUANG, JUN ZHANG, SHIH-FANG WONG, JUN-WEI ZHANG, JIAN-JUN ZHOU
  • Publication number: 20130300442
    Abstract: The present document relates to chip sockets which for testing integrated circuit chips. A chip socket carries an integrated circuit chip comprising a plate for mounting onto a front side of a PCB, a plurality of electrical PCB connectors in a first area on a backside of the plate, wherein the plurality of electrical PCB connectors is adapted for electrically connecting the chip socket to a corresponding plurality of connectors on the PCB and a corresponding plurality of chip connectors on a front side of the plate, wherein the plurality of chip connectors is electrically connected to the plurality of electrical PCB connectors respectively; wherein the plurality of chip connectors connect the chip socket to a corresponding plurality of connectors of the integrated circuit chip, wherein the plate comprises a recess at its backside.
    Type: Application
    Filed: December 20, 2012
    Publication date: November 14, 2013
    Applicant: Dialog Semiconductor GmbH
    Inventors: Eric Marschalkowski, Karl Stadtmann
  • Publication number: 20130300443
    Abstract: The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.
    Type: Application
    Filed: July 15, 2013
    Publication date: November 14, 2013
    Inventor: Lee D. Whetsel
  • Publication number: 20130293248
    Abstract: A high-voltage discharge circuit diagnostic system includes a high voltage DC link with a positive DC link and a negative DC link, a first resistor selectably connectable between the positive DC link and the negative DC link, and a second resistor connected between the positive DC link and the negative DC link. A control module connects the first resistor between the positive DC link and the negative DC link until the high voltage DC link discharges to a first voltage after which the control module disconnects the first resistor from between the positive DC link and the negative DC link to permit continued discharge of the high voltage DC link through the second resistor to a second voltage through an elapsed time period. The control module diagnoses a fault in the second resistor based upon the first voltage, the second voltage, and the elapsed time period.
    Type: Application
    Filed: May 4, 2012
    Publication date: November 7, 2013
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Li-Pen J. Ho, David P. Tasky
  • Patent number: 8564317
    Abstract: A test socket is provided that includes a socket body to receive an object to be tested, a lid disposed on the socket body, one or more pushers coupled to a first surface of lid to apply force to a first surface of the object toward the socket body, and a temperature controlling member to provide a temperature to the object. A semiconductor package may be tested in a test apparatus that includes the test socket, the methods of testing including receiving a semiconductor package in a socket in a test chamber, applying a first temperature to the test chamber to test the semiconductor package at a first test temperature, and applying a second temperature to the semiconductor package to test the semiconductor package at a second test temperature by controlling the application of the second temperature with the socket.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: October 22, 2013
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Jong-Won Han, Seok Goh, Byoung-Jun Min, Jung-Hyeon Kim, Sang-Sik Lee, Bo-Woo Kim, Ho-Jeong Choi
  • Publication number: 20130271166
    Abstract: A system and method for monitoring or testing dielectric material nondestructively and in situ within field-based electrical equipment or as samples in a laboratory environment. In exemplary embodiments the use of negative voltage test pulses and a ground plane electrode with a parabolic curve or ogive shape minimizes energy transferred to the dielectric material to avoid or minimize degradation of the material. The disclosed system and method are thus suitable, inter alia, for continuous or near-continuous monitoring of fluid-filled electrical equipment in the field.
    Type: Application
    Filed: October 5, 2012
    Publication date: October 17, 2013
    Applicant: WICOR AMERICAS INC.
    Inventor: WICOR AMERICAS INC.
  • Publication number: 20130265066
    Abstract: A pixel array module with a self-test function including a test circuit unit, a plurality of test lines, and a pixel array is provided. The test circuit unit provides the self-test function. The test lines are connected between the test circuit unit and the pixel array. The pixel array is connected to the test circuit unit through the test lines and includes a plurality of pixels. Each pixel includes a transistor. Each transistor has a first terminal and a second terminal. Regarding each of the pixels, a driving signal of the transistor is transmitted from the first terminal to the second terminal thereof under a normal mode, and a test signal of the transistor is transmitted from the second terminal to the first terminal thereof under a test mode. Furthermore, a self-test method of the foregoing pixel array module is also provided.
    Type: Application
    Filed: July 1, 2012
    Publication date: October 10, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Cheng Hsieh, Shang-Fu Yeh, Ka-Yi Yeh
  • Publication number: 20130265067
    Abstract: The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.
    Type: Application
    Filed: March 13, 2013
    Publication date: October 10, 2013
    Inventor: Glenn J Leedy
  • Publication number: 20130257466
    Abstract: In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
    Type: Application
    Filed: May 23, 2013
    Publication date: October 3, 2013
    Inventors: Baker S. Mohammad, Hong S. Kim, Paul D. Bassett
  • Publication number: 20130249577
    Abstract: Methods and apparatus for performing an accelerated lifetime test on a photovoltaic device are provided. The method can include positioning a first photovoltaic device in a first holder adjacent to a light guide such that a transparent surface of the photovoltaic device faces the light guide, directing light emitted from a first light source into the light guide, and redirecting the light emitted from the first light source within the light guide to illuminate the transparent surface of the photovoltaic device.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 26, 2013
    Applicant: PrimeStar Solar, Inc.
    Inventors: Jeffrey Todd Knapp, Samuel Demtsu, Scott L. French
  • Publication number: 20130249576
    Abstract: A system for testing a PSU includes an input control module, a voltage regulating module, and a load adjusting module. The input control module includes a microcontroller and a plurality of key switches connected to the microcontroller. The microcontroller is configured to receive input instruction from the plurality of key switches and output a control signal according to the input instruction. The voltage regulating module is configured to receive the control signal and generate an output voltage with a voltage value associated with the control signal. The load adjusting module includes a motor coupled to the output voltage of the voltage regulating module. The motor is rotatable in opposite direction to adjust an output current of the PSU. A rotating speed of the motor is in direct proportion to the voltage value of the output voltage.
    Type: Application
    Filed: December 23, 2012
    Publication date: September 26, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (WUHAN) CO., LTD.
    Inventors: ZHI-YONG GAO, YU-LIN LIU
  • Patent number: 8543878
    Abstract: An apparatus to test a parametric structure utilizing a logical sensing technique is provided. The apparatus includes a device under test (DUT) and tester hardware. The DUT includes a parametric structure that receives a logic signal and transfers the logic signal through the parametric structure to a power pin that is coupled to the parametric structure. The DUT also includes a DFT circuitry that controls a pathway connecting the parametric structure and the power pin. The DFT circuitry gates the logic signal propagation from the parametric structure to the power pin. The tester hardware includes a channel to transfer or receive a logic signal and a power pathway to transfer power to the DUT. The tester hardware also includes a switch to multiplex the power pathway or the channel connections to the power pin.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: September 24, 2013
    Assignee: Altera Corporation
    Inventors: Eng Ling Ho, Chai Ling Chee
  • Publication number: 20130241585
    Abstract: There is provided an inverter test apparatus for testing an inverter interconnected with an alternating-current power system, the apparatus including an alternating-current power output unit configured to output alternating-current power, and an alternating-current power controller configured to control the alternating-current power output from the alternating-current power output unit to simulate an alternating-current load of the inverter.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 19, 2013
    Applicant: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATION
    Inventor: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATION
  • Publication number: 20130241584
    Abstract: A test apparatus for executing a power-on test of an electronic device includes a setting module, an activation module, a controller, and a USB connector. The setting module includes a plurality of input keys. The activation module activates a power supply-on pin of a motherboard of the electronic device. The controller is electronically connected to the input keys and the activation module, the controller drives the activation module to activate the power supply-on pin, and controls a number of times of activation of the power supply-on pin according to a predetermined number of power-on events. The USB connector electronically connects the controller to the electronic device, the USB connector receives power-on and power-off confirmation signals from the electronic device, and transmits the signals to the controller.
    Type: Application
    Filed: December 19, 2012
    Publication date: September 19, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventors: Ze-Jun MAO, Hong-Ru ZHU
  • Publication number: 20130241583
    Abstract: A device for testing short circuit protection functions of a plurality power supply units of a power supply includes a short circuit control module, a controller and an oscilloscope. The short circuit control module includes a number of driving circuits and a number of short circuits corresponding to the driving circuits. Each driving circuit is electrically connected to one of the power supply units by the corresponding short circuit. The controller is electrically connected to the driving circuits. The controller controls one or more of the driving circuits to drive the corresponding short circuits to short-circuit the corresponding power supply units. The oscilloscope is electrically connected to each power supply unit. The oscilloscope displays waveforms of output voltage of the short-circuit power supply units.
    Type: Application
    Filed: September 11, 2012
    Publication date: September 19, 2013
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: CHI-WEN CHEN
  • Publication number: 20130234741
    Abstract: A wireless electronic device may contain at least one antenna tuning element for use in tuning the operating frequency range of the device. The antenna tuning element may include radio-frequency switches, continuously/semi-continuously adjustable components such as tunable resistors, inductors, and capacitors, and other load circuits that provide desired impedance characteristics. A test station may be used to measure the radio-frequency characteristics associated with the tuning element. The test station may provide adjustable temperature, power, and impedance control to help emulate a true application environment for the tuning element without having to place the tuning element within an actual device during testing. The test system may include at least one signal generator and a tester for measuring harmonic distortion values and may include at least two signal generators and a tester for measuring intermodulation distortion values.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Inventors: Matthew A. Mow, Thomas E. Biedka, Liang Han, Rocco V. Dragone, JR., Hongfei Hu, Dean F. Darnell, Joshua G. Nickel, Robert W. Schlub, Mattia Pascolini, Ruben Caballero
  • Publication number: 20130234742
    Abstract: A integrated circuit having a receiver testing function includes a signal generating circuit, a jitter output circuit, a signal mix circuit, a receiver, and an error counting circuit. The signal generating circuit outputs a reference signal to the signal mix circuit and the error counting circuit. The jitter output circuit outputs a jitter. The signal mix circuit injects the jitter into the reference signal, and outputs a testing signal that is a combination of the jitter and the reference signal. The receiver receives and then outputs the testing signal to the error counting circuit. The error counting circuit tests a performance of the receiver by determining whether a difference between a code information of the testing signal and a code information of the reference signal is within a predetermined difference range.
    Type: Application
    Filed: December 19, 2012
    Publication date: September 12, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventor: FA-SHENG HUANG
  • Publication number: 20130229197
    Abstract: A main power supply is arranged such that its output terminal Po is connected to a power supply terminal of a DUT via a power supply line, and is configured to feedback control an output voltage VOUT output from the output terminal such that a detection value VDD? that corresponds to a power supply voltage VDD at the power supply terminal approaches a target value VREF?. When a test pattern is supplied to the DUT, a power supply control unit is configured to feedforward control the main power supply such that the power supply voltage VDD approaches a predetermined target waveform VTGT.
    Type: Application
    Filed: February 28, 2013
    Publication date: September 5, 2013
    Applicant: ADVANTEST CORPORATION
    Inventors: Takashi Kusaka, Masahiro Ishida
  • Publication number: 20130229198
    Abstract: Methodologies and test configurations are provided for testing thermal interface materials and, in particular, methodologies and test configurations are provided for testing thermal interface materials used for testing integrated circuits. A test methodology includes applying a thermal interface material on a device under test. The test methodology further includes monitoring the device under test with a plurality of temperature sensors. The test methodology further includes determining whether any of the plurality of temperature sensors increases above a steady state.
    Type: Application
    Filed: April 2, 2013
    Publication date: September 5, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dustin FREGEAU, David L. GARDELL, Laura L. KOSBAR, Keith C. STEVENS, Grant W. WAGNER
  • Publication number: 20130229196
    Abstract: A variable pressure probe pin device, including: a housing with a channel having a first longitudinal axis; a probe at least partially disposed in the channel and including a plurality of probe pins configured to measure a property of a conductive layer; and a fluid pressure system configured to supply pressurized fluid o the channel to control a position of the probe within the channel. The housing or the probe is displaceable such that the plurality of probe pins contact the conductive layer.
    Type: Application
    Filed: February 27, 2013
    Publication date: September 5, 2013
    Applicant: KLA-TENCOR CORPORATION
    Inventors: Walter H. Johnson, Nanchang Zhu
  • Patent number: 8527231
    Abstract: A test system that provides an output signal for analysis without requiring the test hardware to be idle during a settling interval. The test system includes a preprocessor that identifies the near-DC drift that occurs in the output signal and then adjusts the output signal to remove the near-DC drift. A set of values representing the near-DC drift at each of multiple times during the acquisition of a signal for analysis may be computed and used to model a settling profile of the signal by fitting a curve to the set of values. The model of the settling profile may then be subtracted from samples representing the output signal to provide an adjusted signal for further analysis.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: September 3, 2013
    Assignee: Teradyne, Inc.
    Inventor: Lawrence B. Luce
  • Publication number: 20130222000
    Abstract: An exemplary load circuit includes a switch unit and a current dividing circuit. The switch unit includes a number of switches. The current dividing circuit includes a number of sub-circuits. A terminal of a resistance module of each of the sub-circuits is connected to both a power terminal and a terminal of a corresponding one of the switches. The other terminal of the resistance module of each of the sub-circuits is connected to a drain of a transistor of each of the sub-circuits. A source of the transistor is connected to ground. A gate of the transistor is connected to ground, and is also connected to another terminal of the corresponding switch.
    Type: Application
    Filed: July 18, 2012
    Publication date: August 29, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD .
    Inventors: ZHEN-SEN LI, JIAN-SHE SHEN
  • Publication number: 20130221999
    Abstract: A testing method implemented by a testing system connected to an electronic device includes testing whether the electronic device is successfully powered on in a powering on/off test according to pre-set test parameters; detecting if the electronic device is successfully powered on in the powering on/off test; generating a pause signal when the electronic device is successfully powered on; upon receiving the pause signal, preventing from entering into testing powering off of the electronic device, controlling to test whether certain components in the electronic device can successfully perform some functions; generating a continue signal to test powering off of the electronic device after testing the certain components performing some functions; and testing whether the electronic device is successfully powered off in the powering on/off test. The testing system is also provided.
    Type: Application
    Filed: May 28, 2012
    Publication date: August 29, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventor: FANG TIAN
  • Publication number: 20130214807
    Abstract: An integrated circuit includes a register cell, a control unit and an oscillation detecting unit. The register cell stores a value of a signal input through an input pin. The control unit makes control such that the value of the signal input from the input pin is stored in the register cell, and the value stored in the register cell is output to an outside. The oscillation detecting unit receives a signal output from an oscillator through the input pin, and stores a predetermined value in the register cell when it is detected that the signal oscillates.
    Type: Application
    Filed: April 11, 2013
    Publication date: August 22, 2013
    Applicant: Fujitsu Limited
    Inventor: Fujitsu Limited
  • Publication number: 20130214805
    Abstract: A system for testing over-current fault detection includes a first switch to connect a voltage to a load, a capacitor connected between the first switch and ground, a monitor circuit that monitors a current from the first switch to the load, and a microcontroller configured to detect an over-current fault condition based upon input from the monitor circuit. The microcontroller controls the state of the first switch to connect voltage to the load and verifies over-current detection based upon current generated during charging of the capacitor.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 22, 2013
    Applicant: HAMILTON SUNDSTRAND CORPORATION
    Inventors: James Saloio, JR., An Nguyen
  • Publication number: 20130214806
    Abstract: A system for testing over-current fault detection includes a first switch to connect a voltage to a load and a capacitor; a first monitor circuit that monitors a current from the first switch to the load; a second monitor circuit that monitors a voltage across the capacitor; and a microcontroller configured to control a state of the first switch to connect voltage to the load and verifies over-current detection based upon current generated during charging of the capacitor. The microcontroller detects an over-current fault condition based upon input from the first monitor circuit and detects a short-circuit fault condition based upon input from the second monitor circuit during test of the first monitor circuit.
    Type: Application
    Filed: July 26, 2012
    Publication date: August 22, 2013
    Applicant: HAMILTON SUNDSTRAND CORPORATION
    Inventors: James Saloio, JR., James A. Gosse
  • Patent number: 8509036
    Abstract: A plurality of laser diode units is tested in a bar state, each of the laser diode units in which a laser diode that includes a first electrode and a second electrode formed on surfaces facing each other and that is mounted on a mounting surface of a submount such that the first electrode faces the mounting surface of the submount.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: August 13, 2013
    Assignees: TDK Corporation, Rohm Co., Ltd.
    Inventors: Koji Shimazawa, Kosuke Tanaka, Ryuji Fujii, Takashi Honda, Yoshiteru Nagai, Tsuguki Noma, Hosei Mitsuzawa
  • Patent number: 8508236
    Abstract: An electronic device, and associated method, provided with a circuit board (10), with a set of input contacts (IN/COM), a set of output contacts (OUT/COM) and an electrical circuit (18) connected between the input contacts (IN/COM) and the output contacts (OUT/COM) and a controller. The controller carries out a real-time test of the circuit board using a test signal introduced into the electrical circuit, the electrical circuit (18) being designed as a passive network having a characteristic transfer function and provided with at least two separate partial circuits (18?, 18?) wherein the separate partial circuits are electrically connected in the assembled state by cooperation with at least one of: at least one device components and/or assembly components (181).
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: August 13, 2013
    Assignee: Sartorius Weighing Technology GmbH
    Inventors: Swen Weitemeier, Christian Oldendorf