Abstract: A system for analyzing electronic devices includes an input station, a transport apparatus, an electric machine interface station, an electric machine interface, a support structure and first and second thermal components. The input station receives a plurality of electronic devices and the transport apparatus transports each of the electronic devices from the input station to the electric machine interface station. The electric machine interface engages the electronic device when the electronic device is at the electric machine interface station, and is disengageable from the electronic device for the electronic device to be transportable by the transport apparatus away from the electric machine interface station. The first and second thermal components are located on opposing sides of the electronic device when the electronic device is at the electric machine interface station to simultaneously transfer heat to or from the electronic device.

Abstract: Systems and methods are provided for detecting surface charge on a semiconductor substrate having a sensing arrangement formed thereon. An exemplary sensing system includes the semiconductor substrate having the sensing arrangement formed thereon, and a module coupled to the sensing arrangement. The module obtains a first voltage output from the sensing arrangement when a first voltage is applied to the semiconductor substrate, obtains a second voltage output from the sensing arrangement when a second voltage is applied to the semiconductor substrate, and detects electric charge on the surface of the semiconductor substrate based on a difference between the first voltage output and the second voltage output.

Abstract: A method of detecting a short circuit affecting a sensor, at least one terminal of the sensor being connected to a bias resistor, includes: applying to at least one bias resistor at least one test bias voltage having at least one predefined characteristic that is different from a corresponding characteristic of a nominal bias voltage of the resistor; measuring a resulting differential voltage across the terminals of the sensor; and as a function of at least one characteristic of the measured differential voltage corresponding to the predefined characteristic of the test bias voltages, determining whether the sensor presents a short circuit.

Abstract: The present invention provides a test handler for various IC tests, which includes a chamber and a test carrier. The chamber is controllable to present a dry status. The test carrier is made of a high thermal-conductive material and includes plural positioning structures for respectively accommodating plural IC chips. The test carrier is disposed on and in thermal contact with a temperature-adjustment device in the chamber, and the temperature-adjustment device controls the temperature of the IC chips on the test carrier by thermal conduction through the test carrier. The invention also provides a test carrier used in the test handler and a test method thereof.

Abstract: An apparatus and method for measurement of radiation intensity for testing reliability of a solar cell, and a method for testing the reliability of the solar cell. The apparatus includes a first solar cell receiving a predetermined intensity of radiation or more to generate electricity, a second solar cell receiving a predetermined intensity of radiation or more to generate electricity; a temperature sensor sensing a temperature of the second solar cell; a cooler cooling the first solar cell; and a controller measuring the intensity of radiation applied to the first solar cell, and controlling the cooler to prevent the temperature of the first solar cell from increasing above a predetermined temperature depending on the temperature of the second solar cell sensed by the temperature sensor.

Abstract: Initial calibration is performed only under normal-temperature environment, and accurate current control is performed under practical use temperature environment. A temperature sensor 171 is arranged close to a current detection resistor 126 having predetermined temperature characteristics. Resistance values are estimated in a calibration environment and a practical use environment, an actually measured load current in the calibration environment corresponding to a target load current is stored as control characteristic data, a corrected target current corresponding to the target load current is calculated, and a converted target current based on a change ratio of current detection resistance is controlled as a target current for current control. A resistance change amount by heat generation of the current detection resistor 126 which cannot be entirely detected by the temperature sensor 171 is corrected in control characteristic data, such that linearity of control characteristics is improved.

Abstract: An object is to provide a measuring method with high reproducibility in a bias-temperature stress test of a transistor in which an oxide semiconductor is used for a semiconductor layer. Provided is a measuring method of a transistor, which includes the steps of disposing a transistor in which an oxide semiconductor is used for a semiconductor layer in a measurement room having a light-blocking property, introducing dry air, nitrogen, or argon into the measurement room, and applying a predetermined voltage to a gate electrode of the transistor in the measurement room kept under an atmosphere where the dew point is greater than or equal to ?110° C. and less than or equal to ?60° C., whereby the amount of change in threshold voltage over time is measured.

Abstract: An integrated circuit, testing structure, and method for monitoring electro-migration (EM) performance. A method is described that includes method for measuring on-chip electro-migration (EM) performance, including: providing a first on-chip sensor continuously powered with a stress current; providing a second on-chip sensor that is powered only during measurement cycles with a nominal current; obtaining a first resistance measurement from the first on-chip sensor and a second resistance measurement from the second on-chip sensor during each of a series of measurement cycles; and processing the first and second resistance measurements.

Abstract: A substrate evaluation apparatus and method which includes a substrate storage portion accommodating a substrate, first and second fastening portions are arranged in the substrate storage portion and are each fastened to a side of the substrate, a driving portion driving the first and second fastening portions, and a measurement portion measuring electrical characteristics of the substrate through application of an electrical signal to the substrate.

Abstract: The present invention is a system and method for testing the long term reliability of an implantable device. The system provides a vessel containing temperature controlled buffered saline. A support structure suspends a test device in the vessel so it is submerged in the buffered saline and provides mechanical stress on the implantable devices. The test device is eclectically connected to a programmable signal generator and sensors to actively determine the integrity of the device during active testing.

Abstract: An example system for testing electronic assemblies (EAs) may include carriers for holding EAs and slots for testing at least some of the EAs in parallel. Each slot may be configured to receive a corresponding carrier containing an EA and to test the EA. An example carrier in the system may include a first part and a second part. At least one of the first part and the second part include a first structure, and the first structure is movable to enable electrical connection between an EA and an electrical connector.

Abstract: A thermal gradient is induced in a device-under-test (DUT) and used to determine the location of a defect. In one embodiment, a static thermal gradient is induced across at least a portion of the DUT along a first axis. The thermal gradient is incrementally walked along the first axis until the condition associated with the defect is triggered, thereby defining a first region. The thermal gradient is then induced along a second axis of the DUT and the process is repeated to define a second region. The location of the defect is determined to be the intersection of the first region with the second region.

Abstract: An apparatus for thermal testing of a printed circuit board being electrically energized and being unpopulated or populated with electrical or electronic components is disclosed. The apparatus includes a device for pyrometrical scanning of surface temperatures, wherein the scanning device comprises a pyrometric sensor being movable for the purpose of scanning and being adjustable with respect to its distance from the printed circuit board. A method for operating such an apparatus is disclosed. The method includes adjusting the distance between the sensor and the printed circuit board during scanning.

Abstract: An adaptive thermal control system maintains and regulates an accurate and stable thermal environment for a device under test. The adaptive thermal control system includes (i) pre-trigger communications from automatic test equipment (ATE) to automatic thermal control (ATC) allowing slow-responding ATC to start responding to an imminent thermal change before the thermal change occurs, (ii) a control profile which indicates to the ATC, prior to anticipated thermal change, that a change is imminent and the nature of the change over time. The generation and fine-tuning of the control profile can be done by two different methods (i) with the semi-automatic approach the tester does some pre-tests in order to determine a typical response profile which the test program then adjusts using adaptive techniques, (ii) With the fully automatic adaptive circuitries same typical response profile is algorithmically adjusted and utilized to control the ATC.

Abstract: A probe method includes setting an allowable temperature range, the allowable temperature range including a test temperature and ensuring contact between a pad of a circuit substrate and a needle of a probe card, providing the probe card with a temperature within the allowable temperature range, contacting the needle of the probe card to the pad of the circuit substrate, and supplying a test current to the pad through the needle to test the circuit substrate.

Abstract: A test system for calibrating wireless electronic devices is provided. The test system may include a test host, a radio communication tester, and a temperature chamber in which an electronic device under test (DUT) may be tested. The DUT may include a temperature sensor for monitoring an internal temperature of the DUT and may include power amplifier circuitry for outputting radio-frequency test signals. The tester may be used to measure output power levels of the radio-frequency test signals when the DUT is operating at a given reference temperature and when the DUT is operating at target operating temperature levels other than the given reference temperature. Power amplifier output level offset compensation values may be computed by comparing output power levels measured at each of the target operating temperatures to output power levels measured at the given reference temperature and may be stored in the DUT prior to normal operation.

Abstract: There are provided an evaluation device and an evaluation method for a substrate mounting apparatus capable of simply evaluating a temperature control function of the substrate mounting apparatus depending on evaluation conditions or circumstances and an evaluation substrate used for the same. The substrate mounting apparatus holds a target substrate mounted on a mounting surface and controls a temperature of the target substrate. The evaluation device includes an evacuable airtight chamber in which the substrate mounting apparatus is provided; an evaluation substrate which is mounted on the mounting surface instead of the target substrate and includes a self-heating resistance heater; and a temperature measurement unit which measures a temperature of the evaluation substrate.

Abstract: A testing container includes a right-parallelepiped-like container, electrical components of a transformer test system which are arranged in the container and which represent a respective heat source during a testing operation, and a cooling system including at least one heat exchanger. In addition, the testing container includes a movement apparatus configured to move the at least one heat exchanger from a transport position within the container into a working position which is located at least partially outside the container. Thus, the at least one heat exchanger is movable by means of the movement apparatus from the transport position within the container into the working position which is located at least partially outside the container.

Abstract: A micro-spray cooling system beneficial for use in testers of electrically stimulated integrated circuit chips is disclosed. The system includes micro-spray heads disposed about a probe head. The spray heads and probe head are disposed in a sealed manner inside a spray chamber that, during operation, is urged in a sealing manner onto a sealing plate holding the integrated circuit under test. The atomized mist cools the integrated circuit and then condenses on the spray chamber wall. The condensed fluid is pumped out of the chamber and is circulated in a chiller, so as to be re-circulated and injected again into the micro-spray heads. The pressure inside the spray chamber may be controlled to provide a desired boiling point.

Abstract: A method for conditioning a photovoltaic module for testing includes setting an effective irradiance of a continuous light source at a target plane, configuring a test photovoltaic module to operate at a substantially maximum power point configuration, positioning the test photovoltaic module adjacent to the target plane, and configuring the test photovoltaic module for testing by removing the light source, cooling the test module to a testing temperature, and reversing the substantially maximum power point configuration.

Abstract: Devices and methods useful for testing bare and packaged semiconductor dice are provided. As integrated circuit chips become smaller and increasingly complex, the interface presented by a chip for connectivity with power supplies and other components of the system into which it is integrated similarly becomes smaller and more complex. Embodiments of the invention provide micron-scale accuracy alignment capabilities for fine pitch device first level interconnect areas. Embodiments of the invention employ air-bearings to effectuate the movement and alignment of a device under test with a testing interface. Additionally, testing interfaces comprising membranes supported by thermal fluids are provided.

Abstract: Timing, power and SPICE analysis are performed on a circuit layout, based on temperature and stress variations or gradient across the circuit layout. Specifically, the temperature and stress values of individual window locations across the layout are used to obtain temperature and stress variation aware resistance/capacitance (RC), timing, leakage and power values. In addition, in 3D integrated circuits (IC), the stress and thermal variations or gradients of one die may be imported to another die located on a different tier.

Abstract: A thermal gradient is induced in a device-under-test (DUT) and used to determine the location of a defect. In one embodiment, a laser creates a moving thermal gradient from a test site on the DUT and a respective time of flight for the thermal gradient to trigger a condition associated with the defect is determined. Repeating the time of flight testing at additional test site provides information used to trilaterate the defect in three dimensions. Alternately, a static thermal gradient is induced across at least a portion of the DUT along a first axis. The thermal gradient is incrementally walked along the first axis until the condition associated with the defect is triggered, thereby defining a first region. The thermal gradient is then induced along a second axis of the DUT and the process is repeated to define a second region. The location of the defect is determined to be the intersection of the first region with the second region.

Abstract: The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles without the use of environmental ovens. Testing IC devices at elevated temperatures may be useful for ‘burn-in’, for ‘hot sort’ performance testing that may be used in electronic devices such as DRAM memory, logic, communication devices, and microprocessors. The power sink function may be implemented as an additional isolated area of active devices, or as a section of the circuit that is not involved in the testing procedure. Alternately, the power dissipation circuit may consist of a resistive path between two external pins that are not used for IC operation, where the resistor may be on the IC or on the package. This allows for control of the temperature level and profile by simple adjustment of the voltage between the two external pins.

Abstract: A three-dimensional integrated circuit testing apparatus comprises a probe card configured to couple a device-under-test of a three-dimensional integrated circuit with an automatic testing equipment board having a plurality of testing modules, wherein the probe card comprises a plurality of known good dies of the three-dimensional integrated circuit, a plurality of interconnects of the three-dimensional integrated circuit and a plurality of probe contacts, wherein the probe contacts are configured to couple the probe card with testing contacts of the device-under-test of the three-dimensional integrated circuit.

Abstract: The present invention relates to an electronic load module and to a method and a system therefor. The method comprises receiving control data (301) from a connectable power controller via a data bus connector (202), and controlling (302) an active load (203) based on the received control data to sink a defined current from a connectable device under test via a first input (204), The method further comprises controlling (303) the activate load (203) based on the received control data by means of a digital control circuit (201) and the connectable power controller to generate and maintain an ambient temperature of the device under test.

Abstract: Fault analysis of high power integrated circuits face thermal management challenges. This invention employs thermal diodes incorporated in the device undergoing fault analysis, and a closed loop microprocessor controlled feedback system for thermal control during test and fault analysis.

Abstract: A device instructs a power supply to provide a current to a power cycling test structure that includes a heat source interconnected with a package, via a first level interconnect mechanism, and a printed circuit board (PCB) interconnected with the package, via a second level interconnect mechanism. The device also monitors thermal feedback associated with the heat source, and monitors, based on the provided current, voltage feedback associated with the power cycling test structure. The device further determines a thermal profile of the power cycling test structure based on the thermal feedback and the voltage feedback.

Abstract: An electronic device test apparatus which can optimize throughput and costs is provided. An electronic device test apparatus 1 comprises: a test cell cluster 10 having cell groups 11A to 11H each of which has a plurality of test cells 20; and a conveyor apparatus 30 supplying test carriers to a plurality of the test cells 20, and each of the test cell 20 has: contactors 215; a flow path 221 connected to a vacuum pump 25 and reducing pressure in a recess 211 of a pocket 21 so as to bring external terminals 73 and the contactors 215 into contact; and a test circuit for running a test on an electronic circuit formed into a die 90.

Abstract: A system includes electronics for testing a device, a reservoir to store coolant, where the reservoir includes a bellows that is compressible, a pump system to move coolant out of the reservoir to cool the electronics, and means to compress the bellows and thereby pressurize the coolant stored in the reservoir so that the coolant remains substantially flush with an interface to the pump system.

Abstract: A semiconductor integrated circuit which includes a control circuit; and a power management integrated circuit (IC) configured to supply an operating voltage to the control circuit. The control circuit includes a clock generator; a processor unit; a temperature sensor; a body bias generator; and a controller. The controller controls the power management IC and the clock generator when temperature data indicates a temperature higher than a high temperature and controls the power management IC or the body bias generator when the temperature data indicates a temperature lower than a low temperature. The high temperature is lower than a hot temperature of the control circuit and the low temperature is higher than a cold temperature of the control circuit and lower than the high temperature.

Abstract: Disclosed are a probe inspecting method for confirming the state of a probe for inspecting electric characteristics of an object to be inspected; and a curable resin composition for use in the method. The method is applied to repeat inspections and comprises the steps of bringing a cured resin of a curable resin composition into contact with a probe for inspecting electric characteristics of an object to be inspected, transferring a probe mark of the probe to the cured resin, confirming the state of the probe based on the transferred probe mark, and, after the transfer of the probe mark of the probe, heating the cured resin to a temperature at or above the glass transition temperature of the cured resin to erase the probe mark of the probe.

Abstract: An approach is provided in which a system under test is subjected to thermal cycling that include transferring the system under test between two different environments that generate two different ambient temperatures. In turn, a test system tests the electronic assembly in response to the electronic assembly being subjected to the thermal cycles.

Abstract: An IDDQ test system and method that, in one embodiment,deg includes 1) an empirical extraction subsystem operable to generate an IDDQ versus temperature model for a given semiconductor device design, 2) an automatic test equipment (ATE) test subsystem operable to obtain a measured IDDQ value (IDDQm) at a measured temperature (Tm) for a specific semiconductor device embodying the given semiconductor device design, the measured temperature (Tm) obtained within 5 seconds of obtaining the measured IDDQ value (IDDQm), and 3) a scaling subsystem operable to scale the measured IDDQ value (IDDQm) at the measured temperature (Tm) to a compensated IDDQ value (IDDQc) at a desired temperature (Td) using the IDDQ versus temperature model.

Abstract: The invention regards an method for estimating the end of lifetime for a power semiconductor device, such as an IGBT power module, comprising the steps of; establishing the temperature of the power semiconductor device, determining the voltage drop over the power semiconductor device for at least one predetermined current where the current is applied when the power semiconductor device is not in operation, wherein the end of lifetime is established dependent on the change in a plurality of determined voltage drops.

Abstract: Systems and methods for managing process and temperature variations for on-chip sense resistors are disclosed. The system includes a circuit that can leverage a linear gm circuit in order to provide linear gains (positive gains and/or negative gains). The linearity of the circuit enables compensation for temperature and process variations across an entire range of current (positive to negative). A control signal is generated by using a linear gm amplifier and a replica resistor, which is substantially similar to the on chip resistor. The control signal is used to control the gain of a disparate linear gm amplifier within a compensation circuit, which provides an offset voltage to compensate for the variation in resistance of the on chip resistor.

Abstract: Apparatus, systems and methods are provided for controlling a radio frequency board on an individualized basis and with respect to one or more environmental conditions, for example, temperature, pressure, humidity. In one embodiment, an enclosure configured to hold a single board includes one or more access portals and one or more interfaces, wherein the environment within the enclosure may be modified by applying one or more environmental modifiers to the enclosure through an access portal, and the operation of the board may be modified utilizing the one or more interfaces. In another embodiment, a system for testing a plurality of boards, each in their own enclosure is provided.

Abstract: A test head moving apparatus includes elevating arms that move a test head up and down, a frame that horizontally moves the test head, and an interlock mechanism that prohibits the horizontal movement of the frame on the basis of a height of the test head. The interlock mechanism has a limit switch that detects that the test head is positioned at the lowermost limit and stoppers capable of pressing the pressing units onto a floor plane.

Abstract: A thermal chamber and system for influencing the temperature of an IC chip under test including a thermal block that receives a chip socket, the thermal block adapted to be disposed between a docking interface plate and a workpress. The thermal block receives a flow of heated or cooled gas, and causes an IC chip to become heated or cooled prior to and during a test of the chip. The thermal chamber and system allows an IC chip to be testing under specific temperature conditions without using an expensive handler costing hundreds of thousands of dollars.

Abstract: An over-voltage and over-temperature detecting circuit includes a voltage-limiting circuit, a temperature sensing circuit, a current source, a first comparing circuit and a second comparing circuit. The equivalent resistance of the temperature sensing circuit varies with the temperature. The current source provides a first current to a detecting terminal, so that a detecting voltage is generated at the detecting terminal. By comparing the magnitude of the detecting voltage with the first reference voltage value, the first comparing circuit generates a corresponding temperature status signal. By comparing the magnitude of the detecting voltage with the second reference voltage value, the second comparing circuit generates a corresponding voltage status signal. If the temperature exceeds the temperature upper limit, the temperature status signal is in an enabling status. If the first voltage exceeds the voltage upper limit, the voltage status signal is in an enabling status.

Abstract: An integrated circuit device comprises component devices (that include primary and alternate devices) and storage elements connected to the component devices. The storage elements store different sets of repair addresses indicating which of the primary devices and alternate devices are to be enabled. Further, a controller is connected to the storage elements, and a temperature sensor is connected to the controller. The temperature sensor senses the temperature. The controller selects one of the different storage elements to select at least one of the sets of repair addresses based on the temperature sensed by the temperature sensor. The sets of repair addresses share use of at least one of the alternate devices and at least one of the primary devices.

Abstract: A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with said storage circuit (110) and with said functional circuit modules (IP.i), said test controller (140, 150) operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.

Abstract: The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles without the use of environmental ovens. Testing IC devices at elevated temperatures may be useful for ‘burn-in’, for ‘hot sort’ performance testing that may be used in electronic devices such as DRAM memory, logic, communication devices, and microprocessors. The power sink function may be implemented as an additional isolated area of active devices, or as a section of the circuit that is not involved in the testing procedure. Alternately, the power dissipation circuit may consist of a resistive path between two external pins that are not used for IC operation, where the resistor may be on the IC or on the package. This allows for control of the temperature level and profile by simple adjustment of the voltage between the two external pins.

Abstract: A method and an apparatus for verifying or testing test substrates, i.e. wafers and other electronic semiconductor components, in a prober under defined thermal conditions. Such a verifying apparatus, known to the person skilled in the art as a prober, has a housing having at least two housing sections, in one housing section of which, designated hereinafter as test chamber, the test substrate to be verified is held by a chuck and is set to a defined temperature, and in the other housing section of which, designated hereinafter as probe chamber, probes are held. For verification purposes, the test substrate and the probes are positioned relative to one another by means of at least one positioning device and the probes subsequently make contact with the test substrate.

Abstract: A system for analyzing electronic devices includes an input station, a transport apparatus, an electric machine interface station, an electric machine interface, a support structure and first and second thermal components. The input station receives a plurality of electronic devices and the transport apparatus transports each of the electronic devices from the input station to the electric machine interface station. The electric machine interface engages the electronic device when the electronic device is at the electric machine interface station, and is disengageable from the electronic device for the electronic device to be transportable by the transport apparatus away from the electric machine interface station. The first and second thermal components are located on opposing sides of the electronic device when the electronic device is at the electric machine interface station to simultaneously transfer heat to or from the electronic device.

Abstract: A chuck for supporting and retaining a test substrate includes a device for supporting and retaining a calibration substrate. The chuck comprises a first support surface for supporting a test substrate and a second support surface, which is laterally offset to the first support surface, for supporting a calibration substrate. The calibration substrate has planar calibration standards for calibration of a measuring unit of a prober, and dielectric material or air situated below the calibration substrate at least in the area of the calibration standard. In order to be able to take the actual thermal conditions on the test substrate and in particular also on known and unknown calibration standards and thus the thermal influence on the electrical behavior of the calibration standard used into consideration, the second support surface is equipped for temperature control of the calibration substrate.

Abstract: A thermal controller includes a thermal control interface to receive test data from an automated test equipment (ATE) system and dynamically adjust a target setpoint temperature based on the data and a dynamic thermal controller to receive the target setpoint temperature from the thermal control interface and control a thermal actuator based on the target setpoint temperature.

Abstract: A test pusher assembly, useful in association with a thermal control unit used to maintain a set point temperature on an integrated circuit device under test, is provided with ejection mechanisms configured to facilitate the disengagement of the DUT at the end of the test. One example of the ejection mechanisms is to provide the substrate pusher assembly with spring-loaded pins that can push the substrate of the DUT away from the pedestal at the end of the test. Another example of the ejection mechanisms is to use a pressurized fluid that can push the substrate of the DUT away from the pedestal at the end of the test.

Abstract: A method for quasi-static testing a magnetic recording head read sensor is described. The method includes applying a first voltage to a heater in the magnetic recording head and measuring an output of the magnetic recording head read sensor while applying the first voltage to the heater and recording the measured output as a first set of measurements. The method further includes applying a second voltage to the heater in the magnetic recording head and measuring the output of the magnetic recording head read sensor while applying the second voltage to the heater and recording the measured output as a second set of measurements. The first and second sets of measurements are then compared.

Abstract: Thermal control units (TCU) for maintaining a set point temperature on an IC device under test (DUT) are provided. The units include a pedestal assembly comprising a heat-conductive pedestal, a fluid circulation block, a thermoelectric module (Peltier device) between the heat-conductive pedestal and the block for controlling heat flow between the pedestal and fluid circulation block, and a force distribution block for controllably distributing a z-axis force between different pushers of the TCU. Alternatively, instead of a thermoelectric module, a heater can provide heat to the DUT. Optionally, a swivelable temperature-control fluid inlet and outlet arms may be provided to reduce instability of the thermal control unit due to external forces exerted on the TCU such as by fluid lines attached to the fluid inlet and outlet arms. Also optionally, an integrated means for abating condensation on surfaces of the TCU during cold tests may be provided.