Abstract: Techniques include systems and methods of synchronizing multiple parallel inverters in a power converter system. In one embodiment, control circuitry is connected to a power layer interface circuitry at each of the parallel inverters, via an optical fiber interface. The system is synchronized by transmitting a synchronizing pulse to each of the inverters. Depending on the operational mode of the system, different data exchanges may occur in response to the pulse. In an off mode, power up and power down data may be exchanged between the control circuitry and the inverters. In an initiating mode, identification data may be transmitted from the inverters to the control circuitry. In an active mode, control data may be sent from the control circuitry to the inverters. In some embodiments, the inverters also transmit feedback data and/or acknowledgement signals to the control circuitry.

Abstract: There has been a problem in a conventional semiconductor device that a great deal of time is needed for a returning process associated with circuit correction. A semiconductor device according to the present invention includes a plurality of trigger signal driving elements (FFa and FFb) that synchronize with a trigger signal and operate, trigger wiring lines (CW0 to CW3) that distribute the trigger signal to the plurality of trigger signal driving elements, an additional trigger wiring line (CWb) that is provided by branching from the trigger wiring lines (CW0 to CW3), and an additional supply element (30) that is supplied with the trigger signal via the additional trigger wiring line (CWb) and separated from the plurality of trigger signal driving elements.

Abstract: Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data.

Abstract: A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.

Abstract: An invention is provided for gate training in memory interfaces. The invention includes adding a coarse delay to a gate assert time, where the coarse delay is a predefined period of time and the gate assert time is a time when a data strobe gate signal is asserted. Next, the a data strobe signal is repeatedly sampled at the gate assert time until a rising edge of the data strobe signal is found, wherein a fine delay is added to the gate assert time between sampling of the data strobe signal. The fine delay is a period of time shorter than the coarse delay. Once the rising edge is found, the coarse delay is removed from the gate assert time, thus setting the gate assert time centrally within the preamble of the data strobe signal.

Abstract: An arrangement is described which reduces the number of phase locked loops (PLLs) required in a typical high speed serial interface system. A reference clock is sent from a transmitter on a main board to a receiver on a system board, which employs a PLL that also drives a transmitter on the system board. The transmitter on the system board transmits a data signal to a receiver on the main board which does not require a PLL. Rather, the receiver on the main board is clocked with a static-phase, master reference clock, and the phase of the reference clock sent from the main board is controlled so as to achieve synchronism of the data signal received by the main board receiver using the static-phase, master reference clock.

Abstract: A delay method for determining an activation moment of an output device in a circuit system is disclosed. The delay method includes determining resistance of an over-current flag pull-high resistor of the circuit system, generating a current according to the resistance of the over-current flag pull-high resistor and a voltage drop across the resistor, duplicating the current to generate a first mirror current, delaying an enable signal of the circuit system according to the first mirror current to generate a charging activation signal, providing a charging current according to the charging activation signal, and determining the activation moment of the output device according to the activation current.

Abstract: A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the internal power-supply voltage from the first power-supply circuit through a first line, a second internal circuit that receives a supply of the internal power-supply voltage from the second power-supply circuit through a second line, an inter-block line that connects the first and second lines to each other, and a control circuit that operates the first and second internal circuits in a predetermined operating cycle, and controls a length of a period during which the first and second internal circuits operate simultaneously.

Abstract: Methods and apparatus for determining at least part of the width of the eye of a high-speed serial data signal use clock and data recovery circuitry operating on that signal to produce a first clock signal having a first phase relationship to the data signal. The first clock signal is used to produce a second clock signal whose phase can be controllably shifted relative to the first phase. The second clock signal is used to sample the data signal with different amounts of phase shift, e.g., until error checking circuitry detects that data errors in the resulting sample exceed an acceptable threshold for such errors. The amount(s) of phase shift that caused exceeding the threshold can be used as a basis for a measurement of eye width.

Abstract: A transmission circuit that performs modulation based on a phase difference signal and an amplitude signal includes an asymmetrical phase rotation device. The asymmetrical phase rotation device performs an operation of subtracting 2? from a value of the phase difference signal when the value of the phase difference signal is greater than a predetermined positive threshold value, or an operation of adding 2? to the value of the phase difference signal when the value of the phase difference signal is less than a predetermined negative threshold value. Accordingly, the transmission circuit has distortion reduction characteristics improved uniformly over a range of frequencies higher or lower than a carrier wave band.

Abstract: Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed.

Abstract: A synchronized clock system, for use with an electronic system having several system nodes requiring a synchronized clock signal. The clock system may be formed in either discrete form or in integrated form, or in any combination, and includes a first synch bus and a second synch bus, isolated from the first synch bus, and at least one pair and preferably several pairs of SXO modules connected to the busses in alternating fashion. Each of the system nodes is connected at a different one of any number of arbitrarily selected connection points anywhere along the first bus. The points along the busses at which the SXO modules are connected are spaced roughly equidistantly apart. The system nodes are connected to the bus by means of signal conditioning circuits, which may include correction circuits, an amplifier, a frequency multiplier, a logic translator and a fan buffer.

Abstract: This invention discloses a self-timing method for phase adjustment. An analog signal is digitized at a first and second phase with respect to the symbols comprised in an analog signal in order to obtain first and second quantized samples. Then a first counter out of a first plurality of counters is increased if said first quantized sample has a first digital value to which said first counter is associated. Moreover a second counter out of a second plurality of counters is increased if a second quantized sample has a second digital value to which the second counter is associated. Finally the sampling phase is adjusted based on the values of the counters of the first and second plurality of counters. Moreover a digitizing, self-timing circuit is disclosed.

Abstract: The present invention is a phase dithered digital communications system that includes a digital receiver, and uses phase dithering to spread the energy of one or more system clocks to minimize receiver de-sensitization. Phase dithering uses a single frequency for each system clock; however, the energy of each system clock is spread over a range of frequencies by changing the duty-cycle of each clock half-cycle. A non-phase dithered clock drives the sampling clock of a receiver analog-to-digital converter to provide accurate correlation with received information, which may allow use of a higher frequency sampling clock than in frequency dithered designs. Phase dithered clocks and non-phase dithered clocks may have constant frequencies that are related to each other by a ratio of two integers; therefore, the time base used for extracting received data is always correlated and accurate.

Abstract: Various embodiments generally relate to a method for synchronizing a receiver, said method including receiving a stream that includes a cyclic extension, estimating a size of the cyclic extension, extracting an amount of the stream according to the estimated size, and comparing the extracted amount to the stream to determine thereby a portion of the stream likely to include a symbol start point.

Abstract: The output bits of a binary ripple counter are used to control the sampling of those output bits, thereby ensuring accurate sampling. A sampler is provided with adjustable delay elements that permit accurate sampling regardless of: delay mismatch between the sampler and a data path of the counter; the length of the counter; operating speed; or PVT variations.

Abstract: Various embodiments of the present invention provide systems and circuits that provide for out of band detection. As one example, an out of band detection circuit is disclosed that includes an input signal, a clock generation circuit, and a sampling circuit. The clock generation circuit receives the input signal and derives therefrom a sampling clock, and the sampling circuit is operable to sample the input signal at a time indicated by the sampling clock.

Abstract: An integrated circuit device having a selectable data rate clock data recovery (CDR) circuit and a selectable data rate transmit circuit. The CDR circuit includes a receive circuit to capture a plurality of samples of an input signal during a cycle of a first clock signal. A select circuit is coupled to the receive circuit to select, according to a receive data rate select signal, one of the plurality of samples to be a first selected sample of the input signal and another of the plurality of samples to be a second selected sample of the input signal. A phase control circuit is coupled to receive the first and second selected samples of the input signal and includes circuitry to compare the selected samples to determine whether the first clock signal leads or lags a transition of the input signal. The transmit circuit includes a serializing circuit to receive a parallel set of bits and to output the set of bits in sequence to an output driver in response to a first clock signal.

Abstract: Circuits, systems, and related methods to measure a performance characteristic(s) associated with a semiconductor die and adjust a clock signal based on the measured performance characteristic(s) are provided. The adjusted clock signal can be used to provide a clock signal to a functional circuit provided in the semiconductor die to assure proper operation of the functional circuit while operating with performance, voltage, temperature (PVT) delay variations. In this regard, a performance monitoring circuit is provided in the semiconductor die that includes the functional circuit. As a result, the performance monitoring circuit may be exposed to similar delay variations as the functional circuit. The performance monitoring circuit is configured to measure a performance characteristic(s) associated with the semiconductor die.

Abstract: A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data.

Abstract: An apparatus for testing setup/hold time includes a plurality of data input units, each configured to calibrate setup/hold time of input data in response to selection signals and setup/hold calibration signals, and an off-chip driver calibration unit configured to generate the selection signals and the setup/hold calibration signals by using the input data input of one of the plurality of data input units.

Abstract: Provided are an apparatus and method for synchronizing a timing clock between a transmission signal and a reception signal. The apparatus for synchronizing a timing clock includes a timing restorer configured to restore a timing clock based on a digital input data; and a timing clock synchronizer configured to synchronize the timing clock based on timing information and a timing restoration signal restored in the timing restorer.

Abstract: A system and method for data sending and receiving processing using a secondary data transmit channel is disclosed. The system comprises a device and a device base in which a secondary data transmit channel on the device is enabled when the device is coupled to the device base and receives a triggering signal from the device base. The system implements a 2T2R RF design in which the use of an additional data transmit channel increases the uplink transmit gain and coverage and reduces the deployment costs of base stations.

Abstract: A main (sub) clock circuit comprising a first (second) capacitor, a first (second) current-supply circuit to supply to the first (second) capacitor a first (third) current for charging at a predetermined-current value or a second (fourth) current for discharging at a predetermined-current value, a first (second) charge/discharge-control circuit to output a first (second) control signal for switching between the first (third) current and second (fourth) current which are supplied to the first (second) capacitor from the first (second) current-supply circuit when a voltage across the first (second) capacitor has reached a first (third) reference voltage or second (fourth) reference voltage higher than the first (third) reference voltage, and a first (second) output circuit to output a main (sub) clock according to the first (second) control signal, the first capacitor having one end connected to a first potential, the second capacitor having one end to which the main clock is input.

Abstract: A semiconductor device according to one aspect of the present invention includes: a flip-flop; a clock control circuit that controls a clock signal supplied to the flip-flop; and a controller that supplies a data retention signal to the flip-flop and controls the clock control circuit. When the flip-flop is driven by a negative edge of the clock signal and retains data when the clock signal is at a high level, the controller controls the clock control circuit so as to supply a high-level clock signal to the flip-flop after the input clock signal is fixed and before the flip-flop retains data. This prevents the occurrence of unintended latching of data when the flip-flop having a retention function retains data.

Abstract: An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay line delaying the first intermediate signal by a first delay amount; a second delay line delaying the first intermediate signal by a second delay amount; a third delay line delaying the second intermediate signal by a third delay amount; and a fourth delay line delaying the second intermediate signal by a fourth delay amount. The apparatus also includes a closed feedback loop for detecting and adjusting the second and fourth delay amount.

Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

Abstract: A semiconductor device and a test apparatus including the same, the semiconductor device including a command distributor receiving a serial command that is synchronized with a first clock signal and converting the serial command into a parallel command, a command decoder receiving the parallel command and generating a pattern sequence based on the parallel command, and a signal generator receiving the pattern sequence and generating operating signals synchronized with a second clock signal, wherein a frequency of the first clock signal is less than a frequency of the second clock signal.

Abstract: According to one embodiment, a test circuit comprises a function block, a test circuit, and a signal generation circuit. The test circuit is arranged in an area close to the function block having a plurality of transistors. The test circuit comprises a first flip-flop circuit, a second flip-flop circuit, and a logic circuit connected between the output of the first flip-flop circuit and the input of the second flip-flop circuit. The signal generation circuit generates clock pulses including a first clock pulse and a second clock pulse. The signal generation circuit is capable of controlling a pulse interval between the first clock pulse and the second clock pulse. In a test, the first flip-flop circuit outputs data in synchronization with the first clock pulse of the signal generation circuit and the second flip-flop circuit latches data in synchronization with the second clock pulse of the signal generation circuit.

Abstract: Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with a shift register with a dynamic entry point, which may particularly useful for aligning skewed data. The dynamic entry shift register typically includes a series of storage elements, with multiplexers distributed between the storage elements. Each of the multiplexers is configured to select between: (a) the output signal of a previous storage element, and (b) the input signal. A control is configured to configure the multiplexers for a data signal applied as the input signal to induce an appropriate delay of the data signal as the output signal. The dynamic entry shift register can be scaled to accommodate a longer delay while still using only 2:1 multiplexers between stages in the dynamic entry shift register(s).

Abstract: A digital electronic device is provided with a first and second sequential logic unit (SS1, SS2), each for receiving an input signal (D) and for outputting a first and second output signal (Q, QF), respectively. The electronic device furthermore comprises a comparator unit (C) for comparing the first and second output signals (Q, QF) and an adaptive clock generator unit (ACG) for generating a first and second internal clock (CK, CKF) for the first and second sequential logic unit (SS1, SS2), respectively. In a self-tuning mode, the adaptive clock generator unit (ACG) is adapted to delay the first and second internal clock signals (CK, CKF) with respect to the other internal clock signal (CKF). The delay induced by the adaptive control generator unit (ACG) is dependent on the result of the comparison unit (C). In a normal operation mode the adaptive control generator unit (ACG) is adapted to maintain the delay between the first and second internal clock signals constant.

Abstract: Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality.

Abstract: A multiphase delay unit causes different delay times to a reference clock to generate a multiphase clock with different phases. A multiphase sampling unit samples the input signal using the multiphase clock, and outputs multiphase sampling data. A phase selecting unit detects a phase relation of the multiphase clock using the multiphase sampling data, and selects output data from the multiphase sampling data based on a result of detecting the phase relation.

Abstract: A communication controller and a method is provided for synchronizing a wireless communication device and a wireless communication network having two or more transmit antennas, which support transmit diversity. A reference signal is received from the wireless communication network via each one of a pair of the two or more transmit antennas. A preferred phase offset is then determined for the pair of transmit antennas, and then transmitted to the wireless communication network. Further adjustments of the requested phase and amplitude of the communications transmitted using the pair of transmit antennas are suspended, until further transmissions are received from the wireless communication network via the corresponding transmit antennas, which can be decoded in accordance with the preferred phase offset or a timer has elapsed corresponding to the maximum time needed for the wireless communication network to receive the preferred phase offset and synchronize to the same.

Abstract: Common sample timing control for sample timing of multiple read channels, wherein the signal clocking of the signals received by the multiple read channels are correlated, for example from parallel tracks of magnetic tape that have been written simultaneously. In one embodiment, a common sample timing control comprises multiple phase error inputs, each indicating phase error of one of the read channels. Logic responsive to the multiple phase error inputs is configured to weight and crosscouple the phase error indication of each phase error input with the phase error indication of each other phase error input, and to apply gain related to the variance of noise of the phase error indications. Feedback logic is responsive to the crosscoupling and is configured to provide a sample timing phase estimate for each read channel.

Abstract: In an orthogonal frequency division multiplexed (OFDM) multiple-in multiple-out (MIMO) wireless communication system, a method for correcting sampler clock frequency offset in a receiver comprises acquiring the frequency offset and symbol timing in a received signal by the receiver. The estimated value of a fractional offset is computed, and a correction in the frequency domain based upon the estimated value of the fractional offset is performed.

Abstract: A power supply circuit for a south bridge chip includes a voltage sampling circuit, a control circuit, and an I/O controller. The voltage sampling circuit comprises an input terminal capable of receiving a first voltage, and an output terminal capable of outputting a control signal. The control circuit is capable of receiving the control signal from the voltage sampling circuit and outputting a power good signal when a high voltage level control signal is received. The I/O controller is capable of receiving the power good signal from the control circuit, adjusting time sequence for the power good signal to synchronize with the first voltage, and outputting the adjusted power good signal to provide power for the south bridge chip.

Abstract: One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an internal clock signal provided by an internal clock generator. The internal clock generator may be enabled upon detecting inputs on the one or more asynchronous signals, and disabled once the one or more asynchronous inputs are synchronized with the internal clock signal. Thus, the internal clock signal is provided only for a duration required to synchronize the one or more asynchronous signals. Embodiments of the asynchronous synchronization device, as disclosed herein, may be implemented in a processor-based device and/or a memory device.

Abstract: Provided is a test apparatus and a test method for substantially synchronizing phases of test signals for each of a plurality of clock domains. The test apparatus tests a device under test including a plurality of clock domains.

Abstract: A method and apparatus for producing timing signals for an ultra wideband pulse generator are provided. The apparatus comprises a frequency multiplier for generating a converted signal having a multiple of a pulse frequency of a reference clock signal inputted into the frequency multipliers. Furthermore, the apparatus comprises a feedback controlled delay circuitry connected to the frequency multipliers, for generating at least two versions of the converted signal, the at least two versions having a predefined delay with respect to each other, the two versions being used as timing signals for an ultra wideband pulse generator.

Abstract: A technique for reducing crosstalk between communications paths includes scrambling data using scrambling functions that reduce or substantially minimize a probability that worst-case data patterns occur on communications paths adjacent to a potential victim communications path. In at least one embodiment of the invention, a method includes scrambling a plurality of data bits based at least in part on respective ones of a plurality of distinct combinations of one or more taps of a linear feedback shift register (LFSR). The plurality of data bits are scrambled for transmission during a first bit-time on corresponding ones of a plurality of adjacent communications paths.

Abstract: A fractional-type phase-locked loop circuit is proposed for synthesising an output signal multiplying a frequency of a reference signal by a fractional conversion factor, the circuit including means for generating a modulation value, means for generating a feedback signal dividing the frequency of the output signal by a dividing ratio, the dividing ratio being modulated according to the modulation value for providing the conversion factor on the average, means for generating a control signal indicative of a phase difference between the reference signal and the feedback signal, means for controlling the frequency of the output signal according to the control signal, and means for compensating a phase error caused by the modulation of the dividing ratio; in the circuit of an embodiment of the invention, the means for compensating includes means for calculating an incremental value, indicative of an incremental phase error, according to the conversion factor and the modulation value, means for calculating a corr

Abstract: Conventional retimers generally consume too much power, are too noisy, and are too large. Additionally, phase noise and jitter are generally a function of retiming. As a result, a retimer is provided with a smaller footprint that has reduced power consumption and improved noise characteristics over other conventional retimers.

Abstract: A synchronization apparatus and method for synchronizing a plurality of test and measurement apparatuses or signal generators are provided. A trigger selector is provided or for selecting from a plurality of triggers to be provided to the plurality of test and measurement apparatuses. A trigger enabled input is also provided for receiving a trigger enabled signal from each of the plurality of test and measurement apparatuses and a synchronizing block is provided for generating a single synchronized time stamp signal with the selected trigger and the trigger enabled inputs. A plurality of trigger outputs are also provided for providing the time stamp signal to a trigger input of each of the plurality of test and measurement apparatuses.

Abstract: A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.

Abstract: One inventive aspect relates to a digital sub-circuit suitable for embedding in an at least partially digital circuit for minimizing the influence of another digital sub-circuit on the at least partially digital circuit, the other digital sub-circuit being part of the at least partially digital circuit. The influence of the other digital sub-circuit may, for example, be the introduction of ground bounce by switching of the other digital sub-circuit. Another inventive aspect relates to an at least partially digital circuit comprising such a digital sub-circuit for minimizing the influence of another digital sub-circuit to the at least partially digital circuit and to a method for reducing the influence of another digital sub-circuit to an at least partially digital circuit.

Abstract: A data output control circuit controls a data output in a read operation. A data output control method includes a count shifting mode and a delay mode and can be used in low and high frequency operations, so that a data output can be stably controlled in a broad frequency range. The data output control circuit includes: a low frequency mode controller a high frequency mode controller and a selector selecting any one of first and second command signals through CAS latency information to be output as a data output control signal.

Abstract: A translation circuit for mediating between a fiber-optic controller chip and a host device. The translation circuit may be on a fiber-optic transponder. The controller chip includes a phase locked loop that outputs a short synchronization signal when a hunting frequency passes through a target data signal frequency while hunting for a data signal and outputs a synchronization signal when the phase locked loop is locked onto a data signal. The translation circuit distinguishes between the synchronization signals and generates a lock signal when the phase locked loop is locked onto a data signal, but does not when the hunting frequency passes through the target data signal frequency. The lock signal may be used by a host device into which the fiber-optic transponder has been in installed. Errors from misinterpreted signals can thus be mitigated.

Abstract: A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a power on pulse at the slave divider unit, synchronizing the phase of the slave divider unit to the reference signal using a digitally controlled oscillator, and powering on the slave divider unit after a first predetermined delay period following a rising edge of the power on pulse. By synchronizing a slave divider unit to the reference signal from the master divider unit, any number of slave divider units may be powered on and in-phase with each other.

Abstract: A clock recovery apparatus for generating a recovery clock from received data may include, but is not limited to, first and second oscillators. The first oscillator generates a first signal having a first frequency. The first signal synchronizes with the received data when the received data has a first level. The second oscillator is connected in series to the first oscillator. The second oscillator generates a second signal as the recovery clock when the first signal has a second level. The second signal has a second frequency. The second signal synchronizes with the first signal.