Abstract: A semiconductor apparatus is provided. The apparatus includes a transmission control unit configured to generate, in response to a received pulse signal having a first pulse width, transmission control signals with a second pulse width larger than the first pulse width and synchronization control signals with a third pulse width larger than the second pulse width. The apparatus also includes a reception control unit configured to generate reception control signals in response to the synchronization control signals.

Abstract: There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.

Abstract: A stochastic signal generation circuit includes a signal output circuit and a signal processing circuit connected with the signal output circuit. The signal output circuit includes two matching semiconductor components, wherein the signal output circuit detects a slight mismatch between the two matching semiconductor components, converts the detected slight mismatch into a corresponding electric signal, amplifies the electric signal, and outputs an analog voltage signal. The signal processing circuit converts the analog voltage signal into a stochastic digital signal. Also, a method for generating a stochastic signal is provided. The present invention decreases the cost of the integrated circuit, and better ensures the information security of the electronic products.

Abstract: Disclosed herein is a device that includes a plurality of one-shot pulse generation circuits connected in series between an input node and an output node. Each of the one-shot pulse generation circuits receives an input clock signal supplied from previously connected one-shot pulse generation circuit to output an output clock signal to subsequently connected one-shot pulse generation circuit. Both of a rising edge and a falling edge of the output clock signal are controlled based on one of a rising edge and a falling edge of the input clock signal. A time period from one of the rising edge and the falling edge of the output clock signal to the other of the rising edge and the falling edge of the output clock signal being variable.

Abstract: According to one embodiment, a digital filter circuit includes an EXOR circuit, a clock gating circuit, a reset control circuit, a counter, a filter time setting circuit, a comparator, and a decoder. The clock gating circuit outputs a clock gating signal. The reset control circuit generates a first signal. The counter generates a count signal. The filter time setting circuit latches the count signal when the first signal is in the enable state, and outputs a latched count value as a second signal. The comparator receives the count signal and the second signal, and outputs a third signal of the enable state when the value of the count signal and the value of the second signal match each other.

Abstract: Provided is a timing control device including: a storage unit that stores multiple pieces of timing control information including identification information and expected value data; a first selector that selectively outputs any of the multiple pieces of timing control information; a second selector that selectively outputs any of data items output from data output devices based on the identification information; a reference data generation unit that generates reference data based on expected value data and a data item output from the second selector in synchronization with a switching of the timing control information; a comparator that compares the reference data with the data item output from the second selector and outputs a coincidence signal when the reference data and the data item coincide with each other; and an output control unit that outputs a timing signal according to the coincidence signal.

Abstract: A digital glitch filter for filtering glitches in an input signal includes first and second flip-flops and a synchronizer. The synchronizer includes third and fourth flip-flops. A glitch prone input signal is provided to the first and second flip-flops. Additionally, an input clock signal is provided to the first and second flip-flops and the synchronizer. A glitch occurring in the input signal toggles the first and second flip-flops between transmitting and non-transmitting states and first and second intermediate signals are generated. The synchronizer synchronizes the first and second intermediate signals with the input clock signal to generate a filtered output signal.

Abstract: Determining time latency at a sensor node in a mesh network. A beacon time is received at the sensor node from an upstream node, the beacon time offset from global time by the latency. The latency, the global time, and a corresponding local time are determined at the sensor node.

Abstract: An object is to provide a clock synchronization circuit capable of stable communication even in the case where different clock signals are used in a plurality of circuits, and a semiconductor device provided therewith. Circuit for detecting a change point of received data, and outputting a reset signal; reference clock generating means for generating a clock signal; and circuit for counting the clock signals outputted from the reference clock generation means, and resetting a counter value obtained by counting the clock signals in the case where the reset signal is inputted are provided.

Abstract: A communication system includes a synchronizing signal generator that generates a synchronizing signal based on a timing of an alternating waveform in a power line, a data communicating circuit that performs the data communication, and a communication controller that controls to acquire a transmitting right utilizing a timing of the synchronizing signal and to control the communication circuit in accordance with whether or not the communication apparatus acquires the transmitting right.

Abstract: A method for the generation of a signal including a minimum of disturbances and noise is provided. A method for the detection of a signal including a minimum of disturbances and noise is also provided. An element of the signal is functionally dependent on at least one further element of the signal.

Abstract: The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.

Abstract: A receiver includes a receiving unit that receives a signal from a satellite, a frequency conversion-discretization unit that converts the signal received in the receiving unit into an intermediate frequency signal of a frequency bandwidth including 0 Hz, and discretizes the frequency-converted intermediate frequency signal with a predetermined sampling frequency, a filter unit that filters the discretized signal, which is output from the frequency conversion-discretization unit, through a predetermined filter, a synchronization acquisition unit that acquires synchronization of a spreading code in the discretized signal filtered by the filter unit, and a synchronization holding unit that holds the synchronization of the spreading code, which is acquired by the synchronization acquisition unit.

Abstract: A semiconductor integrated circuit includes a command generating unit configured to generate a plurality of second commands in response to a first command, each second command for indicating an operation sections of a corresponding anti-fuse circuit, and a plurality of anti-fuse circuits, each comprising an anti-fuse and configured to receives a corresponding second command and perform a rupture operation of the anti-fuse in response to the received corresponding second command.

Abstract: Provided are a transmission device, a receiving device, and a communication system having a simple configuration and capable of reliably executing the confirmation of a changed bit rate. The communication system 1 sends, to the receiving device 3, a serial data signal Sdata that is set as a constant value across a period of a constant multiple of a cycle of the clock when a bit rate of a serial data signal Sdata in the transmission device 2 is changed. The receiving device 3 that received the serial data signal Sdata receives training data Tdata from the transmission device 2 when it is determined that the serial data signal Sdata is a constant value across a period of a constant multiple of a cycle of the clock, and proceeds to the processing of confirming the changed bit rate.

Abstract: A method and apparatus for controlling the frequency of a clock signal using a clock-gating circuit is disclosed. In one embodiment, a root clock signal and an enable signal are provided to a clock-gating circuit. The clock-gating circuit is configured to provide an operational clock signal (based on the root clock signal) when the enable signal is asserted. The operational clock signal is inhibited when the enable signal is de-asserted. The frequency of the operational clock signal can be output at a reduced frequency (relative to the root clock signal) by asserting the enable signal for one of every N clock cycles. Furthermore, the frequency of the operational clock signal can be dynamically changed by changing the rate of asserting the enable signal relative to the root clock signal, without suspending operation of a functional unit receiving the operational clock signal.

Abstract: A source synchronous signal synchronization system includes a differential signal receiver; a tunable input delay element coupled to the receiver; an input serializer/deserializer (ISerDes) coupled to the tunable input delay; an alignment unit coupled to the ISerDes; and a delay control unit coupled to the tunable input delay, the ISerDes, and the alignment unit.

Abstract: Provided are transmitter topology, receiver topology and methods for generating and transmitting a radio signal at a transmitter and detecting and processing a radio signal at a receiver. The radio signals are transmitted across a wireless interface using Ultra Wideband (UWB) pulses. A transmitted reference approach is utilized. The radio signal include pairs of UWB pulses with each pair of pulses separated by a fixed time delay. The two pulses are then combined to provide for improved noise immunity.

Abstract: An asynchronous clock adapter is disclosed that transmits multiple data elements from a buffer in a source clock domain to a data register in a destination clock domain. The buffer can be selected by a pointer register in the destination clock domain and a round trip timing path exists from the pointer register to the data register. Data elements from the buffer can be sent on interleaved cycles of the destination clock such that each data element can have a delay constraint of more than one clock period.

Abstract: A display device includes a skew compensating type data receiving unit for delaying clocks received in response to a program signal, comparing the clocks delayed thus to compensating clocks, setting an internal delay amount according to a result of the comparison, and delaying and forwarding a low voltage differential signals according to the delay amount set thus, a clock receiving unit for delaying the clock received thus by a fixed delay amount and forwarding the clock delayed thus as a compensating clock, a clock generating unit for generating a data restoring clock by using the clock delayed thus, and a data restoring logic for restoring the low voltage differential signal delayed at the data receiving unit in synchronization with the data restoring clock, thereby compensating for an internal skew taking place at the data channel which receives a low voltage differential signal.

Abstract: Systems and methods are described including receiving a clock signal, using rational clock divider (RCD) logic to generate a lower frequency clock signal in response to the received clock signal, and using the second clock signal to drive software timer logic and generate media timestamps.

Abstract: An array antenna apparatus in which an SN ratio is improved. Antenna elements having transmission modules, respectively, are arranged in plurality, wherein the plurality of transmission modules respectively have transmission signal generators that each output a transmission intermediate frequency signal, local oscillation signal generators that each output a local oscillation signal, and transmission mixers that each mix the transmission intermediate frequency signal and the local oscillation signal with each other, thereby to carry out frequency conversion to a transmission high frequency signal. A reference signal source inputs a reference signal to the transmission signal generators and the local oscillation signal generators. The transmission intermediate frequency signal and the local oscillation signal are synchronized with each other by the reference signal.

Abstract: An integrated circuit comprises clock gating circuitry comprising at least one gating component located within a clock distribution network and arranged to enable at least one part of the clock distribution network to be gated, and gating control circuitry arranged to cause the at least one gating component to disable the at least one part of the clock distribution network upon certain conditions being fulfilled. The clock gating circuitry further comprises clock gating disabling circuitry configurable to enable the gating of the at least one part of the clock distribution network to be disabled.

Abstract: A synchronizer constituted of a first and second set of three serially coupled latches coupled to a common clocking signal, the first and the ultimate latch of the first set responsive to a first edge of a common clocking signal and the penultimate latch responsive to an opposing edge of the common clocking signal, the second set being respectively responsive to the respective complementary edges of the clocking signal; an input lead arranged to receive a signal to be synchronized, the input lead coupled to the input of the first latch of the first set and to the input of the first latch of the second set; and a filter arranged to pass the output of each of the first set and the second set responsive to the penultimate latch of the set exhibiting a consistent output for two consecutive opposing edges.

Abstract: A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees of the clock mesh network in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path of the design area. The method encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. With gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The method has two synthesis modes as low power mode and high performance mode to serve different design purposes.

Abstract: In a method and a device for decoding a signal, the signal is transmitted via at least one connecting line of a data transmission system, in a user of the data transmission system receiving the signal. It is provided to measure the interval of a change—provided compulsorily in a transmission protocol used in the data transmission system—of the signal from rising to falling or from falling to rising edge. A tendency for an asymmetrical delay of the signal can be ascertained from the measured interval. The sampling of the bits of the received signal can be improved as a function of the interval or of the asymmetrical delay, for example, by setting the sampling instant in variable fashion. Alternatively, the interval or the asymmetrical delay can be utilized for diagnostic purposes.

Abstract: A system including an estimation module, a processing module, and a control module. The estimation module is configured to generate a first set of channel estimates for a plurality of subcarriers of a received signal. The processing module is configured to generate a second set of channel estimates for the plurality of subcarriers, in which the second set of channel estimates are generated based on the first set of channel estimates. The control module is configured to estimate a preamble sequence in the received signal based on each of (i) the first set of channel estimates and (ii) the second set of channel estimates.

Abstract: A dynamic level shifter is disclosed. In one embodiment, a dynamic level shifter circuit may receive an input signal referenced to a first voltage of a first power domain, and may output a corresponding signal referenced to a second voltage into a second power domain. The dynamic level shifter circuit may include an evaluation node that is precharged during a first phase (e.g., the low portion) of a clock signal. During the second phase (e.g., the high portion) of the clock signal, the evaluation node may be either pulled low or high, depending on the state of the input signal. A corresponding output signal, based on the evaluated level on the evaluation node, may be output into the second power domain.

Abstract: The invention concerns a circuit comprising: a first circuit block (302) adapted to receive a first clock signal (CLK1) and to provide a first output data signal at a time determined by said first clock signal; a second circuit block (304) adapted to receive a second clock signal (CLK2) and to provide a second output data signal at a time determined by said second clock signal; a clock bus (314) coupled to corresponding outputs of said first and second circuit blocks for receiving a third clock signal (BCLK) based on said first and second clock signals; and a synchronization unit (312) coupled to said clock bus and adapted to sample said first and second output data signals based on said third clock signal.

Abstract: A data transfer system which can surely transfer data between two function circuits which operate synchronously with different clock frequencies. A data loading signal is generated just before timing when edges of two clocks of different frequencies coincide. Only information data received by the function circuit on a transfer data reception side within an existence period of the data loading signal is determined to be valid.

Abstract: A control circuit arrangement for pulse-width modulated DC/DC converters includes a phase generator for a complementary driver which provides respective gate signals to a first and second driver transistor in response to a control signal. A clock control circuit receives a clock signal and a pulse-width modulated signal and provides the control signal in response to a signal edge of the pulse-width modulated signal and the clock signal applied thereto. A mode selection input terminal receives a mode selection signal to select a first mode or a second mode of operation. The phase generator provides in the first mode each of the gate signals the control signal and the respective other gate signal. In the second mode of operation, it provides each gate signal in response to the control signal.

Abstract: A bit synchronization method is proposed. The method includes buffering a plurality of samples from a signal stream, scanning the buffered samples for transitions and updating a zero-crossing histogram buffer upon detection of the transitions. The method further includes detecting at least two peaks simultaneously from the updated zero-crossing histogram buffer, fixing at least two boundaries from the detected peaks, and integrating the buffered samples within the boundaries. Finally the method includes generating an output signal comprising a synchronized bit stream from the integrated samples.

Abstract: A comparison period determiner (110) detects whether or not a change occurs in received data during a comparison period including a timing at which a rising edge of a reference clock occurs. A phase determiner (120) determines whether a rising edge of the received data is located before or after the reference clock and determines whether a falling edge of the received data is located before or after the reference clock, and outputs a first determination signal and a second determination signal indicating results of the respective determinations. A synchronous data generator (130) outputs a signal having a level depending on a result of the detection by the comparison period determiner (110) and an output of the phase determiner (120), as synchronous data, in synchronization with a synchronization clock.

Abstract: An information processing device includes: a signal receiving portion that receives a signal in which input data that contains first and second bit values different from one another is encoded such that the first bit value is expressed by first amplitude values and the second bit value is expressed by second amplitude values different from the first amplitude values, and such that the same amplitude value does not occur twice in succession and the polarities of the amplitude values are inverted with each cycle; a clock signal extraction portion that extracts a clock signal by detecting polarity inversions in the received signal; a clock signal subtraction portion that subtracts the extracted clock signal from the received signal; and an input data decoding portion that decodes the input data by determining the first and second bit values based on an amplitude value of the signal obtained by subtracting the clock signal.

Abstract: An oscillation detector having an RF oscillator configured to be synchronized with a first frequency and a comparator for distinguishing the synchronized state from the non-synchronized state of the radiofrequency oscillator on the basis of an oscillating signal produced by the radiofrequency oscillator and indicating the presence of oscillations in a frequency band around the first frequency in response to identifying the synchronized state and, in alternation, indicating the absence of oscillations in this frequency band otherwise.

Abstract: An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals.

Abstract: Some embodiments disclosed herein relate to a method. In the method, a duration of a first synchronization pulse is measured. A fixed, predetermined number of ticks are equally spaced at a first time interval over the first sync pulse, regardless of the duration of the first synchronization pulse. A duration of a first data pulse is then measured by periodically incrementing a tick count value at the first time interval during the entire duration of the first data pulse. The tick count value at an end of the first data pulse is then correlated to a first digital value encoded on the first data pulse.

Abstract: A signal reception device is disclosed that is capable of detecting symbol synchronization timing with high precision in accordance with a condition of a propagation path even in an environment involving multi-path interference. The signal reception device adopts an OFCDM transmission scheme or a multi-carrier transmission scheme. The signal reception device includes a received signal information calculation unit to calculate received signal information representing a signal reception condition of a received signal; an output combination unit to combine correlation values in a predetermined section obtained by correlation detection based on the received signal information; and a symbol timing detection unit to detect a symbol synchronization timing based on the combined value.

Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.

Abstract: A burst mode receiver including a CDR circuit that does not perform bit synchronization determination at a wrong position even when a burst signal waveform containing a distortion is input is provided. The burst mode receiver includes a CDR circuit for reproducing clock and data from a received signal, a bit synchronization determination circuit for determining whether the CDR circuit is in an optimum phase, a waveform distortion determination circuit for determining from the received signal whether there is waveform distortion, and a CDR output enable determination circuit for determining whether an output of the CDR circuit is valid or invalid. The CDR output enable determination circuit performs CDR output enable determination based on a bit synchronization determination result and a waveform distortion determination result.

Abstract: An apparatus configured for built in self test (BIST) jitter measurement is described. The apparatus includes a time-to-voltage converter. The time-to-voltage converter generates a voltage signal proportional to timing jitter present in a clock/data signal input. The apparatus also includes feedback circuitry for the time-to-voltage converter. The feedback circuitry provides a ramp slope for the time-to-voltage converter. The apparatus further includes a calibration controller. The calibration controller provides control signals to the time-to-voltage converter for process-independent calibration. The apparatus also includes a sample-and-hold (S/H) circuit. The S/H circuit provides a set bias voltage to the time-to-voltage converter once calibration is complete.

Abstract: A system, method, and computer program product are provided for the switching of clock signals. A clock network switching system includes a first re-synchronization circuit coupled to a first input clock, and a second re-synchronization circuit coupled to a second input clock. There is also an input select decoder coupled to the first and second re-synchronization circuit that can dynamically select either the first or the second input clock to be active. When an input clock is selected to be active, the re-synchronization circuit associated with the selected input clock generates an output clock synchronized with the selected input clock where both a high pulse width and a low pulse width of the output clock are not less than those of the selected input clock.

Abstract: Provided are: plural circuit components including a circuit component which constitutes a receiving unit receiving a signal sequence which is arranged so that a desired signal and a signal different from the desired signal are lined up in time series, the desired signal indicating desired data which includes at least one of text data, sound data, image data, and a computer program product; and an operating parameter changing unit which changes an operating parameter of at least one of the plural circuit components, during a period in which the receiving unit receives the signal different from the desired signal.

Abstract: The disclosed embodiments relate to buffer circuits and methods. One embodiment is a buffer circuit that receives a data signal, a first clock signal and a second clock signal, the buffer circuit comprising circuitry to latch the data signal with the first clock signal to produce a first latched signal, circuitry to latch the data signal with the second clock signal to produce a second latched signal, and circuitry that selects the first latched signal or the second latched signal depending on a transition of the data signal in a previous clock cycle.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: A voltage sequence output circuit includes input terminals of a NOR gate connected to first and second input terminals. An output terminal of the NOR gate connected to a first terminal of a first electrical switch. A third terminal of the first electrical switch connected to a power source. A first terminal of a second electrical switch connected to the first input terminal and the power source through a first resistor. A second terminal of the second electrical switch connected to a second terminal of the first electrical switch. A third terminal of the second electrical switch connected to a first output terminal and a second terminal of a third electrical switch. A first terminal of the third electrical switch connected to a second input terminal and the power source through a second resistor. A third terminal of the third electrical switch connected to a second output terminal.

Abstract: An integrated circuit includes a counter configured to perform a counting operation and output a count code value. The integrated circuit further includes an operation controller, a digital circuit and an alignment unit. The operation controller receives the count code value and generates a first control signal and a second control signal. The first control signal is generated, when the count code value is equal to a first value, which is counted by the counter prior to a target count value. The second control signal is generated, when the count code value is equal to the target count value. A digital circuit performs a first operation based on the first control signal, and output a digital signal. An alignment unit aligns the digital signal, and outputs the aligned digital signal as a final digital signal in response to the second control signal.

Abstract: An apparatus for transferring data in a non-spread domain to a spread domain. The apparatus comprises a first-in-first-out (FIFO) memory; a write pointer generator adapted to generate a write pointer for writing data into the FIFO memory in response to a non-spread clock signal; a spread-clock generator adapted to generate a spread clock signal based on the non-spread clock signal; a read pointer generator adapted to generate a read pointer for reading data from the FIFO memory in response to the spread clock signal; and a controller adapted to control the spread-clock generator in response to the read and write pointers indicating predetermined potential data overflow or underflow of the FIFO memory.

Abstract: A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (which, in turn, is derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal advances onset of the PHEQ (phase equalization) phase and is used to terminate the ForceSL and On1x modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during On1x exit.

Abstract: A circuit and method of applying a three phase power source to a load such that each phase is applied to the load in a manner, such as a predetermined sequence, so as to reduce the electromagnetic interference (EMI) and heat generated in the switching devices during the application and removal of each phase to the load.