Abstract: Systems and methods for generating clock signals using analog recursion are provided. In some embodiments, an analog recursion system includes an analog recursion device and one or more recursion loops. The recursion loops interact to form periodic phenomena within the analog recursion device, which may be sampled to generate clock state. By tuning settings of the analog recursion device, the clock state generated by the analog recursion system may be tailored for a variety of purposes.

Abstract: The present invention relates to the communication field and discloses a method and an apparatus for implementing pulse synchronization, so that the control on a single-chip multi-channel device can be simplified. A method for implementing pulse synchronization includes: when a cycle count value corresponding to a reference symbol port of the multiple ports reaches a length of a predetermined pulse cycle, obtaining, by a microprocessor, cycle count values corresponding to the multiple ports; obtaining lengths of temporary synchronization cycles of the multiple ports according to the length of the predetermined pulse cycle and the cycle count values corresponding to the multiple ports; and sending the lengths of the temporary synchronization cycles to logic circuits corresponding to the multiple ports. Embodiments of the present invention are mainly applied in communication systems to output pulse symbols synchronously.

Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.

Abstract: An interface circuit includes an input/output terminal, a clock generator, a set of multiple data ports, and a data port selector. The input/output terminal is connected to the external circuit to receive a data signal. The clock generator generates a series of multiple phase-shifted clock signals based on a basic clock signal. Each of the multiple data ports is connected to the input/output terminal and the clock generator to receive the data signal in synchronization with an associated one of the multiple phase-shifted clock signals to output a latched data signal. The data port selector is connected to the multiple data ports to check the multiple latched data signals to select one of the multiple data ports. The interface circuit loads the data signal through the selected data port in synchronization with the associated one of the multiple phase-shifted clock signals.

Abstract: System and method for signal synchronization. The system includes a first selection component, a first signal generator, a second signal generator and a first gate drive component. The first selection component is configured to receive a first mode signal and generate a first selection signal based on at least information associated with the first mode signal. The first signal generator is configured to, if the first selection signal satisfies one or more first conditions, receive a first input signal and generate at least a first clock signal based on at least information associated with the first input signal. Furthermore, the first gate drive component is configured to, if the first selection signal satisfies the one or more first conditions, receive at least the first clock signal and output a first drive signal to a first switch.

Abstract: A synchronized pulsing arrangement for providing at least two synchronized pulsing RF signals to a plasma processing chamber of a plasma processing system is provided. The arrangement includes a first RF generator for providing a first RF signal. The first RF signal is provided to the plasma processing chamber to energize a plasma therein, the first RF signal representing a pulsing RF signal. The arrangement also includes a second RF generator for providing a second RF signal to the plasma processing chamber. The second RF generator has a sensor subsystem for detecting values of at least one parameter associated with the plasma processing chamber that reflects whether the first RF signal is pulsed high or pulsed low and a pulse controlling subsystem for pulsing the second RF signal responsive to the detecting the values of at least one parameter.

Abstract: A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: The invention provides a receiver comprising a data input and a strobe input. The strobe signal transitions whenever two consecutive bits in the data signal are the same. The receiver comprises combining means for generating a recovered clock signal from a combination of the data and strobe signals. The receiver also comprises a first sampling stage arranged to sample the data signal in dependence on the recovered clock signal, the first sampling stage comprising a plurality of sampling circuits and being arranged to obtain consecutive samples of the data signal using alternating ones of the sampling circuits. A second sampling stage is arranged to sample the data from the first sampling stage in dependence on a local system clock signal.

Abstract: Provided is a test apparatus and a test method for substantially synchronizing phases of test signals for each of a plurality of clock domains. The test apparatus tests a device under test including a plurality of clock domains.

Abstract: A count value generator includes an input for receiving a synchronizing count value, a counter configured to increment at a local frequency, the local frequency being faster than the synchronizing frequency, and an interpolator for determining a frequency ratio between the local frequency and the synchronizing frequency and for determining an increment value for the counter dependent on a relative amount of a maximum value of the counter with respect to the frequency ratio is disclosed. The counter generates a count value including a predetermined number of bits representing integer values and output as the lower order bits of the output count value and additional lower order bits that represent fractional portions of the integer values. The counter includes output circuitry for outputting the synchronizing count value and the predetermined number of bits representing integer values generated by the counter as the lower order bits of the count value.

Abstract: One clock generator includes an oscillator block, a delay circuit, and an output block. The oscillator block provides a first clock of multiple phases. The delay circuit delays at least one of said multiple phases of said first clock to generate a second clock of multiple phases. The output block generates a third clock by selecting signals from said multiple phases of said second clock, wherein said third clock has non-harmonic relationship with said first clock. Another exemplary clock generator includes an oscillator block and an output block. The oscillator block includes an oscillator arranged to provide a first clock, and a delay locked loop arranged to generate a second clock according to said first clock. The output block generates a third clock by selecting signals from said multiple phases, wherein said third clock has non-harmonic relationship with said first clock.

Abstract: A system and method for synchronizing asynchronous input signals with reliability. Each of a first and a second storage element in a synchronizer receives a first clock signal in a first clock domain. The second storage element may also receive a first reset signal generated by a second clock signal in the first clock domain different from the first clock signal. The first storage element receives a combination of an asynchronous data input signal and the first reset signal. The data input signal may be generated from circuitry utilizing a second clock domain different from the first clock domain. The second storage element additionally receives an output of a second combination of a stored output value of the first storage element and a second reset signal generated from the first clock signal. The second storage element stores a stable output value based at least on the asynchronous data input signal.

Abstract: A semiconductor device according to one aspect of the present invention includes: a flip-flop; a clock control circuit that controls a clock signal supplied to the flip-flop; and a controller that supplies a data retention signal to the flip-flop and controls the clock control circuit. When the flip-flop is driven by a negative edge of the clock signal and retains data when the clock signal is at a high level, the controller controls the clock control circuit so as to supply a high-level clock signal to the flip-flop after the input clock signal is fixed and before the flip-flop retains data. This prevents the occurrence of unintended latching of data when the flip-flop having a retention function retains data.

Abstract: A system for synchronizing a first clock and a second clock includes a receiver associated with the first clock, configured to receive a remote pulse from the second clock. The remote pulse has a pulse repetition frequency and spectral characteristics that are known to the local clock. The system also includes a local pulse emitter configured to create a local pulse at the first clock, and optics configured to align the local pulse and the remote pulse. The system further includes an interferometer configured to create an interference pattern between the local pulse and the remote pulse. A controller is provided that is configured to calculate a time delay between the first clock and the second clock based on the interference pattern between the local pulse and the remote pulse.

Abstract: A semiconductor integrated circuit includes: a plurality of chips configured to receive an external voltage. Each one of the chips detects a signal delay characteristic of the one of the chips to generate an internal voltage having a level corresponding to the signal delay characteristic.

Abstract: A delay circuit generates an internal clock signal or a second clock signal by delaying an external clock signal. A detection-potential generation circuit included in a phase-difference determination circuit generates a detection potential corresponding to a difference between a timing of an active edge of an internal clock signal or a third clock signal and a timing of the target external clock signal in a first node. A reference-potential generation circuit included in the phase-difference determination circuit generates a reference potential in a second node. A phase control circuit delays the second clock signal according to the detection potential. At this time, when the detection potential is higher than the reference potential, an adjustment amount of the second clock signal per adjustment changes.

Abstract: A semiconductor device includes: a clock input unit configured to receive a system clock and a data clock externally; a phase dividing unit configured to generate a plurality of multi-system clocks in response to the system clock, wherein each of the multi-system clocks has an individual phase difference; a phase detecting unit configured to detect phase differences between the plurality of multi-system clock and the data clock and to generating generate a training information signal in response to the detection result; and a signal transmitting unit configured to transmit the training information signal.

Abstract: A signal output circuit includes a signal transfer unit configured to transfer a signal of a first line to a pull-up line during an activation period of a first clock, transfer the signal of the first line to a pull-down line during a deactivation period of a second clock, transfer a signal of a second line to the pull-up line during a deactivation period of the first clock, and transfer the signal of the second line to the pull-down line during an activation period of the second clock; and an output driving unit configured to pull-up drive an output node in response to a signal of the pull-up line and pull-down drive the output node in response to a signal of the pull-down line, wherein the first clock and the second clock have the activation periods longer than the deactivation periods.

Abstract: Systems and methods for fine symbol timing estimation are disclosed herein. In one embodiment, a wireless receiver includes a differential detector, a correlator, a coarse symbol timing estimator, and a fine symbol timing estimator. The differential detector is configured to detect phase differences in a received preamble signal modulated using differential phase shift keying. The correlator is configured to correlate symbol values output by the differential detector against a reference sequence. The coarse symbol timing estimator is configured to generate a coarse symbol timing estimate, and to generate a coarse timing sample symbol index value corresponding to the coarse symbol timing estimate. The fine symbol timing estimator is configured to generate a fine symbol timing estimate that is more accurate than the coarse symbol timing estimate based on the coarse timing sample symbol index value and correlation samples at index values preceding and succeeding the coarse timing sample index value.

Abstract: An operational amplifier circuit is provided. The operational amplifier circuit includes a differential amplifier of a cascade structure and a switched-capacitor type Common-Mode FeedBack (CMFB) circuit. The differential amplifier amplifies a difference between two input signals to output an anode output voltage and a negative output voltage. The switched-capacitor type CMFB circuit averages the anode output voltage and the negative output voltage of the differential amplifier, compares the average voltage with a reference voltage to generate a feedback signal based on a result of the comparison, and provides the feedback signal to the differential amplifier. Therefore, power consumption is reduced and a battery use time of a wireless terminal can be extended. Also, since an operational amplifier gain of each analog filter terminal is not negatively affected, a Direct Current (DC) offset is reduced, thereby improving signal quality.

Abstract: During operation of the device, a drive circuit may provide a drive signal having a fundamental frequency to two electrothermal filters (ETFs) having different temperature-dependent time constants. In response to the drive signal, the two ETFs may provide, signals having the fundamental frequency and phases relative to the drive signal corresponding, respectively, to the time constants of the ETFs. Then, phase-shift values of the phases may be measured using a phase detector, and a signal may be output based on the phase-shift values. Note that the signal may correspond to a value that is a function of a temperature of the device.

Abstract: According to an aspect of the present invention, one of multiple clock signals of different relative phases is selected based on a desired delay magnitude, and the digital values received on an input signal are then synchronized to an edge (“first edge”) of the selected clock signal to provide the digital values with the desired delay magnitude. In an embodiment, the selected clock signal can be delayed by a fine value (less than the minimum phase difference of the multiple clock signals) to provide a wide span of desired delays. An aspect of the invention provides for a synchronization circuit with reduced latency and which is substantially invariant to process, voltage and temperature (PVT) changes.

Abstract: A voltage controlled oscillation circuit oscillates at an oscillation frequency corresponding to a control voltage. Injection locked oscillation circuits oscillate at an oscillation frequency corresponding to an output signal from the voltage controlled oscillation circuit. A mixer circuit performs a frequency conversion based on output signals from the injection locked oscillation circuits. A synchronization determiner determines the synchronous status between the injection locked oscillation circuits in accordance with an output signal from the mixer circuit. The injection locked oscillation circuits synchronize with each other at a frequency that is an integral multiple of the oscillation frequency of the voltage controlled oscillation circuit.

Abstract: Disclosed are method and circuit for synchronizing input and output synchronization signals, which can synchronize an output synchronization signal based on frequency change of an input synchronization signal and limit input and output periods, thereby preventing flickering, a backlight driver of a liquid crystal display device using the same, and a method for driving the backlight driver. The method for synchronizing input and output synchronization signals, includes generating an output synchronization signal whose output period is set based on a comparison result between an input period of an input synchronization signal and a previous output period of the output synchronization signal, and limiting the output period of the output synchronization signal within a predefined limit range from the previous output period.

Abstract: In a multiphase electrical power assignment, a processor: receives instructions to connect a bi-directional power device to a multiphase premise power source; determines that the power device is to be coupled to a target phase's phase connection; confirms that the power device is not coupled to any phase connections; and couples the power device to the phase connection, where the power device's power signal is synchronized with the phase connection's power signal. When the power device is in a connected state, the processor: issues a command to place each phase connection switch in an open state; in response to confirming that the phase connection switches are in the open state, issues commands to the power device so that a power signal of the power device will be synchronized with the target phase; and closes the phase connection switch corresponding to the target phase.

Abstract: The disclosed embodiments provide a synchronizer latch circuit that facilitates resolving metastability issues. This synchronizer latch circuit includes a set of lightly loaded, cross-coupled transistors that form a metastable resolving and state-holding element that is coupled to two outputs. An incoming synchronization signal creates a voltage difference between the two outputs, but does not directly force a state change for the outputs. Instead, the data and clock inputs control transistors that allow neighboring power sources and/or ground network connections to weakly influence the outputs. The cross-coupled transistors then amplify the resulting voltage difference to generate valid output voltages, even when the data input and clock signal are received at roughly the same time. Thus, the synchronizer latch circuit facilitates rapidly resolving metastability and improving synchronizer performance.

Abstract: A second latch latches the output data of a first latch using a third clock having the same frequency as that of a first clock. A third latch latches the output data of the second latch using a second clock having a frequency N (N represents an integer) times that of the first clock and the third clock. The second clock and the third clock have a frequency division/multiplication relation therebetween.

Abstract: The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.

Abstract: Disclosed is a method and apparatus for clock checking, to solve the problem of high resource occupation in existing clock checking methods. The method includes: a programmable device for performing frequency division on the source clock signal to obtain a reference clock signal; treating the source clock signal as a counting work clock to determine the counting value of rising edges and counting value of high levels of a clock signal being checked during each high level period out of N continuous high levels of the reference clock signal; and determining whether the clock signal being checked is valid according to the magnitude relationship between the counting value of the high levels of the clock signal being checked during each high level period and a first expected value, as well as the magnitude relationship between the counting value of the rising edges and a second expected value.

Abstract: Systems and methods for generating control signal in radiation detector systems are provided. One system includes a scheduling architecture having at least one anode channel connected to a detector of the radiation detector system. The anode channel includes a charge sensitive amplifier and a signal shaper, wherein the anode channel is configured to generate at least one control signal to control data acquisition by the detector. The scheduling architecture also includes at least one shaper timer configured having a time constant to define timing for the generation of the control signal without using a clock.

Abstract: A data output circuit of a semiconductor apparatus includes a clock skew compensation repeater configured to control a delay amount of a clock in response to skew compensation codes and output a data synchronization clock; a mismatch compensation driver configured to synchronize internal data with the data synchronization clock and output the internal data synchronized with the data synchronization clock by controlling a transition timing of the internal data according to mismatch compensation codes; and a data output driver configured to generate output data in response to an output of the mismatch compensation driver.

Abstract: In an embodiment, a device includes a buffer circuit with first and second buffer outputs and a latency locked loop (LLL) circuit. The LLL circuit includes first and second LLL inputs for receiving first and second input signals and includes at least one shared component that is time shared. The at least one shared component is configured to measure edge timing errors in output signals on the first and second buffer outputs relative to the first and second inputs signals and to generate delay adjustment signals to adjust timing of edge transitions within the first and second input signals provided to the buffer circuit to control a total propagation delay from the first and second LLL inputs to the first and second buffer outputs.

Abstract: An analog front end (AFE) device has at least one programmable analog-to-digital converter (ADC) and a serial interface switchable to operate in a bidirectional serial interface mode and in a unidirectional two wire serial interface mode, wherein the unidirectional two wire serial interface mode only uses a clock input and a data output signal line, wherein the ADC operates in the unidirectional two wire serial interface mode synchronous with a clock supplied to the clock input.

Abstract: A timing generator that outputs a timing signal obtained by delaying an input signal, comprising first and second period delay sections that each output a rate signal obtained by delaying the input signal by a delay amount corresponding to an integer multiple of a period of an operation clock supplied thereto; a first high-accuracy delay section that outputs the timing signal obtained by delaying a signal input thereto by a delay amount that is less than the period of the operation clock; and a mode switching section that switches between a low-speed mode, in which the rate signal output by the first period delay section is input to the first high-accuracy delay section, and a high-speed mode, in which a signal obtained by interleaving the rate signals output by the first period delay section and the second period delay section is input to the first high-accuracy delay section.

Abstract: A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal.

Abstract: An exemplary calibration apparatus includes a detecting circuit and a calibrating circuit. The detecting circuit is arranged for generating a detection result by detecting relationship between edges of a plurality of signals generated from a plurality of signal sources, wherein at least one of the edges is a falling edge. The calibrating circuit is coupled to the detecting circuit, and arranged for calibrating at least one of the signal sources according to the detection result. An exemplary calibration method includes the following steps: generating a detection result by detecting relationship between edges of a plurality of signals generated from a plurality of signal sources, wherein at least one of the edges is a falling edge; and calibrating at least one of the signal sources according to the detection result.

Abstract: A method and system of fine timing synchronization for an OFDM signal. The OFDM signal is coarse timing synchronized, generating a synchronization sequence and a CFR (Channel Frequency Response). The synchronization sequence is removed. A correlation coefficient of the correlation between the CFR applied to a number of carriers and the number of carriers with different window shifts is calculated. The largest window shift corresponding to a downsampling factor is indicated by the lowest correlation coefficient greater than a threshold. The CFR is downsampled by the downsampling factor, and an inverse FFT is performed on the downsampled CFR with a reduced number of calculations reduced by the downsampling factor, transforming the CFR into a CIR. A fine timing synchronization position is determined from the CIR and is utilized by an FFT unit within an OFDM receiver to accurately receive OFDM symbols of the OFDM signal.

Abstract: A synthesizer comprises a first processing unit that receives digital information relating to a required final frequency of the synthesizer and determines a primary frequency value and a corresponding frequency multiplier mode. A primary synthesizer receives the primary frequency value and an external reference frequency signal to generate a signal of the primary frequency. The synthesizer further comprises a second processing unit that receives the primary frequency value, determines a pre-charge voltage value corresponding to the primary frequency value, and transmits the pre-charge voltage value to a delay locked loop in response to a change in the primary frequency value. The delay locked loop receives the signal of primary frequency and the pre-charge value. The DLL is pre-charged to the pre-charge voltage value for a predetermined time, by opening and closing the delay locked loop to obtain fast locking of the synthesizer.

Abstract: A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.

Abstract: A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second clock signal using the first clock signal; detecting coincident edges of the first and the second clock signals; and changing the second frequency to a third frequency different from the second frequency upon detection of the coincident edges.

Abstract: The embodiment of the present disclosure discloses a method and apparatus for detecting frequency deviation of a clock. The method includes: counting the clock to be detected to acquire current counting information; filtering the current counting information to acquire filtered data; and acquiring the frequency deviation of the clock to be detected from the filtered data. According to the embodiments of the present disclosure, the detection accuracy of frequency deviation is improved by filtering the counting information acquired by counting the clock to be detected, and appropriately increasing an amount of information after the filtering, so as to perceive the occurrence of any abnormal dithering, and avoid neglecting of any abnormal condition in periodic or aperiodic queries.

Abstract: In a method of modulating/demodulating a signal, a transmission signal is generated from an input data signal including data information by combining a plurality of input shift clock signals, which are modulated based on input clock signal during an interval period of the input clock signal, during 2 interval periods of the input clock signal. An output clock signal is detected and an output clock signal is generated from the transmission signal by combining a plurality of output shift clock signals, demodulated based on the output clock signal during an interval period of the output clock, during 2 interval periods of the output clock signal, to restore the data information.

Abstract: A complex acquisition system and method for synchronizing components thereof. The complex acquisition system further including a master acquisition module. The master acquisition module further including an analog to digital acquisition signal generator for generating an analog to digital acquisition signal, a memory acquisition signal generator for generating a memory acquisition signal, a delay calibration signal for generating a delay calibration signal, a step source signal generator for generating a step source signal, and a synchronization module. The complex acquisition system further includes a plurality of slave acquisition modules, each also including a synchronization module. The complex acquisition system additionally includes a distribution system for distributing each of the analog to digital acquisition signal, memory acquisition signal, delay calibration signal and step source signal to each of the synchronization modules in the master and plurality of slave acquisition modules.

Abstract: A communication device includes a current information storage unit 130 that stores the bit boundary signal at each of timings at which a sampling clock is updated, a past information storage unit 140 that takes in and stores a signal stored in the current information storage unit 130 when a variation point of a reception signal is detected, and does not update a signal stored therein when no variation point of the reception signal is detected, and a clock selection unit 44 that selects CLKSEL2 used for the sampling of the reception signal from N-phase clocks based on a signal stored in the current information storage unit 130 when a variation point of the reception signal is detected, and selects CLKSEL3 based on a signal stored in the past information storage unit 140 when no variation point of the reception signal is detected.

Abstract: A delay circuit includes at least a delay stage. The delay stage includes an inverting receiver, a capacitive element, an output inverter, and a feedback transistor. The inverting receiver includes a resistive element. An input node of the inverting receiver receives an input signal, and the resistive element is coupled to an output node and an internal node of the inverting receiver. A capacitive element is coupled to the output node of the inverting receiver. An input node of the output inverter is coupled to the output node of the inverting receiver, and an output node of the output inverter outputs an output signal of the delay stage. The feedback transistor is coupled between the output node and the input node of output inverter, such that the feedback transistor compensates a delay time of the inverting receiver as at least one of a process, a supply-voltage, and a temperature varies.

Abstract: A system for synchronizing the operation of a circuit with a control signal includes synchronization flip-flops operating in cascade for receiving a control signal to be synchronized and providing a corresponding control signal synchronized with a clock signal, and a circuit including a finite state machine for receiving the clock signal having state flip-flops for storing the current state of the finite state machine, wherein a last synchronization flip-flop includes one of the state flip-flops.

Abstract: Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. Another example method includes providing an output clock signal in phase with an input clock signal and compensating for delay error between delays used in providing at least some of the delay of the output clock signal relative to the input clock signal by providing delays having power supply sensitivities resulting in a combined power supply sensitivity that is inverse to the delay error.

Abstract: There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.

Abstract: There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.