Abstract: Disclosed is a multi-phase clock signal generation circuit including two circuit blocks, each of which includes a cross-coupled structure and two delay units, and the delay units are adjustable. One circuit block (MD1) includes two NMOS transistors, two PMOS transistors, and two delay units, and the other circuit block (MD2) may include two NMOS transistors, two PMOS transistors, and two delay units. The circuit can generate clock signals with respective phases whose relationship is relatively independent of integration process, operating voltage and temperature, thereby allowing guaranteed efficiency for a multi-phase charge pump.

Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.

Abstract: A pulsed latching apparatus and a method for generating a pulse signal are provided. The pulsed latching apparatus consists of a pulsed latch and a pulse signal generator. A data input terminal of the pulsed latch receives input data, the pulsed latch latches the input data according to a pulse signal, and transmits the latched input data through the data output terminal to serve as output data. The pulse signal generator duplicates a data transmission delay between the data input terminal and the data output terminal of the pulsed latch to obtain a duplicated delay. The pulse signal generator receives a clock signal, and processes the clock signal according to the duplicated delay to generate the pulse signal.

Abstract: A PWM signal generation circuit according to the present invention includes a duty setting unit (10) configured to generate a duty control signal designating a duty ratio corresponding to each period of a PWM signal on the basis of an initial duty setting signal, a target duty setting signal, a slope setting signal, and a clock signal, a period setting unit (20) configured to output a period setting value, and an output control unit (30) configured to generate the PWM signal having a period corresponding to the period setting value and having a duty ratio corresponding to a value of the duty control signal. The duty setting unit (10) increases the value of the initial duty ratio to the value of the target duty ratio each time the number of a clock pulse of the clock signal reaches the period setting value reaches the slope setting value.

Abstract: A period signal generation circuit includes a first buffer unit suitable for buffering a buffer signal and output an output signal; and a second buffer unit suitable for buffering the output signal and output a period signal, wherein each of the first and second buffer units includes a resistor element coupled between a body of a metal oxide semiconductor (MOS) transistor and a source.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: In one embodiment, an audio processing system includes a frequency control block that forms a system clock and a master audio clock. The frequency control block is configured to change a frequency of the system clock and change a relationship between the system clock and the master audio clock so that the frequency of the master audio clock remains substantially constant.

Abstract: Clock alignment circuitry may include phase comparator circuitry with a first input terminal that receives as first clock signal from a first clock tree and a second input terminal that receives a second clock signal from a second clock tree. The phase comparator circuitry may compare the first and second clock signals and generate different control signals based on the first and second clock signals. The integrated circuit may further include phase interpolator circuitry that generates an output clock signal based on at least one of the control signals received from the phase comparator circuitry. Edges of the generated output clock signal may align with edges of either the first clock signal or the second clock signal.

Abstract: A receiver for decoding a communication signal is disclosed. The receiver includes an input port and a filter. The input port receives the communication signal from a communication medium. The communication signal comprises a sequence of symbols. Each symbol of the symbol sequence is an analog pulse that has a leading edge of exponential shape. The exponential shape has an exponential growth parameter value that has been selected from values ?0 and ?1, which are distinct positive values. For each symbol of the symbol sequence, the exponential growth parameter value for the leading edge of the symbol has been selected based on a corresponding bit from a stream of information bits. The filter receives the communication signal from the input port and filters the communication signal to obtain an output signal. The transfer function of the filter has one or more zeros at ?0.

Abstract: The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.

Abstract: An apparatus comprising a delay circuit and a control circuit. The delay circuit may be configured to generate a plurality of intermediate signals in response to (i) a clock signal and (ii) an adjustment signal. The control circuit may be configured to generate the adjustment signal and a plurality of output signals having a quarter-cycle interval in response to (i) the plurality of intermediate signals and (ii) the clock signal.

Abstract: A method and apparatus for atomic frequency and voltage changes in the processor. In one embodiment of the invention, the atomic frequency and voltage changes in the processor is feasible due to the enabling technology of fully integrated voltage regulators (FIVR) that are integrated in the processor. FIVR allows independent configuration of each core in the processor and the configuration includes, but is not limited to, voltage setting, frequency setting, clock setting and other parameters that affects the power consumption of each core.

Abstract: A signal transmission/reception system includes a transmission line, a signal transmission circuit configured to generate a transfer signal and transfer the transfer signal through the transmission line, wherein a logic value of the transfer signal is changed whenever a pulse signal is input to the signal transmission circuit, and a signal reception circuit configured to receive the transfer signal through the transmission line and generate a restoration signal using the transfer signal and a delayed transfer signal obtained by delaying the transfer signal.

Abstract: There is provided an oscillation frequency regulating circuit including: a measuring section that performs measurement based on an oscillation frequency of an oscillation circuit; a comparator section that compares a measurement value measured by the measuring section against a set comparison value over a set comparison duration; a setting section that sets a comparison value selected from a plurality of comparison values of different magnitudes and that sets in the comparator section the comparison duration according to the magnitude of the selected comparison value; and a regulation section that, based on the comparison result of the comparator section, regulates the oscillation frequency of the oscillation circuit such that the oscillation frequency that is measured by the measuring section becomes a target oscillation frequency.

Abstract: The semiconductor device includes an internal clock generator, a shift signal generator and a first control signal generator. The internal clock generator generates a first internal clock signal and a second internal clock signal in response to an external clock signal. The shift signal generator shifts a clock enable signal in response to the first internal clock signal to generate first and second shift signals, and the shift signal generator shifts the clock enable signal in response to the second internal clock signal to generate third and fourth shift signals. The first control signal generator generates a first control signal in response to the first and third shift signals.

Abstract: A multi-stage phase mixer circuit includes: a first phase mixer configured to receive first and second input clock signals and output a first intermediate clock signal according to control of a first coarse control signal; a second phase mixer configured to receive the first and second input clock signals and output a second intermediate clock signal according to control of a second coarse control signal; and a third phase mixer configured to receive the first and second intermediate clock signals and output an output clock signal according to control of a fine control signal.

Abstract: Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.

Abstract: Parallel/serial conversion is performed on an N (where N is a natural number)-bit first parallel data signal with a first converted clock acquired by multiplying a reference clock by N, and parallel/serial conversion is performed on an (N×K)-bit (where K is a natural number) second parallel data signal with a second converted clock acquired by multiplying the reference clock by N×K.

Abstract: In an embodiment, a circuit configured for asymmetric ageing prevention in an integrated circuit (IC) comprises a primary clock configured to generate a primary clock signal, a secondary clock configured to generate a secondary clock signal, a state determination circuit, and a control circuit. The state determination circuit is configured to determine a current operating state associated with at least one of a primary clock condition and a power-on-reset condition in the IC. The control circuit is configured to generate a control signal in response to a determination of an first operating state. The control signal is configured to facilitate a transition from the primary clock to the secondary clock upon determination of the first operating state, and a transition from a safe operating mode to a normal operating mode upon determination of a second operating state. The secondary clock is associated with a safe operating mode of the IC.

Abstract: A clock trimming apparatus includes an oscillator, a judging unit, a latching unit, and a tracking unit. The oscillator has an input terminal receiving a bias signal and an output terminal generating a clock signal. After a frequency division is performed on the clock signal, the judging unit generates a frequency-divided signal. If the frequency-divided signal matches the reference signal, a pass signal generated by the judging unit is activated. The latching unit is used for generating a trimming completion signal. After the pass signal is activated, the trimming completion signal is activated. The tracking unit is used for counting a pulse number of the reference signal and providing the bias signal to the oscillator according to a trimming code. After the trimming completion signal is activated, the trimming code is stopped being adjusted.

Abstract: A clock generator circuit for producing a clock output having a controlled duty cycle is disclosed. A bi-stable circuit provides the clock output which is switchable to a first state in response to an edge of the input clock signal and to a second state in response to a feedback signal. A duty cycle detection circuit is configured to source a current to a node and to sink a current from the node depending upon the output clock state. A capacitor is connected to receive a duty cycle current relating to the current at the node, with a comparator circuit being configured to sense a voltage on the capacitor and to produce the feedback signal when the voltage is at a selected level.

Abstract: A phase shift is defined as a point in frequency at which the phase is changed from 0 degrees to 180 degrees. A device is provided for combining analog and digital in-band-on-channel (IBOC) signals to feed a common antenna utilizing phase shifting allpass filter modules to provide a 180 degree phase shift to specific IBOC channels within a constant impedance dual-hybrid circuit. The IBOC Allpass combiner includes one input 90 degree 3 dB quadrature hybrid coupler, one output 90 degree 3 dB quadrature hybrid coupler, a load resistor, and two phase shifting allpass filter modules. Each phase shifting allpass filter module is comprised of a two coaxial cavity resonators coupled to a 90 degree 3 dB quadrature hybrid coupler. Components and modules are coupled using mating transmission lines. The four coaxial cavity resonators are used as devices to produce two distinct phase shifts at isolated upper and lower IBOC side band frequencies.

Abstract: The described embodiments provide a configurable pulse generator circuit. More specifically, the described embodiments include a pulse generator circuit; an inverting difference oscillator (IDO) enabling circuit coupled to the pulse generator circuit; and a disable signal coupled to the IDO enabling circuit. When the disable signal is asserted, the IDO enabling circuit is disabled and the pulse generator circuit is configured as a pulse generator. In contrast, when the disable signal is deasserted, the IDO enabling circuit is enabled and the pulse generator circuit is configured as part of an IDO.

Abstract: The present invention provides an adaptable codec for use in a communication system. The adaptable codec is capable of encoding a digital stream to be transmitted according to any one of a number of encoding schemes. A particular encoding scheme may be selected based on information received from a network entity that is separate from the communication system, a user associated with the communication system, a remote communication system with which communications are established, or a combination thereof. Once a particular encoding scheme is selected, an encoder will encode the digital stream to be transmitted, and a packet processor will create packets from the encoded digital stream. The selection of an encoding scheme will generally correspond to a desired quality of experience level.

Abstract: The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal.

Abstract: Digital signals with higher resolution are generated from dual-phase encode signals indicating phase changes of a position or an angle of a target. A signal processing apparatus for processing dual-phase encode signals indicating changes in position of a target, comprises: a first noise reduction unit configured to remove high frequency noise from each of the dual-phase encode signals before interpolation processing; an interpolating unit configured to apply interpolation processing to the dual-phase encode signals output from the first noise reduction unit to generate dual-phase encode signals with higher resolution; and a second noise reduction unit configured to remove noise from the dual-phase encode signals output from the interpolating unit.

Abstract: A pulse generator circuit with ferroelectric memory element is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors that operate as a diode and resistor, respectively. Optionally, a third thin film transistor may be provided to operate as a pass transistor in response to an enable signal. The elements of the circuit are configured such that a rising pulse on an input node triggers an output pulse on an output node in the manner of a monostable multivibrator. The ferroelectric memory element is coupled to the output node such that a pulse on the output node may change a state of the ferroelectric memory element.

Abstract: A first transmitter transmits symbols. The leading edge of each symbol has the form Djexp{?jt}, where Dj is real, where ?j is selected from N possible values based on a current group of bits. The receiver has N filters whose transfer functions correspond respectively to the N possible values. The filter outputs are used to recover the group of bits. A second transmitter transmits an exponential symbol or a zero symbol depending on a current bit to be transmitted. The zero symbol has zero amplitude over the symbol period. The corresponding receiver applies threshold detection to estimate the transmitted bits. A third transmitter transmits a sequence of analog pulses with known interpulse time separation(s). The pulse sequence reflects from a moving object. A receiver captures the reflected pulse sequence. The interpulse separation(s) of the reflect pulse sequence is used to determine the radial velocity of the object.

Abstract: A device includes a dock generator operable to generate a clock signal. A first module includes a first clock network coupled to the clock generator for distributing the clock signal. A second module includes a second clock network coupled to the clock generator for distributing the clock signal. A clock skew control circuit is operable to receive a first instance of the clock signal from the first clock network and a second instance of the clock signal from the second clock network and to control skew between the first and second instances of the clock signal.

Abstract: Communications systems and/or methods are disclosed that may be used to convey information by forming, and then using, a plurality of frequency agile baseband waveforms, wherein any two different waveforms of the plurality of frequency agile baseband waveforms comprise an orthogonality therebetween. The systems/methods disclosed can convey information by mapping an information sequence into a baseband waveform sequence that includes waveforms of the plurality of baseband waveforms, and by transmitting the baseband waveform sequence. Such systems and/or methods can provide extreme privacy, cognitive radio capability, robustness to fading and interference, communications performance associated with M-ary orthonormal signaling and/or high multiple-access capacity.

Abstract: An adaptive clock generating apparatus is provided. The apparatus includes a fixed frequency divider, a replica, a counter, a variable frequency divider. The adaptive clock generating apparatus generates a clock whose period varies along with changes in the critical path delay of a synchronous circuit.

Abstract: A clock generating circuit includes: a counter that counts a number of pulses of an oscillation clock signal existed within one cycle of a reference clock signal; a first time-to-digital converter that generates a plurality of phases of first clock signals by delaying the oscillation clock signal; a second time-to-digital converter that generates a plurality of phases of second clock signals by delaying the oscillation clock signal by a short delay time; a third time-to-digital converter that generates a plurality of phases of third clock signals by delaying the delayed first clock signal; a delay control unit that outputs a delay control signal based on a difference between a cycle of the oscillation clock signal and a target cycle; and an oscillator that generates, based on a cycle of the reference clock signal, the oscillation clock signal whose cycle is 1/m of the cycle of the reference clock signal.

Abstract: A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal.

Abstract: A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal.

Abstract: A multi-valued logic (MVL) circuit includes a MVL clock generator that generates a MVL clock signal having three or more ith MVL levels, a single MVL clock signal distribution network connected to the MVL clock generator, and three or more ith MVL selection circuits connected to the single MVL clock signal distribution network where i=0 to N and N>=3. Each ith MVL selection circuit corresponds to a specified ith MVL level. The ith MVL selection circuit outputs an ith binary clock signal having: (a) a first logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the first logic level, (b) a second logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the second logic level, and (c) a previous logic level of the ith binary clock signal whenever the MVL clock signal is not equal to the ith MVL level.

Abstract: The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.

Abstract: The present invention relates to a clock signal generating circuit and a power supply including the same. The present invention includes: a counter for counting one period of an input clock signal by using a reference clock signal, and generating a count signal; and a clock signal generator for receiving the count signal and the reference clock signal, dividing the count signal to generate a quotient and a remainder, setting the quotient as a reference period of an output clock signal, and distributing and disposing the remainder to the output clock signal with a plurality of periods occurring for one period of the input clock signal.

Abstract: An apparatus and method for reducing interference signals using multiphase clocks. An integrated circuit includes a digital circuit and an analog circuit. The digital circuit includes a derived clock circuit configured to receive a root clock having a frequency D*f, D being a divide factor, to divide the root clock by D, and generate multiphase clocks having N phases. N circuits of the digital circuit are configured to receive a corresponding one of the N phases, with edges of the multiphase clocks being spread over the N phases. The multiphase clocks cause a frequency shift in interference signals generated by reduced periodic peak currents drawn by the N circuits from f to N*f and harmonics thereof. The analog circuit receives an in-band range of signals. A value of N is configured to shift the interference signals outside the in-band range of signals.

Abstract: Timer circuitry completely formable in an integrated circuit (IC) for generating a clock signal in an implantable medical device is disclosed. The timer circuitry can be formed on the same Application Specific Integrated Circuit typically used in the implant, and requires no external components. The timer circuitry comprises modification to a traditional astable timer circuit. A resistance in the disclosed timer circuit can be trimmed to adjust the frequency of the clock signal produced, thus allowing that frequency to be set to a precise value during manufacturing. Precision components are not needed in the RC circuit, which instead are used to set the rough value of the frequency of the clock signal. A regulator produces a power supply for the timer circuitry from a main power supply (Vcc), producing a clock signal with a frequency that is generally independent of temperature and Vcc fluctuations.

Abstract: A clock driver circuit supplies a clock signal with a drive strength determined according to one or more control signals supplied to the clock driver that vary during run-time. The clock driver is operated with a first drive strength in a non-resonant mode of operation of an associated clock network and with a second drive strength in a resonant mode of operation of the associated clock network, the first drive strength being higher than the second drive strength.

Abstract: A semiconductor apparatus includes a clock frequency change block configured to output a plurality of internal clocks with different frequencies by dividing a frequency of an external clock in response to a mode register set signal and a setting command to enable the plurality of internal clocks to be outputted, and generate a flag signal to designate the completion of the output, and a command generation block configured to receive a command and generate the setting command in response to the flag signal and the mode register to set signal.

Abstract: In some embodiments, a synchronizing circuit includes at least one synchronization device that operates at a lower clock frequency than another synchronization device in the synchronization circuit. In at least one embodiment of the invention, a method includes sampling a first signal at a first frequency to thereby generate a plurality of sampled versions of the first signal. The first frequency is a frequency of a clock signal divided by N. N is a number greater than one. The method includes sampling a second signal at the frequency of the clock signal. The second signal is based on sequentially selected ones of the plurality of sampled versions of the first signal to thereby generate an output version of the first signal.

Abstract: Various apparatuses and methods are disclosed. The system describes a pulse generator comprising a first stage configured to be powered by a first voltage; and a second stage configured to be powered by a second voltage different from the first voltage, wherein the second stage is further configured to generate a pulse in response to an input to the first stage comprising a trigger and feedback from the second stage.

Abstract: A current reuse frequency divider including a first latch circuit and a second latch circuit is provided. The first latch circuit includes a first transistor pair and a second transistor pair. The first latch circuit receives a first differential oscillation signal through bodies of the first transistor pair and the second transistor pair and divides the frequency of the first differential oscillation signal to generate a second differential oscillation signal. The second latch circuit is coupled to the first latch circuit and includes a third transistor pair and a fourth transistor pair. The second latch circuit receives the first differential oscillation signal through bodies of the third transistor pair and the fourth transistor pair and divides the frequency of the first differential oscillation signal to generate a third differential oscillation signal.

Abstract: A pulse generator circuit is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors that operate as a diode and resistor, respectively. Optionally, a third thin film transistor may be provided to operate as a pass transistor in response to an enable signal. The elements of the circuit are configured such that a rising pulse on an input node triggers an output pulse on an output node in the manner of a monostable multivibrator.

Abstract: Provided is a semiconductor circuit. The semiconductor circuit includes a pulse generator which is enabled by a rising edge of a clock signal and generates a read pulse which varies depending on a voltage of a feedback node; and a sense amplifier which generates a voltage of a dynamic node and the voltage of the feedback node in accordance with a data value of an input signal using the read pulse.

Abstract: A sampling circuit includes a continuous section which is a circuit for transmitting a continuous signal; a digital section for transmitting a signal which is sampled and quantized; and a sampling and holding section for transmitting a signal which is sampled but not quantized between the continuous section and the digital section. The sampling and holding section includes capacitors for accumulating charge generated by an input signal and plural switches for accumulating the charge in the capacitors. The plural switches receive plural clock signals having different operation timings and perform an ON/OFF operation in response to the supplied clock signals.

Abstract: An operation clock generation circuit performs a calculation on the basis of the frequency errors of a fundamental clock and the clock pulses of the fundamental clock, and generates an operation clock obtained by correcting the frequency errors at first intervals. A correction clock generation circuit converts a lower-bit value that is a value represented by the bits lower than the predefined bit used for judging the change of the state of the operation clock into a count number of the clock pulses of a second clock whose frequency is higher than that of the operation clock, generates a correction clock obtained by correcting the operation clock on the basis of a time required for counting the count number of the clock pulses and the clock pulses of the operation clock.

Abstract: A signal transmission circuit 200 transmits input signals IN1 and IN2 each having a different transmission speed in a mutually electrically insulated manner. Signal transmission circuit 200 includes a pulse generation unit 210, transmission units 230 and 235, a latch circuit 250, and an oscillation determination circuit 270. Transmission units 230 and 235 transmit pulse signals PLS_A and PLS_B generated by pulse generation unit 210 in accordance with logical states of input signals IN1 and IN2 to latch circuit 250 and oscillation determination circuit 270 in a mutually electrically insulated manner. Latch circuit 250 restores input signal IN1 in accordance with rising edges of pulse signals PLS_A and PLS_B. Oscillation determination circuit 270 restores input signal IN2 based on oscillation states of pulse signals PLS_A and PLS_B. With such a configuration, a plurality of signals each having a different transmission speed can be transmitted in a mutually electrically insulated manner.