Abstract: A capacitance multiplier circuit is configured to sense a current through a capacitor in an RC filter of the circuit and to multiply the current so as to achieve a capacitance multiplier effect without adding additional circuitry or requiring additional power. The circuit includes an RC filter, a first signal path connected to a filter output, and a second signal path connected to an input to the filter. A current output through the filter (iout) is split between the two paths, sensed in the first path and multiplied in the second path. The multiplied current is fed back from the second path to the filter input to raise the effective capacitance of capacitor C. The capacitance multiplier circuit, in raising the effective capacitance of the capacitor in the filter, does not affect the frequency response, linearity performance and/or stability of the overall circuit.

Abstract: A semiconductor driver circuit includes impedance units for generating impedances at data pads, independently of each-other. Thus, signal swing widths of data signals generated at the data pads may be easily adjusted to be substantially equal for high operating speed. The semiconductor driver circuit also includes switching units for uncoupling at least one of the impedance units from at least one of the data pads for enhanced testing of the data pads.

Abstract: An apparatus configured as a compandor to achieve a defined dynamic range for an output signal in response to an input signal. In particular, the apparatus comprises a first circuit adapted to generate a first signal from the input signal, wherein the first signal includes a first dynamic range (e.g., a first sensitivity and first compression point); and a second circuit adapted to generate a second signal from the input signal, wherein the second signal includes a second dynamic range (e.g., a second sensitivity and second compression point) that is different from the first dynamic range of the first signal. The apparatus may further include a third circuit adapted to generate an output signal related to a sum of the first and second signals. By adjusting the first and second dynamic ranges, an overall dynamic range for the output signal of the companding apparatus may be achieved.

Abstract: A trimming circuit is disclosed. The trimming circuit includes a first trimming circuit having resistors and fuses, and a second trimming circuit having a resistor, an NMOS transistor, and a control circuit. The control circuit includes an inverter circuit and a series circuit in which a resistor and fuses are connected in series. The first trimming circuit is connected with a reference resistor in series and the second trimming circuit is connected with the reference resistor in parallel.

Abstract: According to at least one embodiment of the invention, an apparatus may include first, second and third circuits. The first circuit receives input data and provides a plurality of first signals asserted based on the input data. The second circuit receives the plurality of first signals and provides a plurality of second signals used to select a plurality of circuit elements. The third circuit generates a control for the second circuit using a fractional data weight of the input data, the second circuit mapping the plurality of first signals to the plurality of second signals based on the control from the third circuit.

Abstract: A voltage controlled variable capacitor, formed of a larger number of fixed capacitor segments and a corresponding number of switching elements, uses translinear amplifiers to control each switching element. Each translinear amplifier linearly switches from the fully off to the fully on state; a minimum number of switching stages (ideally only one) is in the mode-of-change at any one time with a minimum overlap. The arrangement achieves a nearly linear change of capacitance at linear tuning voltage change, while resulting in high Q-factor due to the low RDSon and high RDSoff of the fully switched stages. The invention eliminates temperature and voltage dependencies of other solutions like varactor diodes.

Abstract: A control device contains a plurality of controllers, a common signal output, and a change-over unit. The controllers are coupled on an output side to the common signal output through the change-over unit. A plurality of differentiating elements are disposed upstream of the change-over unit and in each case connected with one of the controllers. An integrating element follows the change-over unit. An output of a controller is first differentiated, sent through the change-over unit, and then integrated.

Abstract: The present invention provides a set of analog circuit modules and procedures for assembling them into circuits that represent fundamental expressions and operations in mathematics, and more specifically to circuits for performing computations on problems formulated as constraints in Set Theory. In this invention, physical analogues of mathematical sets are realized by the current flowing through electronic circuit devices, or by the voltage across such devices. A circuit assembled from set analogue devices appropriately connected together can generate analogues of the basic operations in Set Theory, such as intersection, union, complement, difference, subset, etc. Using these basic circuit modules, the analogues of arbitrarily complex expressions and operations can be obtained by combination. A complete circuit that is the analogue of Set Theory expressions defining the problem specification can be assembled by requiring the circuit and the Set Theory expressions to have the same topology.

Abstract: An anti-exponential amplifier produces an output signal that is an exponential/anti-logarithmic function of an input signal. The amplifier includes three function generators and a low-pass filter. The first function generator produces a periodic exponential waveform based upon a resistor-capacitor time constant, with the magnitude of the periodic exponential waveform exponentially increasing to a maximum value in each period. A second function generator produces a ramp waveform from the exponential waveform. The ramp waveform has a period and maximum amplitude substantially equal to those of the exponential signal. The third function generator produces a hybrid waveform with a first portion and a second portion, with the duration of the first period determined in response to the ramp waveform. A low pass filter produces the anti-logarithmic output signal as a function of the hybrid waveform. The resulting amplifier could be useful in a brightness or other parameter control for a display.

Abstract: An on-chip detection circuit automatically detects when an external switch has been activated. When the device is initialized, the detection circuit measures the operating current and coverts the information into an analog voltage. The analog voltage is then processed through an on-chip analog-to-digital converter and the digitized result is stored as a reference value. To sense the open and close action of the off-chip mechanical switch, the device then takes a sample of the operating current periodically, digitizes this information and compares the sampled value to the reference value. A change in value larger than some predetermined level indicates the external switch has been activated.

Abstract: An internal power voltage trimming circuit and its method individually or simultaneously perform level trimming for a plurality of power voltages in a semiconductor memory device. The internal power voltage trimming circuit includes a trimming control signal generator for generating a trimming selection signal and a trimming enable signal by using an inputted address signal, and an internal power voltage level controller for controlling the levels of the internal power voltages by using the trimming selection signal that is outputted under control of the trimming enable signal.

Abstract: An input circuit includes an input signal transmission circuit configured to output a first transmission signal at a first output node in response to an input signal at an input node, and a Schmitt trigger inverter configured to output a second transmission signal at a second output node in response to the first transmission signal. The input signal transmission circuit includes a voltage drop element connected to the input node and configured to provide a voltage drop between the input node and a transistor having a gate to which a first supply voltage is applied.

Abstract: An internal power voltage trimming circuit and its method individually or simultaneously perform level trimming for a plurality of power voltages in a semiconductor memory device. The internal power voltage trimming circuit includes a trimming control signal generator for generating a trimming selection signal and a trimming enable signal by using an inputted address signal, and an internal power voltage level controller for controlling the levels of the internal power voltages by using the trimming selection signal that is outputted under control of the trimming enable signal.

Abstract: The present invention comprises a method and structure for programming an on-chip phase-change resistor to a target resistance. Using an off-chip precision resistor as a reference, a state-machine determines a difference between the resistance of an on-chip resistor and the target resistance. Based upon this difference, the state machine directs a pulse generator to apply set or reset pulses to the on-chip resistor in order to decrease or increase, respectively, the resistance of the resistor, as necessary. In order to program the resistance of the phase-change resistor to a tight tolerance, it is successively reset and set by applying progressively decreasing numbers of reset pulses and set pulses, respectively, until the number of set pulses is equal to one and the target resistance of the on-chip resistor is reached.

Abstract: Values of control signals 61, 62, 63, . . . , 6n, each inputted to an input terminal for operation control 6 of each of transistor elements 4 constituting a variable resistance portion 2, are controlled based upon an input signal 40 and offset signals 52, 53, . . . , 5n generated by an offset provision portion 3. Thus, a ratio of the maximum resistance value to the minimum resistance value can be made large, while using a limited power supply voltage range as a control range.

Abstract: A system and method for generating multiple drive strengths for one or more output signals of a memory controller operable to control a memory subsystem. The system includes a state machine operable to generate an n-bit output representative of a drive strength operable to drive the one or more output signals; and a plurality of adders, each adder having a plurality of n-bit inputs, each input receiving a selective set of bits from the n-bit output of the state machine, the adders generating a plurality of n-bit outputs representative of drive strengths operable to drive the output signals. The method includes generating an n-bit output representative of a drive strength, and adding combinations of two or more selective sets of bits from the n-bit output to generate a plurality of n-bit outputs representative of a plurality of drive strengths that are operable to drive the output signal.

Abstract: Variations in the actual resistance of a target poly resistor in a semiconductor integrated circuit can be compensated for by using an active circuit that provides a negative resistance in parallel with the target resistor. This produces a tuned resistance that is closer to a desired resistance than is the actual resistance of the target resistor.

Abstract: In a signal processing system with an IC having an intrinsic signal provided at a pin of the IC, a first operational function (de-emphasis) for the signal is provided at the pin, and further along in the signal flow path, a second operational function (variable attenuation) for the signal is provided within the IC. An extrinsic signal is switchably coupled to the pin so that the second operational function can be used to operate on the extrinsic signal. The second signal is coupled to the pin at a low source impedance so that when the second signal is switched to be operational, the first operational function is defeated, and the first signal is severely attenuated. When the circuit is switched to not couple the second signal to the pin, the coupling path for the second signal and the low source impedance are both removed, thus restoring the first operational function and the first signal at the pin of the IC.

Abstract: A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.

Abstract: Using programmable resistance material for a matching resistor, a resistor trimming circuit is designed to reversibly trim a matching resistor to match a reference resistor. The programmable resistance materials such as metal-amorphous silicon metal materials, phase change materials or perovskite materials are typically used in resistive memory devices and have the ability to change the resistance reversibly and repeatably with applied electrical pulses. The present invention reversible resistor trimming circuit comprises a resistance bridge network of a matching resistor and a reference resistor to provide inputs to a comparator circuit for generating a comparing signal indicative of the resistance difference. This comparing signal can be used to control a feedback circuit to provide appropriate electrical pulses to the matching resistor to modify the resistance of the matching resistor to match that of the reference resistor.

Abstract: An impedance adjustment circuit has an external resistor, a comparator which compares the potential of one terminal of the external resistor with a predetermined voltage, a counter whose counted value changes in accordance with an output from the comparator and which outputs a control signal corresponding to the counted value, an NMOS array whose value of resistance changes in accordance with the control signal and which is connected to one terminal of the external resistor and an NMOS arbitration circuit which detects an output from the NMOS comparator a plurality of times and outputs a signal determined by a majority decision logic taken on the detected signals to the counter.

Abstract: Using programmable resistance material for a matching resistor, a resistor trimming circuit is designed to reversibly trim a matching resistor to match a reference resistor. The programmable resistance materials such as metal-amorphous silicon metal materials, phase change materials or perovskite materials are typically used in resistive memory devices and have the ability to change the resistance reversibly and repeatable with applied electrical pulses. The present invention reversible resistor trimming circuit comprises a resistance bridge network of a matching resistor and a reference resistor to provide inputs to a comparator circuit which generates a comparing signal indicative of the resistance difference. This comparing signal can be used to control a feedback circuit to provide appropriate electrical pulses to the matching resistor to modify the resistance of the matching resistor to match that of the reference resistor.

Abstract: Transition signal control for creating asynchronous timing is provided using a transition signal control circuit, which includes Muller C elements each with an inverter. The control device is constituted by a machine ring including n-stages of transition signal control circuits, a state ring including k-stages of transition signal control circuits, and a synchronous circuit for synchronizing with the machine ring by receiving a vector which is output from the state ring. When the output vector of the state ring is received, the synchronous circuit outputs a vector to the machine ring. The output vector of the machine ring and the output vector of the state ring create timings for controlling the processor, for example, asynchronously, and these timings are input to the instruction decoder, for example.

Abstract: Methods and apparatus for automatic tuning of MOSFET resistors providing accuracy and linearity throughout process and temperature variations. In accordance with the methods, the source and drain of a MOSFET device are biased in a balanced manner around a common mode voltage using a circuit controlling the gate voltage of the MOSFET to set the current through the MOSFET responsive to the value of a resistor. Operating MOSFETs, such as in MOSFET-C filters, with the same device conductivity type, gate bias, substrate voltage and signal common mode voltage provides linear MOSFET resistors, accurately set by a single resistance value. Use of an external resistor provides a single pin setting of MOSFET resistances, that may be independent of temperature and process variations. Various embodiments are disclosed.

Abstract: There is disclosed a variable capacitance circuit which comprises: first to Nth variable capacitance elements C1-CN (N is an odd number) sequentially connected in series between an input terminal I and an output terminal O, whose capacitances change depending on voltage applied thereto; an ith bias line on the input terminal side provided between an input terminal portion of the first variable capacitance element and a connection point between a 2ith variable capacitance element and a (2i+1)th variable capacitance element; and an ith bias line on the output terminal side provided between an output terminal portion of the Nth variable capacitance element and a connection point between a (2i?1)th variable capacitance element and the 2ith variable capacitance element, where N and i are integers satisfying N=2n+1, n?1, 1?i?n.

Abstract: A high-precision and high-performance level shift circuit, which is not adversely influenced by an offset error owned by an operational amplifier. Two sets of resistors (4o) and (4p) having the same resistance values, which are connected between differential output terminals and an operational amplifier (4r) for performing a level shift control are provided. A feedback operation is carried out in such a manner that an average voltage of each of differential outputs (4i) and (4m) is continuously made coincident with a DC reference potential (4q) irrespective of an offset error of an output-purpose operational amplifier, and a level shift function having a small error is realized. Two resistors (4h and 4l) are series-connected between a differential output of a digital/analog converter (4a) and a level shift circuit to output a voltage outside an output dynamic range of the digital/analog converter (4a).

Abstract: An integrated circuit has a voltage divider that is configured to save current. The circuit includes a capacitor that is inventively connected to a potential sink or potential source by way of a charge branch even when the voltage divider is inactive. The capacitor is thus held at a charge state that corresponds to the charge state given an active voltage divider. The voltage divider thus becomes functional in a shorter time following activation, because the capacitor does not require recharging.

Abstract: A compensation arrangement, having a first FET (220) having a non-linear response as an active resistor and a second FET (240) having a non-linear response coupled to the first FET (220), reduces non-linearity in an active resistor network. The non-linear response of the second FET (240) is adapted in order to compensate for the non-linear response of the first FET (220). The two FETs (220, 240) are complementary, and are selected to achieve the desired overall resistance value of the network. In this way the arrangement substantially reduces non-linear performance with an applied voltage, and is well suited for high frequency applications.

Abstract: An impedance adjustment circuit has an external resistor, a comparator which compares the potential of one terminal of the external resistor with a predetermined voltage, a counter whose counted value changes in accordance with an output from the comparator and which outputs a control signal corresponding to the counted value, an NMOS array whose value of resistance changes in accordance with the control signal and which is connected to one terminal of the external resistor and an NMOS arbitration circuit which detects an output from the NMOS comparator a plurality of times and outputs a signal determined by a majority decision logic taken on the detected signals to the counter.

Abstract: A variable impedance circuit has an impedance block including a plurality of MOS transistors connected in parallel by switching and having impedances in accordance with powers of 2, the powers corresponding to the sequential orders of the MOS transistors arranged. A control unit controls ON or OFF of each of the MOS transistors to thereby select one of overall impedances of the MOS transistors. The step difference in the variable impedances is substantially a constant irrespective of the overall impedance selected.

Abstract: A voltage generation circuit for generating a read-back voltage in response to a supply voltage and a reference voltage. The voltage generation circuit includes a comparator configured to receive the supply voltage and the reference voltage. The voltage generation circuit activates a select signal if the supply voltage has a predetermined relationship with respect to the reference voltage, and de-activates the select signal if the supply voltage does not exhibit the predetermined relationship with respect to the reference voltage. An adjustable voltage divider circuit is coupled to receive the supply voltage and the select signal. The adjustable voltage divider circuit is configured in response to the select signal to provide an output voltage that is a first percentage of the supply voltage if the select signal is activated, and provide an output voltage that is a second percentage of the supply voltage if the select signal is de-activated.

Abstract: A common bias section is composed of a first series circuit having an internal resistor and an external resistor connected in series and an operational amplifier having a first input terminal connected to a reference voltage, a second input terminal connected to a Vr1 node, and an output terminal connected to the series circuit. An impedance trimming section is composed of a series circuit having an internal resistor and an impedance dummy resistor connected in series, a comparator CMP having a first input terminal connected to the Vr1 node and a second input terminal connected to a Vto1 node, a code control circuit which uses a clock signal to latch an output signal from the comparator to generate a plurality of switching codes, and a switching circuit which switch a resistance value of the impedance dummy resistor.

Abstract: A hybrid circuit has a transfer function having three zeros and four poles that are realized using only two fully-differential amplifiers in combination with a small plurality of resistors and capacitors, making the hybrid suitable for use with a communication medium comprising capacitively coupled non-ideal transformers and transmission lines while providing remarkably good hybrid rejection without the use of inductors.

Abstract: A circuit, method and system for generating a non-linear transfer characteristic, including a plurality of current mirror circuits in parallel, each current mirror circuit having an offset current applied to an output terminal of an output-side transistor of the current mirror circuit for controlling an output current thereof, wherein the offset current of each current mirror circuit is set to a respective predetermined level, and the transfer characteristic is generated by summing the respective output currents of the current mirror circuits in a piece-wise manner.

Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as a capacitor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.

Abstract: Even in the case where the reference voltage of a reference-voltage generating circuit is adjusted by fuses, a number of fuses are required to be disconnected, and the area of fuse circuits tends to increase for fine adjustment. Therefore, by dividing control signals into one part that are predetermined by fixed wiring and another part that is adjustable by fuse circuits, time required for disconnecting fuses is minimized and fine adjustment is made possible.

Abstract: The invention relates to a circuit device for realizing a non-linear reactive elements scale network, wherein the non-linear elements of the network are pairs of inductive and capacitive components cascade connected between a pair of input terminals and a pair of output terminals. Advantageously in the invention, each component of the network is formed by cascade connecting a first and a second transconductance integrator with each other.

Abstract: An analog unit system according to this invention comprises a first analog unit having first storage means for storing a first factory setting value and a first user setting value, second storage means for reading the first factory setting value and the first user setting value out of the first storage means and storing the setting values, operation means for calculating a second user setting value based on the first factory setting value and the first user setting value read out of the second storage means, and a second analog unit having third storage means for storing the second user setting value calculated by this operation means and thereby, adjustment and calibration of the user setting value can automatically be performed by simple manipulation with respect to the analog unit in which the user setting value is not set.

Abstract: The present invention relates to a resistance calibration circuit to correct a resistance variation in an output terminal of a semiconductor device. The resistance calibration circuit according to the present invention includes: a correction code generator for generating a plurality of push-up code signals and a plurality of pull-down code signals based on an external reference resistor, wherein a reference voltage is applied to the correction code generator; a push-up decoder for decoding the plurality of push-up code signals from the correction code generator; a pull-down decoder for decoding the plurality of pull-down code signals from the correction code generator; and a resistance adjustor for receiving a push-up signal from the push-up decoder and a pull-down signal from the pull-down decoder and for turning on/off a plurality of inner transistors.

Abstract: A baseband analog circuit includes a demodulator to demodulate a received signal and to output a baseband analog signal, a low-pass filter to filter the demodulated baseband analog signal, and an impedance converter, provided between the demodulator and the low-pass filter, having lower output impedance than the output impedance of the demodulator.

Abstract: In a parameter correction circuit to be included in an LSI, a reference resistor element with high precision having a resistance value set to a target value is connected to the external terminal of the LSI. A constant current I1 is allowed to flow from a mirror circuit connected to a current supply to the reference resistor element so that a voltage value generated in the reference resistor element is measured by a voltage measuring circuit. Next, a constant current I1 is allowed to flow in the same manner from the mirror circuit to a variable resistor element to be adjusted and corrected, and at this time, the resistance value of the variable resistor element is adjusted so that a voltage generated in the variable resistor element is allowed to correspond to the voltage generated in the reference resistor element.

Abstract: A method to establish an adjustable on-chip impedance within a predetermined range that involves establishing a reference current for the adjustable on-chip impedance and applying this reference current to the adjustable on-chip impedance. A voltage produced by applying the reference current to the adjustable on-chip impedance is sensed and compared with the comparator or other similar processor to a reference voltage. This comparison allows the adjustable on-chip impedance to be tuned when the comparison of the sense voltage and the reference voltage is unfavorable. Tuning the impedance results in an impedance value within a predetermined range that accounts for variances of both the reference current and reference voltage.

Abstract: An input control signal within a range corresponding to static operating states of a circuit device (18) is applied to an input terminal (12). A sigma delta modulator (14) quantizes the input control signal. An output terminal (16) subsequently applies the quantized signal to the circuit device (18) for selecting a new operating state different than the static operating states by rapidly switching between operating states of the circuit device to generate a time averaged response of the circuit device that is within the range corresponding to the static operating states of the circuit device and consistent with the input control signal.

Abstract: A dynamic low power reference circuit includes a reference source for generating a reference voltage and/or a reference current. The reference circuit further includes an activity detector configured to measure an activity level of at least a portion of another circuit coupled to the reference circuit and to generate a control signal representative of the activity level. A controller coupled to the reference source is configured to dynamically change an output impedance of the reference circuit in response to the control signal. The techniques of the present invention thus provide a reference circuit that is capable of dynamically changing an output impedance associated therewith, such that when activity on one or more nodes in the other circuit is detected within a time period, the output impedance of the reference circuit is at a first value which is sufficiently low so as to reduce the likelihood of noise being coupled onto the output of the reference circuit.

Abstract: An internal power voltage generating circuit of a semiconductor device includes a voltage dividing circuit composed of a single field effect transistor and a plurality of resistances incorporated into a semiconductor chip. The voltage dividing circuit divides an externally supplied power voltage into two types of voltage by conducting or non-conducting the single field effect transistor. The divided voltages are supplied as an internal power voltage to a plurality of field effect transistors incorporated into the semiconductor chip.

Abstract: A capacitive element includes two or more voltage-variable capacitors (varactors). The varactors are configured so that they are coupled in series with respect to an applied AC signal and are coupled in parallel with respect to an applied DC bias voltage. The effective capacitance of the overall capacitive element can be tuned by varying the DC bias voltage.

Abstract: The invention relates to a circuit arrangement for a current-controlled resistor having an enlarged linear range, using an arrangement of non-linear bipolar load elements wherein the resistance is generated between a first terminal (E) and a second terminal (F), having at least one control terminal (X) that is fed by a supply current source (I1), wherein the arrangement of the non-linear bipolar load elements comprises at least a third chain (C) comprising one or more of the load elements (DC1 . . . DCi), the load elements being connected in series where there is more than one of them, and comprises a first chain (A) and a second chain (B) each comprising one or more load elements (DA1 . . . DAj and DB1 . . .

Abstract: A circuit arrangement for a resistor of high linearity that can be produced in integrated technology and be controlled by the current (Io1, Io2), which circuit arrangement is constructed from two pairs of transistors comprising transistors (T1 . . . T4) of the same junction type connected as diodes. Each pair of transistors (T1, T2 and T3, T4) has a common point of connection (D, E) that connects together the anodes of one pair of diodes and the cathodes of the other pair. The point of connection (D) of the first pair of transistors (T1, T2) is situated on their collector lines and thus connects the anodes and forms the infeed point for a first control current source (Io1). The point of connection (E) of the second pair of transistors connects the cathodes and is thus situated on their emitter lines and forms the infeed point for a second control current source (Io2).

Abstract: A gradation selector circuit provided with a resistor string circuit in which resistive elements are connected in series between a high potential power source and a low potential power source and a selector circuit which is connected to the resistor string circuit, which selects one of plural analog voltages generated in the resistor string circuit according to a control signal and which outputs it to an output terminal is used. The selector circuit includes analog switching circuits that select analog voltage close to intermediate potential. The analog switching circuit includes a P-type MOS transistor to the source electrode and the back gate electrode of which the resistor string circuit is connected and a depletion type N-type MOS transistor to the source electrode of which the drain electrode of the P-type MOS transistor is connected and to the drain electrode of which an output terminal is connected.

Abstract: A switching device (20) is formed to generate a ramp voltage by using a capacitor (48) formed on the semiconductor die (90) with the switching device (20). The switching device (20) drives a high-power device to conduct load currents for a load. The ramp voltage is used to gradually increase the drive that is applied to the high-power device in order to gradually increase the current conducted by the high-power device.