Abstract: An apparatus includes first and second switches. The first switch is for coupling a first node to a second node responsive to a first control signal having a first value, and for decoupling these nodes responsive to the first control signal having a second value. The second switch is for coupling the first node to a third node responsive to a second control signal having the first value, and for decoupling these nodes responsive to the second control signal having the second value. A load is coupled between the second and third nodes. A detection circuit coupled to the first node is configured to generate a signal indicating whether voltage at the first node exceeds a threshold. First and second modules are configured to set the first and second control signals to the second value responsive to the signal indicating that the voltage at the first node exceeds the threshold.

Abstract: A circuit is provided and includes current sources, switches, a control module, and capacitances. The current sources adjust current flowing through a load. Each of the switches activates a respective one of the current sources. Kick-back voltages are generated at inputs of the current sources in response to the current sources being turned ON. A control module generates control signals to change states of the switches to alternate a direction in which the current flows through the load. A first capacitance is connected between a first pair of the current sources and a second pair of the current sources. A second capacitance is connected between the first pair of the current sources and a reference terminal. A third capacitance connected between the second pair of the current sources and the reference terminal. The first capacitance, the second capacitance, and the third capacitance reduce magnitudes of the kick-back voltages.

Abstract: A power gating circuit is configured to connect a first voltage line to a second voltage line or separate the first voltage line from the second voltage line using a Schmitt trigger circuit that is configured to detect a voltage level of the second voltage line. The voltage lines are power lines or ground lines.

Abstract: A low voltage isolation circuit is coupled between an input terminal for receiving a high voltage signal and an output terminal for transmitting the high voltage signal to a load. The isolation circuit includes a driving block; having a first driving transistor coupled between a first voltage reference and an intermediate node and a second driving transistor coupled between the intermediate node and a second voltage reference; an isolation block connected between the input and output terminals and, through a protection block to the intermediate node. The protection block includes first and second protection transistors (MD1, coupled in anti-series to each other and having control terminals receiving complementary protection driving signals. The isolation block includes a voltage limiter block, a diode block and a control transistor connected across the diode block between the input and output terminals and having a control terminal connected to the intermediate node through the protection block.

Abstract: A thermal controller for driving a gate control unit of a gate-driven semiconductor switching device, the thermal controller comprising a junction temperature estimation module for generating an estimated junction temperature for the switching device, a gate voltage control module for modifying a gate voltage of the switching device, a switching frequency control module for modifying a switching frequency of the switching device, and a duty cycle control module for modifying the duty cycle of the switching device. In use, the thermal controller is adapted to activate one of the gate voltage control module, switching frequency control module and duty cycle control module dependent upon the estimated junction temperature in order to maintain the actual junction temperature below a pre-determined limit.

Abstract: A power device includes a switching device having a control terminal and an output terminal; and a driving circuit configured to provide a driving voltage to the control terminal such that a voltage between the control terminal and the output terminal remains less than or equal to a critical voltage. A rise time required for the driving voltage to reach a target level is determined according to current-voltage characteristics of the switching device. And, when the voltage between the control terminal and the output terminal exceeds the critical voltage, leakage current is generated between the control terminal and the output terminal.

Abstract: Disclosed herein is a resistor-sharing switching circuit, including: a first switching element turning on/off between a first input and output terminal and a second input and output terminal; a second switching element turning on/off between the first input and output terminal and a third input and output terminal; a signal transmission unit connected to both a control terminal of the first switching element and a control terminal of the second switching element; and a resistor having one end connected to the signal transmission unit and the other end connected to a control signal input terminal.

Abstract: To suppress variation of a signal in a semiconductor device. By suppressing the variation, formation of a stripe pattern in displaying an image on a semiconductor device can be suppressed, for example. A distance between two adjacent signal lines which go into a floating state in different periods (G1) is longer than a distance between two adjacent signal lines which go into a floating state in the same period (G0, G2). Consequently, variation in potential of a signal line due to capacitive coupling can be suppressed. For example, in the case where the signal line is a source signal line in an active matrix display device, formation of a stripe pattern in a displayed image can be suppressed.

Abstract: A linear voltage stabilizing circuit includes a main stabilizing unit, a first resistor, a second resistor, and a sub-stabilizing unit. The main stabilizing unit includes a first transistor connected between a signal input terminal and a signal output terminal, and a first comparator controlling the first transistor. The first and the second resistor are connected between the signal input terminal and ground. The voltage between the first resistor and the second resistor is equal to a first reference voltage. The sub-stabilizing unit includes a third resistor, a fourth resistor, a second transistor connected between the signal input terminal and the first transistor, and a second comparator. The third and fourth resistor are connected between the second comparator and ground. The node of the third and fourth resistor is connected to the node between the first and the second resistor. The second comparator controls the second transistor turn on or off.

Abstract: According to one embodiment, a semiconductor switch includes a first element that includes a switching element and an anti-parallel diode. The switching element has a breakdown voltage and is coupled to a control terminal and second and third terminals. The semiconductor switch further includes a second element having a breakdown voltage lower than that of the first element. The second element is coupled to a control terminal and second and third terminals. The semiconductor switch also includes a flyback diode having a breakdown voltage substantially similar to that of the first element. A negative electrode of the first element is connected to a negative electrode of the second element and the flyback diode is connected in parallel between a positive terminal of the first element and a positive terminal of the second element. The control terminal for the first element and the control terminal for the second element are coupled to one or more control circuits independently of each other.

Abstract: The current-mode CMOS logarithmic function circuit provides an ultra-low power circuit that produces an output current proportional to the logarithm of the input current. An OTA (operational transconductance amplifier) constructed from CMOS transistors, in combination with two PMOS transistors configured in weak inversion mode for providing a reference voltage input and a voltage input from the input current to the OTA, provides the circuit with a high dynamic range, controllable amplitude, high accuracy, and insensitivity to temperature variation.

Abstract: A method and apparatus for repairing transistors comprises applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time In this manner the semiconductor structure may be repaired or returned to the at or near the original operating characteristics.

Abstract: A cascode switch includes a first power transistor configured to be coupled to a load and a second power transistor coupled in series with the first power transistor so that the second power transistor is between ground and the first power transistor. The second power transistor is operable to switch on and off responsive to a pulse source coupled to a gate of the second power transistor. The first power transistor is operable to switch on and off responsive to the same pulse source as the second power transistor or a DC source coupled to a gate of the first power transistor. Alternatively or in addition, a transistor device is coupled to the gate of the first power transistor and operable to actively turn off the first power transistor independent of the load current.

Abstract: There is provided a high frequency switch capable of suppressing deterioration in distortion characteristics. The high frequency switch includes: a common port outputting a transmission signal to an antenna; a plurality of transmission ports each having the transmission signal input thereto; and a plurality of switching units each connected between the plurality of transmission ports and the common port to conduct or block the transmission signal from each of the transmission ports to the common port, wherein each of the switching units has one or more metal oxide semiconductor field effect transistors (MOSFETs) formed on a silicon substrate, and a capacitor connected between a body terminal of a MOSFET connected to the common port among the MOSFETs and a terminal of the MOSFET connected to the common port.

Abstract: This document discusses, among other things, a signal switch circuit including a first field effect transistor (FET) configured to couple a first node to a second node in an on-state and a charge pump circuit configured to provide a first supply voltage to control the FET, wherein a reference voltage of the charge pump circuit is coupled to a well of the FET to maintain a constant gate to source voltage of the FET during the on-state.

Abstract: A power semiconductor device includes first and second power semiconductor elements connected in parallel to each other and a drive control unit. The drive control unit turns on or off each of the first and second power semiconductor elements in response to an ON instruction and an OFF instruction repeatedly received from outside. Specifically, the drive control unit can switch between a case where the first and second power semiconductor elements are simultaneously turned on and a case where one of the first and second power semiconductor elements is turned on first and thereafter the other thereof is turned on, in response to the ON instruction. The drive control unit turns off one of the first and second power semiconductor elements first and thereafter turns off the other thereof, in response to the OFF instruction.

Abstract: A multiplex circuit includes: a plurality of input transistors that correspondingly receive a plurality of input signals of different switching points, the switching points beginning with edges of symbol periods of the plurality of input signals; one of a common base transistor that is connected to a collector of the input transistor, and a common gate transistor that is connected to a drain of the input transistor; and an output end that is connected to one of the collector of the common base transistor and the drain of the common gate transistor, and to which a signal that is obtained by combining the plurality of input signals is output.

Abstract: The present invention provides an array substrate, a driving method and a display device. The array substrate comprises a plurality of gate lines. A first gate line of the two adjacent gate lines is coupled to a first switch unit and a second gate line is coupled to a second switch unit. The first switch unit and the second switch unit are coupled to a control line, and are coupled to a gate drive output channel. The second switch unit is turned off when the first switch unit is turned on under control of the control line, and the first switch unit is turned off when the second switch is turned on under control of the control line. According to the present invention, it is able to effectively reduce the number of the gate drive ICs and thereby to reduce the cost.

Abstract: The described FET switch topology greatly reduces the off state loading experienced by the gate biasing resistors in a stacked FET structure. The FET switch topology evenly distributes the voltage across the FET switch topology which reduces the voltage across the gate biasing resistors when the stacked FET structure is in an off state. Because the off state loading is reduced, there is a corresponding reduction of the current through bias resistors, which permits a reduction in the size of the bias resistors. This permits a substantial reduction in the area attributed to the bias resistors in an integrated solution.

Abstract: According to one embodiment, an active clamp circuit includes a first switch element, a first diode, a first resistance, a first control circuit and a second control circuit. The first diode is connected to the first switch element and breaks down by an overvoltage applied to the first switch element. The first resistance is connected to the first diode and detects a current through the first diode. The first control circuit is configured to amplify a voltage across the first resistance and controls a current through the first switch element. The second control circuit is configured to control a conduction of the first switch element in accordance with the voltage across the first resistance.

Abstract: A functional circuit is coupled to a power supply conductor by at least one power gating transistor. A switching device applies a gate drive voltage to a gate terminal of the power gating transistor via a resistive element. The power gating transistor provides a Miller capacitance between its drain and gate terminals. The Miller capacitance, the resistance of the resistive element, and the drive strength of the switching device are configured such that, in response to the switching device switching the gate drive voltage to allow more current to pass through the power gating transistor, the Miller capacitance provides a feedback mechanism competing against the switching device to reduce the slew rate of the gate drive voltage such that the current passing between the power gate supply conductor and the functional circuit through the power gating transistor is less than the saturation current of the power gating transistor.

Abstract: A transistor (1) has a FET (2) and a temperature sensing diode (4) integrated within it. Gate drive circuit (12) is arranged to switch off FET (2) and in this case biasing circuit (14) drives a constant current through the diode (4). The voltage across the diode (4) is measured by voltage sensor (15) which provides a measure of the temperature of the FET.

Abstract: Apparatus and methods for ultrasound transmit switching are provided. In certain implementations, a transmit switch includes a bias polarity control circuit, a bias circuit, a first high voltage field effect transistor (HVFET), and a second HVFET. The sources of the first and second HVFETs are connected to one another at a source node, the gates of the first and second HVFETs are connected to one another at a gate node, and the drains of the first and second HVFETs are connected to an input terminal and an output terminal, respectively. The bias circuit and the bias polarity control circuit are each electrically connected between the source node and the gate node. The bias polarity control circuit can turn on or off the HVFETs by controlling a polarity of a bias voltage across the bias circuit, such as by controlling a direction of current flow through the bias circuit.

Abstract: The present invention provides a current limit circuit apparatus, coupled with the gate of a GaN transistor. The current limit circuit comprises a diode, a first transistor, a second transistor, a first resistor, a second resistor, a third resistor and a fourth resistor. The source and the drain of the first transistor couple with the diode. The source of the second transistor couples with the gate of the first transistor. The source of the first transistor couples with the first transistor. The source of the second transistor couples with the second resistor. The third resistor couples with the fourth resistor and the gate of the first transistor. The first transistor turned off and the gate current is limited. When the current of the gate of the GaN transistor exceeds the predetermined value, the breakdown voltage is increased by limiting the gate current.

Abstract: According to one embodiment, an output signal circuit for use in a receiver is provided. The output signal circuit is provided with first and second transistors of an insulated gate field effect type, and a backgate bias generator. A source of the first transistor is capable of receiving an input signal. A source of the second transistor is capable of generating an output signal. A backgate bias generator produces a backgate bias voltage which is applied to backgate of the first and second transistors commonly.

Abstract: Transient blocking unit reset capability is improved by adding one or more transistors in parallel to one of the main blocking transistors of the circuit. These additional transistors switch off at higher voltages than their corresponding main blocking transistor, and have higher on-resistances than their corresponding main blocking transistor. The resulting transient blocking unit characteristic has two or more different slopes in the negative differential resistance part of the circuit I-V characteristic. This piecewise linear behavior can be exploited to ensure that the circuit I-V characteristic only has a single intersection with a normal load characteristic. By satisfying this condition, automatic reset is ensured, because the combination of the transient blocking unit with any load that is consistent with the normal load characteristic will have only one stable operating point.

Abstract: The present disclosure discloses a radio frequency switching circuit including an antenna terminal, a transmitter terminal, a receiver terminal, a first switching module, a second switching module, a first switching component, and a second switching component. The first switching module is connected between the antenna terminal and the transmitter terminal. The second switching module is connected between the antenna terminal and the receiver terminal. The first and second switching modules include several transistors respectively, and each of the transistors includes a gate terminal, a drain terminal, a source terminal, and a bulk. The first switching component has a first anode terminal connecting with the gate terminal, and a first cathode terminal connecting with the drain terminal. The second switching component has a second anode terminal connecting with the gate terminal, and a second cathode terminal connecting with the source terminal.

Abstract: A VSC converter includes in each valve one first semiconductor device of turn-off type with a voltage blocking capacity rating of a first, high level and connected in parallel therewith a series connection of a plurality of second semiconductor devices of turn-off type with a voltage blocking capacity rating of a second, lower level. A control arrangement of the converter is configured to switch a said valve into a conducting state starting from a forward biased blocking state of the valve by controlling the second semiconductor devices to be turned on and then the first semiconductor devices to be turned on with a delay, and at the end of the conducting state to turn off the first semiconductor device in advance of turning the second semiconductor devices off.

Abstract: According to one embodiment, a resonant gate driver comprises a resonant path configured to couple a gate of a power transistor to a supply capacitor, and a low impedance path configured to couple the gate of the power transistor to a voltage rail. The resonant gate driver selectively utilizes the resonant path during charging and discharging of the gate, and selectively utilizes the low impedance path to couple the gate to the voltage rail when the gate is neither charging nor discharging. A method for use by the resonant gate driver for driving the power transistor comprises charging and discharging the gate of the power transistor by selectively coupling the gate to a supply capacitor through a resonant path, and utilizing a low impedance path to selectively couple the gate to a voltage rail when the gate is neither charging nor discharging.

Abstract: The present invention relates to a switch control circuit that controls a switching operation of a power switch circuit that includes cascode-coupled first and second transistors. A switch control circuit includes a first zener diode coupled between a gate of the first transistor and a first end of a capacitor supplying a power voltage and a second zener diode coupled to a gate and a source of the first transistor, and a first resistor coupled between the first zener diode and the second zener diode.

Abstract: N (n is an integer more than one) number of transistors are connected in series in an order from a first transistor to an nth transistor from a first terminal to a second terminal. First to nth nodes are connected to gates of the first to nth transistors. N number of resistance elements are connected in series in an order from a first resistance element to an nth resistance element from a bias terminal to the nth node. The first resistance element is connected between said bias terminal and said first node, and the kth resistance element (k=2 to n) is connected between the (k?1)th node and the kth node. Thus, a high frequency switch circuit can reduce an area of the whole gate bias resistances.

Abstract: A bi-directional switch circuit includes a pair of N-type MOS devices connected in series with a common source terminal, and a pair of P-type MOS devices connected in series with a common source terminal. The series connected N-type devices are connected in parallel with the series connected P-type devices in a configuration that includes a first input/output (I/O) point of the switch circuit being connected to a drain of a first one of the N-type devices and a drain of a first one of the P-type devices. The parallel configuration also includes a second I/O point of the switch circuit being connected to a drain of a second one of the N-type devices and a drain of a second one of the P-type devices.

Abstract: Disclosed herein are bias voltage generating circuits configured for switching power supplies, and associated control methods. In one embodiment, a bias voltage generating circuit can include: (i) a first control circuit configured to compare a drain-source voltage of a switch against a bias voltage; (ii) a capacitor, with the bias voltage across the capacitor; (iii) a second control circuit configured to control the switch, and that is enabled when the bias voltage is at least as high as an expected bias voltage; (iv) the first control circuit being configured to control the capacitor to charge when the drain-source voltage of the switch is greater than the bias voltage; and (v) the bias voltage being less than an overvoltage protection voltage when the capacitor charges, and where the overvoltage protection voltage comprises a voltage that is a predetermined amount higher than the expected bias voltage.

Abstract: An integrated switching device, such as an RF attenuator, can be controlled to be in various states according to control bits of a control signal. The integrated switching device can be gradually transitioned from one state to another by staggering the timing of changing the control bits. Latch-up problems in the integrated switching device can thereby be reduced or prevented.

Abstract: In one general aspect, an apparatus including a first voltage rail, and a second voltage rail. The apparatus includes a first P-type metal-oxide-semiconductor field effect transistor (MOSFET) PMOS device between the first voltage rail and the second voltage rail where the first PMOS device is configured to electrically couple the first voltage rail to the second voltage rail in response to the first PMOS device being activated. The apparatus can also include a second PMOS device configured to provide a charge pump voltage produced by a charge pump device to the second voltage rail in response to the second PMOS device being activated and the first PMOS device being deactivated. The apparatus can also include a pass gate, and a driver circuit coupled to the pass gate and configured to operate based on a voltage of the second voltage rail.

Abstract: A method for driving a field effect transistor for shaping an electrical signal, representing a sound, to an output signal is disclosed. The method comprises modifying the input signal to an intermediate signal, and output of the intermediate signal to the field effect transistor for shaping the output signal. The method comprises the steps of adjusting the quiescent point of the field effect transistor such that the same is placed in the quadratic region of the transfer characteristics of the field effect transistors, and adjusting the amplitude of the intermediate signal, such that the same causes the potential swing between the gate terminal and the source terminal to at least partly be in the quadratic region of the transfer characteristics of the field effect transistor.

Abstract: The present disclosure is generally directed to a plurality of solid state switches of varying periphery sizes connected in series between a power source and a load. A built-in test circuit senses an overvoltage condition across one or more of the varying periphery sizes and opens or closes the one or more of the varying periphery sizes in accordance with a measured voltage across at least one solid state switch of the plurality of solid state switches.

Abstract: A circuit is provided that includes a parasitic power circuit that powers a parasitic circuit. The parasitic power circuit derives a supply voltage from an external AC or other signal suitable for use as a communications signal. A PMOS transistor or transistors is utilized to enable a supply voltage capacitor to charge substantially to the same voltage as the channel voltage of the communications signal.

Abstract: A control circuit includes: a first switching element having a source, a gate, and a drain; a battery configured to supply a voltage to the gate through a second switching element; a PWM signal generator circuit configured to supply a PWM signal to the gate through a third switching element; and a gate control circuit configured to, under a power-off condition, turn on the second switching element to supply the voltage of the battery to the gate and turns off the third switching element, and configured to under a power-on condition, turn on the third switching element to supply the PWM signal voltage to the gate and turns off the second switching element.

Abstract: A switching circuit includes first and second switching elements arranged in parallel in an energization path, first and second gate driving lines, first and second fuses, and first and second abnormality detection portions capable of detecting abnormality in the switching elements. In the switching circuit, when abnormality in either one of the first and second switching elements is detected, the fuse between the first and second fuses which corresponds to the switching element in which abnormality is detected is turned into non-conduction state.

Abstract: A high-frequency semiconductor switch includes a serial-parallel conversion circuit, a power supply circuit, and a drive circuit. In the serial-parallel conversion circuit, a parallel data signal is formed from a serial data signal input thereto. In the power supply circuit, a first positive voltage, a second positive voltage, and a negative voltage are formed from a high-potential power source supplied thereto. The drive circuit is supplied with the first positive voltage, the second positive voltage, and the negative voltage, and includes an inverter to which the parallel data signal is input and a differential type of level shifter to which the parallel data signal and the output signal of the inverter is provided. The drive circuit outputs the second positive voltage as a high level signal, and the negative voltage as a low level signal, to a switching circuit, and the switching circuit performs selective switching based thereon.

Abstract: It is described a high efficiency rectification stage using dynamic threshold MOSFET. The idea is to use the input signal to reduce the threshold voltage when the transistor has to be on, and to increase the threshold when the transistor has to be off. This allows reducing both the resistive losses and the leakage current. A matching network allows the generation of a second higher voltage signal to drive the control gates and the bulk, i.e. the wells, of the transistors. Further, a self-tuned front-end is provided to extend the bandwidth of the high-Q charge pump.

Abstract: An output circuit providing isolation between inputs and the output employs first and second opto-couplers for isolation. Pulse activation of the first opto-coupler turns on an output transistor and pulse activation of the second opto-coupler turns off the output transistor. An input stage of the output circuit is and light emitting devices of the first and second opto-couplers are powered by a first power source and an output stage of the output circuit is powered from an external power source. Power consumption by the input stage of output circuit occurs only during pulse activation of the first and second opto-couplers.

Abstract: An RF switch circuit for switching RF signals includes a first terminal and a second terminal and a series connection of a plurality of transistors between the first terminal of the RF switch circuit and the second terminal of the RF switch circuit. Furthermore, the RF switch circuit includes a control circuit configured to conductively couple, in a high impedance state of the RF switch circuit, the first terminal of the RF switch circuit to a control terminal of a first transistor in a series of the series connection of the plurality of transistors. The second terminal of the RF switch circuit is conductively coupled to a control terminal of a last transistor in the series of the series connection of the plurality of transistors.

Abstract: An analog to digital converter comprising at least one sampling capacitor connected to a sample node, and a pre-charge circuit arranged to cause the voltage on the sample node to substantially match the input voltage prior to the analog to digital converter entering an acquire mode in which the sample node is connected to the input node by a sample switch.

Abstract: A coupling circuit has a first and a second transistor (P1, P2) of a p-channel field-effect transistor type. A drain terminal of the first transistor (P1) is connected to a signal input (1), source terminals of the first and the second transistor (P1, P2) are commonly connected to a signal output (2), bulk terminals of the first and the second transistor (P1, P2) are commonly connected to a drain terminal of the second transistor (P2), and a gate terminal of the first transistor (P1) is connected to a gate terminal of the second transistor (P2). The coupling circuit further comprises a gate control circuit (10) with a charge pump circuit (110) which is configured to generate a negative potential. The gate control circuit (10) is configured to control a gate voltage at the gate terminals of the first and the second transistor (P1, P2) based on a negative potential.

Abstract: The transistor suffers the variation caused in threshold voltage or mobility due to gathering of the factors of the variation in gate insulator film resulting from a difference in manufacture process or substrate used and of the variation in channel-region crystal state. The present invention provides an electric circuit having an arrangement such that both electrodes of a capacitance element can hold a gate-to-source voltage of a particular transistor. The invention provides an electric circuit having a function capable of setting a potential difference at between the both electrodes of the capacitance element by the use of a constant-current source.

Abstract: A driving circuit has output terminal connected to an ultrasonic transducer and provides an output voltage. The driving circuit includes an output transistor coupled between a voltage reference and the output terminal, a high voltage comparator coupled to said output terminal and to a threshold voltage reference), a start-up circuit controlled by a setting signal; and a switching ON/OFF circuit having an input coupled to the start-up circuit an input coupled to the comparator, and an output coupled to a control terminal of the output transistor. The start-up circuit provides an ON signal to the switching on/off circuit and the comparator provides an OFF signal to the switching on/off circuit which switches off the output transistor. The high voltage comparator generates the switching off signal in response to the output voltage reaching a desired supply voltage value which depends on the value of the first threshold voltage reference.

Abstract: A radio frequency (RF) switch includes a common port, a first port, and a second port, a first semiconductor switching element disposed in a first RF pathway between the common port and the first port, a second semiconductor switching element disposed in a second RF pathway between the common port and the second port, a first pair of direct current (DC) blocking capacitors disposed to isolate the first semiconductor switching element in the first RF pathway, and a second pair of DC blocking capacitors disposed to isolate the second semiconductor switching element in the second RF pathway. The respective pairs of DC blocking capacitors allow for different bias voltages to be applied to the respective RF pathways. A charge-discharge circuit may also be employed to decrease transient switching time of the RF switch.

Abstract: An integrated circuit comprising at least one MOS-type transistor, further comprising a system for detecting the variations of the electrical quantities of the at least one transistor, and a biasing device modifying the bias voltage of the bulk of the at least one transistor according to the variations measured by the detection system.