Abstract: An integrated circuit is provided with a low-power island including embedded memory power domains that may selectively couple to either an active-mode power supply voltage supplied on a first power rail or to a sleep-mode power supply voltage supplied on a second power rail.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract: An electronic device can include a bidirectional HEMT. In an aspect, a packaged electronic device can include the bidirectional HEMT can be part of a die having a die substrate connection that is configured to be at a fixed voltage, electrically connected to drain/source or source/drain depending on current flow through the bidirectional HEMT, or electrically float. In another aspect, the electronic device can include Kelvin connections on both the drain/source and source/drain side of the circuit. In a further embodiment, a circuit can include the bidirectional HEMT, switch transistors, and diodes with breakdown voltages to limit voltage swings at the drain/source and source/drain of the switch transistors.

Abstract: A method includes detecting current from a first terminal of the switch to a second terminal of the switch, wherein the current exceeds a current limit for a linear region of the switch. The method includes controlling a gate voltage of the switch from a first voltage to a second voltage. The second voltage is configured to enable the switch to operate in an active region of the switch. The method further includes opening the switch when the switch is operating in the active region.

Abstract: A driving device includes a switching circuit configured to have switching elements disposed on a high side and a low side, the switching element including a first electrode, a second electrode, and a reverse conducting element disposed between the first electrode and the second electrode; and a determination part configured to determine whether to permit the switching element to turn on, based on a result obtained by detecting a voltage between the first electrode and the second electrode, in a period during which the switching elements on both sides are off.

Abstract: A switch and a multiplexer including the same are provided, which are applicable to selectively transmit the high frequency signal from an input terminal to an output terminal therethrough. The switch includes a switch device and a variable resistor. The switch device is connected between the input terminal and the output terminal, and the switch device includes a control terminal and is configured to be switched between ON and OFF according to a switch controlling signal provided to the control terminal. The variable resistor is connected to the control terminal and configured to change to a first resistance while the switch device is ON, and to change to a second resistance while the switch device is OFF according to a resistor controlling signal. The first resistance is higher than the second resistance, and the resistor controlling signal is changed corresponding to the switch controlling signal.

Abstract: A power module includes: a base plane; at least one switch chip assembled on the base plane; and a voltage clamping circuit for clamping a voltage spike occurring on the at least one switch chip, comprising components of a charging loop, wherein the components of the charging loop at least comprise a capacitor, wherein a projection of a center point of at least one of the components of the charging loop on the base plane is located within at least one first circle, defined with a center of the first circle being a center point of the at least one switch chip, and with a radius of the first circle being a product of a maximum one of a length and a width of the at least one switch chip and a first coefficient, which is a multiple of 0.5.

Abstract: A control circuitry (134) and a method for controlling a bi-directional switch (132) is provided. The bi-directional switch (132) having a control terminal (130) for receiving a control voltage (124) to control an on state and an off state of the bi-directional switch (132) and at least one semiconductor switch in a bi-directional main current path. The control circuitry (134) comprises an energy storage element (102), a coupling means (101) to couple the energy storage element (102) to a supply voltage to charge the energy storage element (102), and a control circuit (108) configured to receive power from the energy storage element (102) and pendent of the supply voltage when the emergency storage element (102) is not coupled to the supply voltage. The coupling means (101) is configured for only coupling the energy storage element (102) to the supply voltage when the bi-directional switch (132) is in the off state.

Abstract: A semiconductor device includes a transistor; a diode configured to be connected in reverse-parallel with the transistor; a sense transistor configured to generate a sense current depending on a current flowing in the transistor; a sense diode configured to generate a sense diode current depending on a current flowing in the diode; a resistor part configured to have one terminal connected with an emitter of the sense transistor and an anode of the sense diode, and another terminal connected with an emitter of the transistor and an anode of the diode, and to have the sense current or the sense diode current flow in the resistor part; and a resistance value control unit configured to differentiate a resistance value of the resistor part for a case where the sense current flows in the resistor part, and for a case where the sense diode current flows in the resistor part.

Abstract: An power voltage generating unit for a radio frequency switch includes a first input and a second input respectively configured to receive a first control signal and a second control signal, wherein the first control signal and the second control signal are configured to control which one of a plurality of paths in the radio frequency switch is enabled, and at least one output, configured to output an auxiliary voltage, derived from at least one of the first control signal or the second control signal, that is used to operate the radio frequency switch. The power voltage may be a voltage used to power an inverting circuit used to enable a selected branch as an isolation branch or shunt branch.

Abstract: In a driver, a clamping module executes a clamping task that clamps an on-off control terminal voltage to be equal to or lower than a clamp voltage for a predetermined time during charging of the on-off control terminal of the switching element. The clamp voltage is lower than an upper limit of the voltage at the on-off control terminal of the switching element. A measuring module measures a parameter value correlated with a sense current correlated with a current flowing between input and output terminals of the switching element. A limiting module discharges the on-off control terminal to limit flow of the current between the input and output terminals if the value of the parameter exceeds a threshold. A setting module variably sets a length of the predetermined time as a function of the parameter value during charging of the switching element's on-off control terminal.

Abstract: A snubber circuit includes a current-variation suppressor, a voltage-variation suppressor, a retrieving circuit, and a discharging circuit. The current-variation suppressor is connected between a bridge circuit and a power supply and reduces current variation when switches in the bridge circuit are controlled. The voltage-variation suppressor is parallel to the switches and reduces voltage variation when the switches are controlled. The retrieving circuit transfers energy stored in the current-variation suppressor when the switches are controlled to the voltage-variation suppressor. The discharging circuit discharges energy stored in the voltage-variation suppressor when the switches are controlled to an AC side of the bridge circuit when the semiconductor switches are controlled.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device is a half bridged field effect transistor having a monolithic chip, and includes a semiconductor substrate with a 2-dimensional electron gas layer formed therein; a drain electrode formed on the semiconductor substrate; a first gate electrode, an output electrode, a second gate electrode, and a source electrode. The method of manufacturing the semiconductor device uses a method of monolithically forming a stack structure, which implements a half bridge function, on a substrate according to semiconductor processes.

Abstract: Example current tracking circuits and systems as well as methods for tracking current are described herein. In one example, a current tracking circuit comprises a current mirror that receives a power supply input and a control signal as inputs, wherein the current mirror has a mirror ratio. The current tracking circuit also comprises a programmability sub-circuit coupled to the current mirror that trims a value of the mirror ratio. In another example, a method comprises performing current mirroring using a current mirror comprising a sense device, wherein a mirror ratio of the current mirror is based on a programmable sub-circuit. The method further comprises maintaining, by a voltage regulation loop, a collector potential of the sense device within a threshold difference level of a collector potential of a power device coupled to the sense device, wherein the sense device mirrors a current flowing in the power device.

Abstract: A cascode circuit (1) is provided with a switching element (Q1) which is normally off by default, a switching element (Q2) and a clamp circuit (10). A source of the switching element (Q2) is connected to a drain of the switching element (Q1). The cascode circuit (1) engages in a normally-off operation through a gate driving circuit (100) connected to a gate of the switching element (Q1). The clamp circuit (10) is provided between a power source terminal (P) of the gate driving circuit (100) and the drain of the switching element (Q1). A power source (E) is connected to the power source terminal (P). When the gate driving circuit (100) operates to turn off the switching element (Q1) and the switching element (Q2), the clamp circuit (10) clamps a voltage between the drain and the source of the switching element (Q1) to a power source voltage (V) supplied from the power source (E).

Abstract: Systems, apparatuses and methods for reduced OFF capacitance in switching devices are disclosed. A semiconductor die may include a semiconductor substrate, first and second elongated doped regions, said first region serving as a source of a first transistor, said second region serving as a drain of the first transistor and a source of a second transistor. The semiconductor die further includes a plurality of elongated gate structures including a first gate structure disposed between the first and second regions and serving as a gate of the first transistor. The semiconductor die further includes a first set of evenly-spaced electrical contact pads disposed on the first region, and a second set of evenly-spaced electrical contact pads disposed on the second region, the second set of contact pads being offset with respect to the first set of contact pads in a longitudinal direction of the first and second regions.

Abstract: A semiconductor device includes a circuit block that is switchable between selection and non-selection, and a leakage current control circuit disposed between the circuit block and a first power supply line. The leakage current control circuit includes a first transistor disposed between the circuit block and the first power supply line, and a resistor device disposed between the circuit block and the first power supply line.

Abstract: An induction heating cooker is provided. The induction heating cooker may include a rectifier to rectify an input voltage into a direct current (DC) voltage and output the DC voltage, an inverter to generate an alternating current (AC) voltage by switching the DC voltage, a first heater driven by the AC voltage so as to heat a first cooking container, a second heater connected in parallel to the first heater, and driven by the AC voltage so as to heat a second cooking container, and a switching controller configured to output a switching signal to the inverter for controlling the first and second heaters in accordance with a selected operation mode. The selected operation mode may be a first operation mode for driving only the first heater, a second operation mode for driving only the second heater, or a third operation mode for driving both the first and second heaters at the same time.

Abstract: A drive device according to one aspect of the disclosure includes a control terminal connector, a switch circuit, a current limit circuit, and a clamp switch on a circuit board. The clamp switch is located in a second quadrant or a fourth quadrant of four quadrants, where the four quadrants are partitioned by two mutually orthogonal virtual lines with the current limit circuit set as an origin and the four quadrants consist of a first quadrant including an area where the control terminal connector is located, the second quadrant, a third quadrant, and the fourth quadrant, in clockwise order.

Abstract: A power circuit for an electronic device includes an input terminal, an output terminal, a voltage transform unit, and a control unit. The control unit controls the voltage transform unit to operate or not operate, according to the input terminal receives a first voltage or a second voltage. The first voltage is transformed to an output voltage, and is output by the output terminal, when the input terminal receives the first voltage. The second voltage is transmitted from the input terminal to the output terminal through the third switch unit, when the input terminal receives the second voltage. Therefore, the power circuit can receive the first voltage or the second voltage through the input terminal, and outputs the output voltage to other electronic components.

Abstract: A semiconductor apparatus includes a switching element configured to include a gate electrode, a first main electrode, a second main electrode, a sense electrode to output a sense current smaller than a principal current depending on the principal current flowing in the first main electrode, and to turn off when a control voltage being applied between the gate electrode and the first main electrode is reduced; a sense diode configured to include an anode connected with the sense electrode, and a cathode connected with the second main electrode; and a connection circuit configured to connect the gate electrode with the sense electrode when the switching element turns off.

Abstract: Radio-frequency (RF) devices are disclosed providing reduced intermodulation distortion. Disclosed RF and semiconductor devices can include a semiconductor substrate, a switch formed on the semiconductor substrate having a stack of field-effect transistors (FETs) connected in series, and a capacitor formed on the semiconductor substrate and connected in series with the switch, the capacitor configured to inhibit a low-frequency blocker signal from mixing with a fundamental-frequency signal in the switch.

Abstract: Provided is a switch circuit capable of reliably controlling the transmission or interruption of a voltage of from GND to VDD to an internal circuit even when a positive or negative voltage is input to an input terminal. By adding PMOS transistors to NMOS transistors constituting the switch circuit and controlling gates of the PMOS transistors by a voltage of the input terminal, the transmission or interruption of the voltage of from GND to VDD can be reliably controlled.

Abstract: A current limiting circuit is electronically connected between a power source and a load, and comprises a MOSFET having a drain, a gate, and a source, a first operational amplifier, a voltage-limiting circuit, and a first transistor having an emitter, a base, and a collector. The drain is connected to the power source, the source is connected to the load and is grounded, and the gate is connected to the voltage-limiting circuit. The emitter is connected to the voltage-limiting circuit, the base is connected to the first operational amplifier, and the collector is grounded. The first operational amplifier detects an output voltage of the load to control a drain current of the MOSFET for protecting the MOSFET from being overloaded, and the current limiting circuit has no current limiting resistor, such that power consumption is reduced.

Abstract: A D/A converter is configured to output tri-level potentials from an output terminal. A high potential terminal and the output terminal are connected through a p-type MOS transistor. An intermediate potential terminal and the output terminal are connected through p-type and n-type MOS transistors, which are connected in series and have low threshold voltages. A low potential terminal and the output terminal are connected through an n-type MOS transistor. The p-type MOS transistor and the n-type MOS transistor connected to the Intermediate potential terminal have a positive voltage and a negative voltage between gate-source paths in off-states, respectively, and a substrate bias effect and hence remain in the off-state stably.

Abstract: The present subject matter relates to systems and methods for arranging and controlling programmable combinations of tuning elements in which more than one form of switching technology is combined in a single array. Specifically, such an array can include one or more first switchable elements including a first switching technology (e.g., one or more solid-state-controlled devices) and one or more second switchable elements including a second switching technology that is different than the first switching technology (e.g., one or more micro-electro-mechanical capacitors). The one or more first switchable elements and the one or more second switchable elements can be configured, however, to deliver a combined variable reactance.

Abstract: An aircraft power distribution network comprising first and second galvanically isolated power bus bars, and first and second remote data concentrators (RDCs), each RDC having an input/output interface (I/O) and a power supply, the first RDC power supply being connected to the first power bus bar, the second RDC power supply being connected to the second power bus bar, an input/output device being connected to the I/O of the first RDC and to the I/O of the second RDC, each RDC being adapted to supply electrical power to the input/output device through its respective I/O, wherein each RDC includes a switch for isolating the input/output device, and the switches being operatively coupled such that electrical power cannot be supplied to the input/output device by both RDCs simultaneously. Also, a method of operating the network.

Abstract: An electronic switch includes a load path connected in series with the load and a drive terminal for receiving a drive signal. The electronic switch is operable to switch between a first operation state and a second operation state dependent on the drive signal. In a first switching cycle, the electronic switch is switched from the first operation state to the second operation state and a voltage across the load is evaluated during the first switching cycle in order to obtain a measured switching profile. The measured switching profile is compared with a reference profile. A drive profile dependent on the comparison is provided. The drive profile is used to drive the electronic switch in a second switching cycle after the first switching cycle. At least two drive parameters are used at different times in the at least one second switching cycle to drive the electronic switch.

Abstract: An envelope detector circuit, suitable for use in RFID tags, includes a voltage doubler circuit and a biasing voltage generating circuit which comprises components matched respectively to rectifying components of the voltage doubler circuit. A rectifying component of this voltage doubler circuit is formed by a transistor controlled by the biasing voltage generating circuit which provides a biasing voltage to a control gate of this transistor, the biasing voltage generating circuit being arranged so as to permit a determined forward biasing current to flow through the transistor and further rectifying elements of the voltage doubler circuit. This embodiment provides fast, highly sensitive detection of envelope waveforms in input signals. Thanks to the matched rectifying components, efficiency variations due to variations in manufacturing process can be eliminated. The envelope detector circuit is further arranged for maintaining a stable detection independent of variations in temperature.

Abstract: A switching circuit is electrically coupled between a connection terminal and an output terminal of a transmission channel and includes first and second switching transistors electrically coupled in series to each other and having respective body diodes in anti-series, between the connection terminal and the output terminal. The switching circuit comprises a bootstrap circuit connected to respective first and second control terminals of these first and one second switching transistors, as well as to respective first and second voltage references. The bootstrap circuit includes a first parasitic capacitance electrically coupled between the first control terminal and a first bootstrap node, and a second parasitic capacitance electrically coupled between the second control terminal and a second bootstrap node. The parasitic capacitances have value of at least one order of magnitude lower with respect to the gate-source capacitances of the first and second switching transistors.

Abstract: An impedance matching switch circuit module includes a first switch device connected to first and second high-frequency input/output terminals, a second switch device connected between the first high-frequency input/output terminal and a first matching terminal, and a third switch device connected between the second high-frequency input/output terminal and a second matching terminal. Impedance matching elements having appropriately set element values (inductances or capacitances) are connected to the first and second high-frequency input/output terminals and the first and second matching terminals, and on/off control is performed for the first, second, and third switch devices.

Abstract: A switching mode power supply apparatus is provided. The switching mode power supply apparatus may include a switch unit configured to switch an input voltage to a transformer and a controller configured to select an operation mode having a switching frequency according to a size of a load applied to a secondary side of the transformer and control a switching operation of the switch unit. The switching mode power supply apparatus may include a transformer. A refrigerator having the switching mode power supply apparatus is also provided.

Abstract: Devices for isolating an input from an output are disclosed. For example, a device includes a first p-type metal oxide semiconductor transistor and a first circuit. A source of the first p-type metal oxide semiconductor transistor is connected to an input of the device. The first circuit is for delivering a signal on the input of the device to a gate of the first p-type metal oxide semiconductor transistor when an enable signal is deactivated and for delivering a ground voltage to the gate of the first p-type metal oxide semiconductor transistor when the enable signal is activated.

Abstract: A high-frequency switching circuit includes a high-frequency switching transistor, wherein a high-frequency signal-path extends via a channel-path of the high-frequency switching transistor. The high-frequency switching circuit includes a control circuit and the control circuit is configured to apply at least two different bias potentials to a substrate of the high-frequency switching transistor, depending on a control signal received by the control circuit.

Abstract: An element can be prevented from being damaged even when a high level signal is input to an integrated circuit having a variable capacitance element whose capacitance is variable by digital signal control. There is provided an integrated circuit including b sub-circuits (b is an integer equal to or greater than 1) that are connected in series between a first terminal and a second terminal and have capacitance 2b-1 times larger than predetermined unit capacitance. The b-th sub-circuit includes 2b-1 configurations, which are connected in parallel, each including at least two capacitors connected in series and at least two stacked switch elements. At least the two stacked switch elements are operated to all switched for each sub-circuit, and at least one switch element of at least the two stacked switch elements is provided between at least the two capacitors.

Abstract: A semiconductor device in which operation delay due to stop and restart of the supply of a power supply potential is suppressed is provided. Potentials corresponding to data held in first and second nodes while the supply of a power supply potential is continued are backed up in third and fourth nodes while the supply of the power supply potential is stopped. After the supply of the power supply potential is restarted, data are restored to the first and second nodes by utilizing a change in channel resistance of a transistor whose gate is electrically connected to the third or fourth node. Note that shoot-through current is suppressed at the time of data restoration by electrically disconnecting the power supply potential and the first or second node from each other.

Abstract: A control circuit for a switch, configured to measure the drain-to-source current of the switch is described. The control circuit is configured to control an external transistor and comprises a control pin coupled to the gate of an external transistor. The external transistor and a level shifting unit are coupled to the control pin and configured to isolate an AC current from the control pin; at a time instant subsequent to the first pulse duration, the isolated AC component of the voltage potential is indicative of a drain-to-source current through the external transistor.

Abstract: Aspects of the invention are directed to a gate driving circuit for a power conversion circuit having an upper and lower arm circuit composed of series-connected upper arm and a lower arm, each arm including two or more semiconductor switching devices connected in series. In some aspects, a gate driving circuit of the invention includes a circuit of series connection including a diode and a resistor between a positive potential side of a positive side power supply and a positive electrode side. The gate driving circuit can determine a short-circuit fault of the semiconductor switching device that is connected to the gate driving circuit by detecting the current that flows through the circuit of series connection including the diode and the resistor when an OFF command of ON/OFF command signals is given to the semiconductor switching device.

Abstract: A power semiconductor device module includes a plurality of inverters, each having a first transistor and a second transistor that are interposed in series between a first potential and a second potential and that operate complementarily. The plurality of inverters are assembled into a module. Only one predetermined inverter of the plurality of inverters is configured to detect temperatures of the first and second transistors, and control terminals for detection of the temperatures of the first and second transistors protrude from sides of the module.

Abstract: In an embodiment, a gate driver circuit and/or method therefor may include configuring the gate driver circuit form a drive current to supply to a gate of an MOS transistor wherein the value of the drive current is a minimum value that can be supplied to the gate without increasing a charge stored on a gate-to-source capacitance of the MOS transistor; configuring the gate driver circuit to change the value of the drive current responsively to changes of a Vgs of the MOS transistor.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: A method and apparatus for repairing transistors may include applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time. In this manner the transistor structure may be repaired or returned to operate at or near the original operating characteristics.

Abstract: A semiconductor device prevents recognition failure in mutual recognition between a host and a device compliant with USB Specifications. The semiconductor device includes: an interterminal opening/closing section having a plurality of first conductivity type MOS transistors, the respective sources or drains of which are cascaded, in which the source or drain of a first-stage MOS transistor among the cascaded MOS transistors is used as a first terminal, the source or drain of a final-stage MOS transistor among the cascaded MOS transistors is used as a second terminal, and the respective gates of the cascaded MOS transistors receive a control signal for controlling the opening or short-circuiting between the first and second terminals; and a current bypass section that reduces a current flowing into either one connection node coupling the respective sources or drains of the cascaded MOS transistors.

Abstract: An electronic apparatus includes a switching element which has a control terminal and is driven by controlling voltage of the control terminal, a driving power supply circuit which supplies voltage required for driving the switching element, an on-driving circuit which is connected to the driving power supply circuit and the control terminal of the switching element and is supplied with voltage from the driving power supply circuit, and which applies a constant current to the control terminal of the switching element to charge the control terminal, thereby turning on the switching element, and at least one diode which is connected between the on-driving circuit and the control terminal of the switching element. The on-driving circuit applies a constant current to the control terminal of the switching element through the diode.

Abstract: A circuit arrangement includes a first semiconductor device having a load path and a number of second semiconductor devices. Each second semiconductor device has a control terminal and a load path between a first load terminal and a second load terminal. The second semiconductor devices have their load paths connected in series and connected in series with the load path of the first semiconductor device. Each of the second semiconductor devices has a load terminal of one of the first semiconductor device and of one of the second semiconductor devices associated thereto and a voltage limiting element coupled between the control terminal of one of the second semiconductor devices and the load terminal associated with that one of the second semiconductor devices.

Abstract: There is provided a high frequency switch having a reduced circuit scale while maintaining satisfactory harmonic characteristics in a transfer path of a high frequency signal. The high frequency switch includes: at least one transmission port; at least one reception port; a common port; transmission side series switches each including a body contact type FET; transmission side shunt switches each including a body contact type FET; reception side series switches each including a body contact type FET; and reception side shunt switches each including at least one floating body type FET.

Abstract: Contrary to phase shifters which require complimentary polarity control voltages, a phase shifter may be driven with a single polarity control voltage. The phase shifter comprises an input node in communication with both a high pass network and a low pass network which are both in communication with an output node, where the phase shifter further comprises a first single pole double throw switch and a second single pole double throw switch configured to selectively pass an RF signal from the input node to the output node by way of one of said high pass network and said low pass network. Furthermore, the first and second single pole double throw switches are configured to select between the high pass network and the low pass network based on a single control signal having a voltage greater than or less than a reference voltage.

Abstract: A calibration system may be provided for calibrating wireless communications circuitry in an electronic device during manufacturing. The calibration system may include data acquisition equipment and calibration computing equipment for receiving and processing test and calibration signals from wireless communications circuitry to be calibrated. During testing and calibration operations, a device may be provided with initial pre-distortion calibration values. The initial pre-distortion calibration values may be generated at least in part based on calibration operations performed for other wireless electronic devices. The device may generate a test signal using the initial pre-distortion calibration values. The calibration system may determine whether the test signal is within an acceptable range of a known reference signal.

Abstract: Various embodiments of circuits configured to improve second order harmonic distortion of Metal Oxide Semiconductor (MOS) transistors operating in linear region are provided. In one embodiment, a circuit includes an averaging circuit configured to average signals at a drain and a source of a MOS transistor and provide the averaged signal to a gate of the MOS transistor, and one or more current sources coupled with the gate; the circuit is configured to vary voltage at the gate so as to vary a resistance of the MOS transistor. The averaging circuit comprises a first MOS circuit coupled between the drain and the gate, a first capacitor coupled in parallel to the first MOS circuit between the drain and the gate, a second MOS circuit coupled between the source and the gate, and a second capacitor coupled in parallel to the second MOS circuit between the source and the gate.

Abstract: A driver circuit for driving a power transistor includes a converter having a first transistor and a second transistor coupled in series between a supply node and a reference node. The converter is configured to receive a first signal and in response thereto generate a second signal for selectively controlling status of the power transistor. The ratio of a first leakage current of the first transistor to a second leakage current of the second transistor is used in the generation of the second signal which is applied to the control terminal of a transistor switch that is selectively actuated to turn off the power transistor.